Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628196
Yuan Bing, Lai Xin-quan, Ye Qiang, Wang Hongyi, L. Yajun
A soft-start circuit with soft-recovery function for DC-DC converters is presented in this paper. The soft-start strategy is based on a linearly ramped-up reference and an error amplifier with minimum selector implemented with a three-limb differential pair skillfully. The soft-recovery strategy is based on a compact clamp circuit. The ramp voltage would be clamped once the feedback voltage is detected lower than a threshold, which could control the output to be recovered slowly and linearly. A monolithic DC-DC buck converter with proposed circuit has been fabricated with a 0.5μm CMOS process for validation. The measurement result shows that the ramp-based soft-start and soft-recovery circuit have good performance and agree well with the theoretical analysis.
{"title":"Ramp-based soft-start circuit with soft-recovery for DC-DC buck converters","authors":"Yuan Bing, Lai Xin-quan, Ye Qiang, Wang Hongyi, L. Yajun","doi":"10.1109/EDSSC.2013.6628196","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628196","url":null,"abstract":"A soft-start circuit with soft-recovery function for DC-DC converters is presented in this paper. The soft-start strategy is based on a linearly ramped-up reference and an error amplifier with minimum selector implemented with a three-limb differential pair skillfully. The soft-recovery strategy is based on a compact clamp circuit. The ramp voltage would be clamped once the feedback voltage is detected lower than a threshold, which could control the output to be recovered slowly and linearly. A monolithic DC-DC buck converter with proposed circuit has been fabricated with a 0.5μm CMOS process for validation. The measurement result shows that the ramp-based soft-start and soft-recovery circuit have good performance and agree well with the theoretical analysis.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130546807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628149
R. Ma, Li Wang, Chen Zhang, Fei Lu, Z. Dong, Albert Z. H. Wang, Wei Lu, Yonghua Song, B. Zhao
This paper discusses a practical technique to accurately correlate package level ESD protection results by HBM (human body model) zapping and TLP (transmission line pulsing) testing. It is found that the ESD pulse duration plays a key role in correlating HBM and TLP testing results as verified by evaluating 40V-5V DC-DC convertor ICs.
{"title":"TLP and HBM ESD test correlation for power ICs","authors":"R. Ma, Li Wang, Chen Zhang, Fei Lu, Z. Dong, Albert Z. H. Wang, Wei Lu, Yonghua Song, B. Zhao","doi":"10.1109/EDSSC.2013.6628149","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628149","url":null,"abstract":"This paper discusses a practical technique to accurately correlate package level ESD protection results by HBM (human body model) zapping and TLP (transmission line pulsing) testing. It is found that the ESD pulse duration plays a key role in correlating HBM and TLP testing results as verified by evaluating 40V-5V DC-DC convertor ICs.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129181715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628092
N. Singh, N. H. Hamid, V. Asirvadam
As CMOS scales further into non-CMOS technology, being able to measure reliability of modern logic integrated circuits instantly and correctly is fast becoming necessary. Therefore, reliability assessment has become a decisive step in the design methodology of nano-sized circuit systems. In contemporary to current literature, the existing reliability assessment tool based on Probabilistic Gate Model (PGM) and Boolean Difference-error Calculator (BDEC) techniques works manually, thus making the process of computing reliability very intractable and time consuming. For an instant reliability measure, this paper firstly looks into the development of an automated reliability assessment tool based on the generalization of PGM and BDEC techniques. The Matlab-based tool allows users to speed-up the task of reliability analysis for large number of nano-based electronic circuits. Secondly, by using the developed automated tool, the work explores into the correctness of BDEC compared to PGM in assessing reliability of same functionality nano-based circuits. The reliability analysis shows that BDEC gives correct and transparent reliability measures, but as the complexity of the same functionality circuits with respect to gate error increases, BDEC tends to be more inferior in the reliability measure compared to PGM. The lower reliability measures by BDEC is well explained in this paper using distribution of different signal input patterns overtime for same functionality circuits. Simulation results conclude that the reliability measure by BDEC does not only depend on faulty gates but it also depends on circuit, probability of input signals being one or zero and probability of error on signal lines.
{"title":"Correctness of BDEC compared to PGM in assessing reliability of nano-based circuits","authors":"N. Singh, N. H. Hamid, V. Asirvadam","doi":"10.1109/EDSSC.2013.6628092","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628092","url":null,"abstract":"As CMOS scales further into non-CMOS technology, being able to measure reliability of modern logic integrated circuits instantly and correctly is fast becoming necessary. Therefore, reliability assessment has become a decisive step in the design methodology of nano-sized circuit systems. In contemporary to current literature, the existing reliability assessment tool based on Probabilistic Gate Model (PGM) and Boolean Difference-error Calculator (BDEC) techniques works manually, thus making the process of computing reliability very intractable and time consuming. For an instant reliability measure, this paper firstly looks into the development of an automated reliability assessment tool based on the generalization of PGM and BDEC techniques. The Matlab-based tool allows users to speed-up the task of reliability analysis for large number of nano-based electronic circuits. Secondly, by using the developed automated tool, the work explores into the correctness of BDEC compared to PGM in assessing reliability of same functionality nano-based circuits. The reliability analysis shows that BDEC gives correct and transparent reliability measures, but as the complexity of the same functionality circuits with respect to gate error increases, BDEC tends to be more inferior in the reliability measure compared to PGM. The lower reliability measures by BDEC is well explained in this paper using distribution of different signal input patterns overtime for same functionality circuits. Simulation results conclude that the reliability measure by BDEC does not only depend on faulty gates but it also depends on circuit, probability of input signals being one or zero and probability of error on signal lines.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123881056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628135
S. Panigrahi, M. Baghini, U. Gogineni, F. Iravani
Super junction (SJ) is one of the emerging principles used in high-voltage high-power semiconductor devices. Implementation of SJ principle with charge balance in the pillars has overcome the “Silicon-limit”. SJ principle demands formation of back-to-back reverse biased p-n pillars. Main technology constraint is formation of narrow pillars with high aspect ratio and charge imbalance in these pillars. We propose a method to obtain high breakdown voltage in planar SJ-LDMOS by reducing the effect of charge imbalance at the drain end without reducing width of the pillars and no significant change in ION. The breakdown voltage of 120 V in a HV CMOS technology with tox of 13nm is achieved without ION degradation, as compared to 100 V conventional LDMOS device.
{"title":"120 V super junction LDMOS transistor","authors":"S. Panigrahi, M. Baghini, U. Gogineni, F. Iravani","doi":"10.1109/EDSSC.2013.6628135","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628135","url":null,"abstract":"Super junction (SJ) is one of the emerging principles used in high-voltage high-power semiconductor devices. Implementation of SJ principle with charge balance in the pillars has overcome the “Silicon-limit”. SJ principle demands formation of back-to-back reverse biased p-n pillars. Main technology constraint is formation of narrow pillars with high aspect ratio and charge imbalance in these pillars. We propose a method to obtain high breakdown voltage in planar SJ-LDMOS by reducing the effect of charge imbalance at the drain end without reducing width of the pillars and no significant change in ION. The breakdown voltage of 120 V in a HV CMOS technology with tox of 13nm is achieved without ION degradation, as compared to 100 V conventional LDMOS device.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126478658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628189
Tao Yang, Wei Li, Xing’ao Li, Wei Huang, H. Ho, Qian-jin Wang, Yong‐yuan Zhu
We present a novel compact optical spectrometer in which the transmission characteristics of a silica nanoparticle coating may be used for analyzing the spectral contents of an incident beam.
{"title":"Novel integrated optical microspectrometer using silica nanoparticles","authors":"Tao Yang, Wei Li, Xing’ao Li, Wei Huang, H. Ho, Qian-jin Wang, Yong‐yuan Zhu","doi":"10.1109/EDSSC.2013.6628189","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628189","url":null,"abstract":"We present a novel compact optical spectrometer in which the transmission characteristics of a silica nanoparticle coating may be used for analyzing the spectral contents of an incident beam.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128065131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628143
Hoi Lee, Zhe Hua
Switched-capacitor (SC) power converters that use capacitors as energy storage elements offer much better power density than switched-inductor counterparts and are thus attractive in low-power area-constrained applications. This paper first reviews the importance of having auto-reconfigurable conversion ratios in the SC power stage in order to enable the regulator to maintain high power efficiency under unstable input voltages. To minimize the required capacitors and power switches in SC power converters, multiple-output SC power regulators can share capacitors and power switches in the power stage for generating multiple regulated outputs and thus improving the converter area efficiency. To simultaneously illustrate above concepts, an auto-reconfigurable dual-output SC power regulator is developed to generate two outputs while saving 1 flying capacitor and 3 power switches compared with using two independent single-output doubler and tripler. The proposed regulator has minimal cross regulation between outputs and achieves a maximum power efficiency of 88% via auto-reconfiguration when the input voltage varies from 1.1V to 1.6V.
{"title":"Power- & area-efficiency enhancement techniques of switched-capacitor power converters for low-power applications","authors":"Hoi Lee, Zhe Hua","doi":"10.1109/EDSSC.2013.6628143","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628143","url":null,"abstract":"Switched-capacitor (SC) power converters that use capacitors as energy storage elements offer much better power density than switched-inductor counterparts and are thus attractive in low-power area-constrained applications. This paper first reviews the importance of having auto-reconfigurable conversion ratios in the SC power stage in order to enable the regulator to maintain high power efficiency under unstable input voltages. To minimize the required capacitors and power switches in SC power converters, multiple-output SC power regulators can share capacitors and power switches in the power stage for generating multiple regulated outputs and thus improving the converter area efficiency. To simultaneously illustrate above concepts, an auto-reconfigurable dual-output SC power regulator is developed to generate two outputs while saving 1 flying capacitor and 3 power switches compared with using two independent single-output doubler and tripler. The proposed regulator has minimal cross regulation between outputs and achieves a maximum power efficiency of 88% via auto-reconfiguration when the input voltage varies from 1.1V to 1.6V.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125797798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628130
Hao Zhang, Mengshu Huang, Yimeng Zhang, Xutao Li, T. Yoshihara
Combining switched-capacitor technology with body effect in MOSFETs, a nano-power CMOS voltage reference is implemented in 0.18 μm standard CMOS technology. The low output breaking threshold restriction is produced without using any component subdivision, such that chip area is saved. Measurements show that the output voltage is about 123.3 mV, temperature coefficient is about 17.6 ppm/°C, and line sensitivity is 0.15 %/V. The supply current is less than 90 nA when the supply voltage is 1 V. The area occupation is about 0.03 mm2.
{"title":"A nano-power switched-capacitor voltage reference using body effect in MOSFETs for application in subthreshold LSI","authors":"Hao Zhang, Mengshu Huang, Yimeng Zhang, Xutao Li, T. Yoshihara","doi":"10.1109/EDSSC.2013.6628130","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628130","url":null,"abstract":"Combining switched-capacitor technology with body effect in MOSFETs, a nano-power CMOS voltage reference is implemented in 0.18 μm standard CMOS technology. The low output breaking threshold restriction is produced without using any component subdivision, such that chip area is saved. Measurements show that the output voltage is about 123.3 mV, temperature coefficient is about 17.6 ppm/°C, and line sensitivity is 0.15 %/V. The supply current is less than 90 nA when the supply voltage is 1 V. The area occupation is about 0.03 mm2.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121775523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628221
Liu Yuan, He Yu-juan, En Yun-fei, Shi Qian
Total dose dependence of leakage current in the partially depleted SOI devices with different layout structures are presented. The experimental results show that the leakage currents in the irradiated PD-SOI device with standard structure are significant affected by trench sidewall leakage, but the leakage currents in the enclosed gate and H gate structures are more affected by the conduction of back gate parasitic transistor and gate induced drain leakage currents.
{"title":"Ionizing radiation induced leakage current in the PD-SOI devices with different layout structures","authors":"Liu Yuan, He Yu-juan, En Yun-fei, Shi Qian","doi":"10.1109/EDSSC.2013.6628221","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628221","url":null,"abstract":"Total dose dependence of leakage current in the partially depleted SOI devices with different layout structures are presented. The experimental results show that the leakage currents in the irradiated PD-SOI device with standard structure are significant affected by trench sidewall leakage, but the leakage currents in the enclosed gate and H gate structures are more affected by the conduction of back gate parasitic transistor and gate induced drain leakage currents.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132325692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628175
R. L. de Orio, S. Selberherr
Interconnect lifetimes due to electromigration (EM) failures are traditionally described by a modified Black equation [1] equation (1) where tf is the time to failure (TTF), A is a constant, j is the electrical current density, n is a fitting parameter which describes the impact of the current density, Ea is the fitted activation energy representing the failure mechanism, k is Boltzmann's constant, and T is the temperature. Originally, Black's derivation resulted in n = 2 [1]. However, this was the source of an extensive debate [2], until more physically sound models showed that n = 2 is associated with a failure dominated by the void nucleation time [3], while n = 1 implies a failure dominated by the void growth time [4].
{"title":"Physically based models of electromigration","authors":"R. L. de Orio, S. Selberherr","doi":"10.1109/EDSSC.2013.6628175","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628175","url":null,"abstract":"Interconnect lifetimes due to electromigration (EM) failures are traditionally described by a modified Black equation [1] equation (1) where tf is the time to failure (TTF), A is a constant, j is the electrical current density, n is a fitting parameter which describes the impact of the current density, Ea is the fitted activation energy representing the failure mechanism, k is Boltzmann's constant, and T is the temperature. Originally, Black's derivation resulted in n = 2 [1]. However, this was the source of an extensive debate [2], until more physically sound models showed that n = 2 is associated with a failure dominated by the void nucleation time [3], while n = 1 implies a failure dominated by the void growth time [4].","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130072162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628232
F. Huang, Dedong Han, D. Shan, Yu Tian, Suoming Zhang, Y. Cong, Yi Wang, Lifeng Liu, Xing Zhang, Shenmin Zhang
Bottom-gate-type oxide thin-film transistors (TFTs) on flexible plastic substrates have been fabricated, with Gallium-doped ZnO (GZO) by radio frequency (RF) sputtering as the channel material at room temperature. The devices use SiO2 as gate insulator and indium tin oxide (ITO) as gate, source and drain electrodes. To optimize performance of AZO TFTs, we studied effects of different oxygen/argon gas flow ratio on electrical properties of TFTs. We found that O2/Ar flow ratio influence the performance of GZO TFTs very significantly. Finally, we gained high performance GZO TFTs with excellent electrical properties, such as a drain current on/off ratio of 107, a subthreshold swing of 394mV/decade, a threshold voltage of 3.2V, and a field effect mobility of 20.7cm2/ V·s in saturation region.
{"title":"Room-temperature fabrication of flexible gallium-doped zinc oxide thin-film transistors on plastic substrates","authors":"F. Huang, Dedong Han, D. Shan, Yu Tian, Suoming Zhang, Y. Cong, Yi Wang, Lifeng Liu, Xing Zhang, Shenmin Zhang","doi":"10.1109/EDSSC.2013.6628232","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628232","url":null,"abstract":"Bottom-gate-type oxide thin-film transistors (TFTs) on flexible plastic substrates have been fabricated, with Gallium-doped ZnO (GZO) by radio frequency (RF) sputtering as the channel material at room temperature. The devices use SiO2 as gate insulator and indium tin oxide (ITO) as gate, source and drain electrodes. To optimize performance of AZO TFTs, we studied effects of different oxygen/argon gas flow ratio on electrical properties of TFTs. We found that O2/Ar flow ratio influence the performance of GZO TFTs very significantly. Finally, we gained high performance GZO TFTs with excellent electrical properties, such as a drain current on/off ratio of 107, a subthreshold swing of 394mV/decade, a threshold voltage of 3.2V, and a field effect mobility of 20.7cm2/ V·s in saturation region.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130160214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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