Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628134
Yingying Chi, Dongmei Li, Zhihua Wang
A relatively low-power 16-bit 1MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Based on the typical structure of SAR ADC, some effective techniques including bootstrapped sampling-switch used to suppress nonlinear distortion, dynamic comparator to reduce power dissipation and the offset-calibration to ensure conversion accuracy have been employed. The off-chip search algorithm is developed against the harmonic distortion resulted from capacitor mismatch. Simulation with parasitism extracted from the layout demonstrates that the ADC achieves signal-to-noise-and-distortion-ratio (SNDR) of 94.3dB at 1MSamples/s, 500KHz input frequency and consumes 44mW from a 1.8V power supply. With the 0.18μm complementary metal-oxide semiconductor (CMOS) process and metal-insulator-metal (MIM) capacitor, the ADC core including decoupling capacitors occupies an active area of 1.0mm×1.4mm.
{"title":"A 16-bit 1MS/s 44mW successive approximation register analog-to-digital converter achieving signal-to-noise-and-distortion-ratio of 94.3dB","authors":"Yingying Chi, Dongmei Li, Zhihua Wang","doi":"10.1109/EDSSC.2013.6628134","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628134","url":null,"abstract":"A relatively low-power 16-bit 1MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Based on the typical structure of SAR ADC, some effective techniques including bootstrapped sampling-switch used to suppress nonlinear distortion, dynamic comparator to reduce power dissipation and the offset-calibration to ensure conversion accuracy have been employed. The off-chip search algorithm is developed against the harmonic distortion resulted from capacitor mismatch. Simulation with parasitism extracted from the layout demonstrates that the ADC achieves signal-to-noise-and-distortion-ratio (SNDR) of 94.3dB at 1MSamples/s, 500KHz input frequency and consumes 44mW from a 1.8V power supply. With the 0.18μm complementary metal-oxide semiconductor (CMOS) process and metal-insulator-metal (MIM) capacitor, the ADC core including decoupling capacitors occupies an active area of 1.0mm×1.4mm.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130282304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628093
Changjian Zhou, Yi Yang, Hualin Cai, Hao Jin, B. Feng, S. Dong, M. Chan, T. Ren
The integration of diamond-like carbon (DLC) and piezoelectric AlN thin film for acoustic wave devices has been presented. Provided the high acoustic velocity and high thermal conductivity of DLC, the AlN/DLC/Si layered structure will outperform the traditional AlN/Si structure for acoustic wave devices. In this paper, the key issues including the deposition of DLC and AlN for implementing DLC based acoustic wave device have been experimentally investigated and surface acoustic wave resonators have been fabricated based on the AlN/DLC/Si layered structure.
{"title":"Integration of diamond-like carbon and AlN for acoustic wave devices","authors":"Changjian Zhou, Yi Yang, Hualin Cai, Hao Jin, B. Feng, S. Dong, M. Chan, T. Ren","doi":"10.1109/EDSSC.2013.6628093","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628093","url":null,"abstract":"The integration of diamond-like carbon (DLC) and piezoelectric AlN thin film for acoustic wave devices has been presented. Provided the high acoustic velocity and high thermal conductivity of DLC, the AlN/DLC/Si layered structure will outperform the traditional AlN/Si structure for acoustic wave devices. In this paper, the key issues including the deposition of DLC and AlN for implementing DLC based acoustic wave device have been experimentally investigated and surface acoustic wave resonators have been fabricated based on the AlN/DLC/Si layered structure.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134540465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628219
K. Chou, H. Hsu, Chun‐Hu Cheng, Kai-Yu Lee, Shang-Rong Li, A. Chin
This study proposes a low operation voltage indium-gallium-zinc oxide (IGZO) thin-film transistor using a high-κ lanthanum-lutetium oxide as the gate dielectric. It is the first time to integrate the high-κ LaLuO3 into an IGZO TFT. The resulting LaLuO3/IGZO TFT shows a low threshold voltage of 0.32 V, a small sub-threshold swing of 310 mV/decade and an acceptable mobility (μFE) of 6.6 cm2/V-s. The low VT and small SS allow device operation voltage below 2.5 V.
{"title":"A low operating voltage IGZO TFT using LaLuO3 gate dielectric","authors":"K. Chou, H. Hsu, Chun‐Hu Cheng, Kai-Yu Lee, Shang-Rong Li, A. Chin","doi":"10.1109/EDSSC.2013.6628219","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628219","url":null,"abstract":"This study proposes a low operation voltage indium-gallium-zinc oxide (IGZO) thin-film transistor using a high-κ lanthanum-lutetium oxide as the gate dielectric. It is the first time to integrate the high-κ LaLuO<sub>3</sub> into an IGZO TFT. The resulting LaLuO<sub>3</sub>/IGZO TFT shows a low threshold voltage of 0.32 V, a small sub-threshold swing of 310 mV/decade and an acceptable mobility (μ<sub>FE</sub>) of 6.6 cm<sup>2</sup>/V-s. The low V<sub>T</sub> and small SS allow device operation voltage below 2.5 V.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"378 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133872079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628179
M. Ostling
This paper will give a brief overview of current state of the art device technology for SiC discrete devices and applications. The superior energy efficiency of SiC devices will be demonstrated and compared to its silicon counterparts.
{"title":"SiC device technology for energy efficiency and high temperature operation","authors":"M. Ostling","doi":"10.1109/EDSSC.2013.6628179","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628179","url":null,"abstract":"This paper will give a brief overview of current state of the art device technology for SiC discrete devices and applications. The superior energy efficiency of SiC devices will be demonstrated and compared to its silicon counterparts.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131720933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628156
Pankaj Kumar, Chitrakant Sahu, Anup Shrivastava, P. Kondekar, Jawar Singh
A novel device structure has been proposed in this paper for junctionless transistor with gate inside device architecture. Its characteristics are demonstrated at gate length of 30 nm. The proposed device shows very good ION/IOFF ratio approximately 108, excellent sub-threshold swing (SS) 63 mV=dec, improved drain induced barrier lowering (DIBL) 40 mV with high ON-state current and extremely low leakage current. The various device parameters are also observed for channel length of 22 nm and 14 nm. The device shows improved short-channel effects with no junction between channel and source/drain, which greatly simplifies the fabrication process at nano scale level. A 3-D ATLAS numerical simulation has been carried out for the proposed device structure.
{"title":"Characteristics of gate inside junctionless transistor with channel length and doping concentration","authors":"Pankaj Kumar, Chitrakant Sahu, Anup Shrivastava, P. Kondekar, Jawar Singh","doi":"10.1109/EDSSC.2013.6628156","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628156","url":null,"abstract":"A novel device structure has been proposed in this paper for junctionless transistor with gate inside device architecture. Its characteristics are demonstrated at gate length of 30 nm. The proposed device shows very good ION/IOFF ratio approximately 108, excellent sub-threshold swing (SS) 63 mV=dec, improved drain induced barrier lowering (DIBL) 40 mV with high ON-state current and extremely low leakage current. The various device parameters are also observed for channel length of 22 nm and 14 nm. The device shows improved short-channel effects with no junction between channel and source/drain, which greatly simplifies the fabrication process at nano scale level. A 3-D ATLAS numerical simulation has been carried out for the proposed device structure.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131056927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628107
Ravi K. Mishra, U. Ganguly, S. Ganguly, S. Lodha, A. Nainani, M. Abraham
In this study we show that incorporation of rare earth metal interlayers such as Yb and Er between Ni and n-Ge can simultaneously enhance the stability of the germanide as well as lower the Schottky barrier (φb) at the germanide/n-Ge interface. As compared to nickel germanide, thermal stability improvement in the low resistance phase by nearly 150 °C and reduction in the electron Schottky barrier height by 0.13 eV was observed for germanides formed using Yb and Er interlayers. This work addresses key challenges in realizing low resistance contacts to n-Ge for future logic and memory applications.
{"title":"Nickel germanide with rare earth interlayers for Ge CMOS applications","authors":"Ravi K. Mishra, U. Ganguly, S. Ganguly, S. Lodha, A. Nainani, M. Abraham","doi":"10.1109/EDSSC.2013.6628107","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628107","url":null,"abstract":"In this study we show that incorporation of rare earth metal interlayers such as Yb and Er between Ni and n-Ge can simultaneously enhance the stability of the germanide as well as lower the Schottky barrier (φb) at the germanide/n-Ge interface. As compared to nickel germanide, thermal stability improvement in the low resistance phase by nearly 150 °C and reduction in the electron Schottky barrier height by 0.13 eV was observed for germanides formed using Yb and Er interlayers. This work addresses key challenges in realizing low resistance contacts to n-Ge for future logic and memory applications.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132701482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628180
K. Guha, Purbashis Ganguly, S. Baishya
This paper deals with the design and simulation of low power and highly efficient RF Power Amplifiers for 4th Generation Wireless Systems. Efficient Linearization and Bandwidth Enhancement techniques are implemented to increase the performance metrics of the power amplifier under consideration. A 90nm CMOS, 60 GHz fully integrated power amplifier has been designed for the 4th Generation Wireless Systems. It has been optimized to deliver maximum linear output power and a considerable amount of gain in the VHF band around 60 GHz. The schematic of the two stage power amplifier has been designed using Agilent's Advanced Design System software. The schematic is used to plot Gain, Linearity, Noise Figure and Stability.
{"title":"Performance analysis of low power and high frequency novel RF Power Amplifier for 4G systems","authors":"K. Guha, Purbashis Ganguly, S. Baishya","doi":"10.1109/EDSSC.2013.6628180","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628180","url":null,"abstract":"This paper deals with the design and simulation of low power and highly efficient RF Power Amplifiers for 4th Generation Wireless Systems. Efficient Linearization and Bandwidth Enhancement techniques are implemented to increase the performance metrics of the power amplifier under consideration. A 90nm CMOS, 60 GHz fully integrated power amplifier has been designed for the 4th Generation Wireless Systems. It has been optimized to deliver maximum linear output power and a considerable amount of gain in the VHF band around 60 GHz. The schematic of the two stage power amplifier has been designed using Agilent's Advanced Design System software. The schematic is used to plot Gain, Linearity, Noise Figure and Stability.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115371113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628115
G. Dash, J. Pradhan, S. K. Swain, S. R. Pattanaik
The electric field and width of the avalanche region are vital while determining the performance of an IMPATT diode. In an attempt to optimize the same a new doping pattern in the form of doping steps is introduced in the avalanche zone and its effects on the terahertz characteristics of a 4H-SiC IMPATT Diode are explored. It is exciting to observe a conversion efficiency of 17.24 % from the IMPAT T diode with the proposed doping steps.
{"title":"Realization of high efficiency 4H-SiC IMPATT diode using optimized doping steps","authors":"G. Dash, J. Pradhan, S. K. Swain, S. R. Pattanaik","doi":"10.1109/EDSSC.2013.6628115","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628115","url":null,"abstract":"The electric field and width of the avalanche region are vital while determining the performance of an IMPATT diode. In an attempt to optimize the same a new doping pattern in the form of doping steps is introduced in the avalanche zone and its effects on the terahertz characteristics of a 4H-SiC IMPATT Diode are explored. It is exciting to observe a conversion efficiency of 17.24 % from the IMPAT T diode with the proposed doping steps.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115752000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-03DOI: 10.1109/EDSSC.2013.6628124
Chun-Yu Lin, M. Ker
To protect a radio-frequency (RF) power amplifier from electrostatic discharge (ESD) damages, a low-capacitance, high-robust, and good-latchup-immune ESD protection device was proposed in this work. The proposed design has been realized in a compact structure in a 65-nm CMOS process. Experimental results of the test devices have been successfully verified, including RF performances, I-V characteristics, and ESD robustness.
{"title":"SCR device for on-chip ESD protection in RF power amplifier","authors":"Chun-Yu Lin, M. Ker","doi":"10.1109/EDSSC.2013.6628124","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628124","url":null,"abstract":"To protect a radio-frequency (RF) power amplifier from electrostatic discharge (ESD) damages, a low-capacitance, high-robust, and good-latchup-immune ESD protection device was proposed in this work. The proposed design has been realized in a compact structure in a 65-nm CMOS process. Experimental results of the test devices have been successfully verified, including RF performances, I-V characteristics, and ESD robustness.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124099581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper a 1.8 V, 2.4 GHz CMOS fully integrated low noise amplifier (LNA) has been implemented in 0.18 μm RF CMOS process for Wireless Local Area Net (WLAN) and Bluetooth band. Acceptable consumption with higher voltage and power gain are achieved using traditional cascode configuration. In this configuration, we successed to have a good trade off among noise, gain, and stability. In order to achieve good input matching for narrow bandwidth the inductive source degeneration LNA topology is used. The LNA power gain is 22.1 dB, noise figure is 1.47 dB and the power consumption is 11 mW from a single 1.8 V power supply.
{"title":"A high gain fully integrated CMOS LNA for WLAN and Bluetooth application","authors":"Laichun Yang, Yuexing Yan, Yiqiang Zhao, Jianguo Ma, Guoxuan Qin","doi":"10.1109/EDSSC.2013.6628229","DOIUrl":"https://doi.org/10.1109/EDSSC.2013.6628229","url":null,"abstract":"In this paper a 1.8 V, 2.4 GHz CMOS fully integrated low noise amplifier (LNA) has been implemented in 0.18 μm RF CMOS process for Wireless Local Area Net (WLAN) and Bluetooth band. Acceptable consumption with higher voltage and power gain are achieved using traditional cascode configuration. In this configuration, we successed to have a good trade off among noise, gain, and stability. In order to achieve good input matching for narrow bandwidth the inductive source degeneration LNA topology is used. The LNA power gain is 22.1 dB, noise figure is 1.47 dB and the power consumption is 11 mW from a single 1.8 V power supply.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114872493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：