Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410612
Cheng-Liang Ding, Ching-yen Ho, M. J. Irwin
It is well known that doing clustering before cell placement could improve the quality of the placement and reduce the run time significantly. The authors present a clustering algorithm which is specially suitable for large designs. It uses local connectivity information to do clustering, and uses global connectivity information to do tie-breaking. Large scale real world circuits show that by this method the improvement could be up to 41% compared to the clustering method without the tie-breaker.<>
{"title":"A new optimization driven clustering algorithm for large circuits","authors":"Cheng-Liang Ding, Ching-yen Ho, M. J. Irwin","doi":"10.1109/EURDAC.1993.410612","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410612","url":null,"abstract":"It is well known that doing clustering before cell placement could improve the quality of the placement and reduce the run time significantly. The authors present a clustering algorithm which is specially suitable for large designs. It uses local connectivity information to do clustering, and uses global connectivity information to do tie-breaking. Large scale real world circuits show that by this method the improvement could be up to 41% compared to the clustering method without the tie-breaker.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125008939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410681
A. Debreil, P. Oddo
Previously, the authors (Proc. Euro. Design Automat. Conf., pp. 680-681, 1992) defined how the concept of synchronous design can be mapped to VHDL descriptions. Now, they present a set of rules, such that, if respected, the VHDL description is synchronous. They then extend the strict notion of synchronism to circuits that can be resynchronized assuming some good timing property and introduce the concept of cleanliness for this purpose.<>
此前，作者(Proc. Euro;设计自动售货机。Conf.， pp. 680-681, 1992)定义了如何将同步设计的概念映射到VHDL描述。现在，它们提出了一组规则，如果遵守这些规则，VHDL描述就是同步的。然后，他们将严格的同步概念扩展到可以重新同步的电路，假设具有良好的定时特性，并为此目的引入清洁度的概念。
{"title":"Synchronous designs in VHDL","authors":"A. Debreil, P. Oddo","doi":"10.1109/EURDAC.1993.410681","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410681","url":null,"abstract":"Previously, the authors (Proc. Euro. Design Automat. Conf., pp. 680-681, 1992) defined how the concept of synchronous design can be mapped to VHDL descriptions. Now, they present a set of rules, such that, if respected, the VHDL description is synchronous. They then extend the strict notion of synchronism to circuits that can be resynchronized assuming some good timing property and introduce the concept of cleanliness for this purpose.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114828967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410669
G. Alves, M. Gericota, J. L. Ramalho, J. Ferreira
Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is, however, still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analyzed, and a corresponding set of testability blocks is proposed. A high flexibility and reduced cost solution is described, which implements these blocks on medium-complexity PLDs (programmable logic devices), using a simple and powerful HDL (hardware design language).<>
{"title":"An HDL approach to board-level BIST","authors":"G. Alves, M. Gericota, J. L. Ramalho, J. Ferreira","doi":"10.1109/EURDAC.1993.410669","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410669","url":null,"abstract":"Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is, however, still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analyzed, and a corresponding set of testability blocks is proposed. A high flexibility and reduced cost solution is described, which implements these blocks on medium-complexity PLDs (programmable logic devices), using a simple and powerful HDL (hardware design language).<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122838212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410622
Negoslav Simic, H. Ortner
Standard gate and switch level simulators are not capable of simulating accurate behavior of certain properties of BiCMOS digital circuits such as bidirectionality and charge sharing. Therefore, the parallelizing and mixing of timing level simulation and gate level simulation within a multilevel simulator would provide an effective balance between simulation speed and functional accuracy. The ability of the simulation system to change its internal partitioning during simulation time is presented. This feature is called dynamic repartitioning and improves the speedup of parallel logic simulation about 20-40% using small numbers of subsimulators.<>
{"title":"Partitioning strategies within a distributed multilevel logic simulator including dynamic repartitioning","authors":"Negoslav Simic, H. Ortner","doi":"10.1109/EURDAC.1993.410622","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410622","url":null,"abstract":"Standard gate and switch level simulators are not capable of simulating accurate behavior of certain properties of BiCMOS digital circuits such as bidirectionality and charge sharing. Therefore, the parallelizing and mixing of timing level simulation and gate level simulation within a multilevel simulator would provide an effective balance between simulation speed and functional accuracy. The ability of the simulation system to change its internal partitioning during simulation time is presented. This feature is called dynamic repartitioning and improves the speedup of parallel logic simulation about 20-40% using small numbers of subsimulators.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114055444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410689
Sanjiv Narayan, D. Gajski
As synthesis tools become more advanced and reliable, the entry point for the designer in the design process is moving towards higher levels of specification. Issues related to the specification of embedded systems are discussed. The authors compare VHDL with five other specification languages: HardwareC, SDL (Specification and Description Language), Statecharts, SpecCharts, and CSP (Communicating Sequential Processes). The capabilities of these languages with respect to specifying designs at the system-level are highlighted. The authors conclude by presenting a list of features which are desirable in a language to be used for specifying systems.<>
{"title":"Features supporting system-level specification in HDLs","authors":"Sanjiv Narayan, D. Gajski","doi":"10.1109/EURDAC.1993.410689","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410689","url":null,"abstract":"As synthesis tools become more advanced and reliable, the entry point for the designer in the design process is moving towards higher levels of specification. Issues related to the specification of embedded systems are discussed. The authors compare VHDL with five other specification languages: HardwareC, SDL (Specification and Description Language), Statecharts, SpecCharts, and CSP (Communicating Sequential Processes). The capabilities of these languages with respect to specifying designs at the system-level are highlighted. The authors conclude by presenting a list of features which are desirable in a language to be used for specifying systems.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127347923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410663
V. A. Shepelev, A. Vlasov
The flexible integration approach intended for the construction of open, tightly integrated CAD systems is presented. The conception of the approach, which is based on maximum flexibility of tool integration methods, design data representation, and data processing, is described in detail. Additionally, experiences in using flexible integration for the development of the CADS framework is reported.<>
{"title":"Implementation of the conception of flexible integration within the CADS framework","authors":"V. A. Shepelev, A. Vlasov","doi":"10.1109/EURDAC.1993.410663","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410663","url":null,"abstract":"The flexible integration approach intended for the construction of open, tightly integrated CAD systems is presented. The conception of the approach, which is based on maximum flexibility of tool integration methods, design data representation, and data processing, is described in detail. Additionally, experiences in using flexible integration for the development of the CADS framework is reported.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125738585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410693
M. Gasteier, N. Wehn, M. Glesner
Behavioral descriptions in VHDL often take advantage of complex operations to describe the behavior of a system in a comprehensive way. Existing synthesis tools, however, are not able to handle the complete set of operations. A time expansive transformation is required to map the high level behavioral description to a lower level description containing only operations that can be processed by synthesis tools. A methodology for replacing a high level mathematical operator with a lower level description is described. In this approach a generator produces synthesizable code able to execute the same function as the original operator. The method allows a design space exploration in time and area. The authors present a multiplier generator to show the benefits of the approach.<>
{"title":"Synthesis of complex VHDL operators","authors":"M. Gasteier, N. Wehn, M. Glesner","doi":"10.1109/EURDAC.1993.410693","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410693","url":null,"abstract":"Behavioral descriptions in VHDL often take advantage of complex operations to describe the behavior of a system in a comprehensive way. Existing synthesis tools, however, are not able to handle the complete set of operations. A time expansive transformation is required to map the high level behavioral description to a lower level description containing only operations that can be processed by synthesis tools. A methodology for replacing a high level mathematical operator with a lower level description is described. In this approach a generator produces synthesizable code able to execute the same function as the original operator. The method allows a design space exploration in time and area. The authors present a multiplier generator to show the benefits of the approach.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123721656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410686
Mohamed Belhadj, R. McConnell, P. Guernic
The work presented introduces a formal definition of some important constructs of VHDL, using a formally defined language. Both macro time and micro time scales are used. The inclusion of micro time, or time deltas, allows the authors to describe variables as well as signals. For the purpose of illustration they present the signal attributes of VHDL. This work represents a prelude to the complete translation of VHDL into the formal verification language SIGNAL. SIGNAL can then provide a basis for verifying VHDL programs.<>
{"title":"A framework for macro- and micro-time to model VHDL attributes","authors":"Mohamed Belhadj, R. McConnell, P. Guernic","doi":"10.1109/EURDAC.1993.410686","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410686","url":null,"abstract":"The work presented introduces a formal definition of some important constructs of VHDL, using a formally defined language. Both macro time and micro time scales are used. The inclusion of micro time, or time deltas, allows the authors to describe variables as well as signals. For the purpose of illustration they present the signal attributes of VHDL. This work represents a prelude to the complete translation of VHDL into the formal verification language SIGNAL. SIGNAL can then provide a basis for verifying VHDL programs.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132714235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410614
M. Chrzanowska-Jeske, Steffen Goller
A new routing-driven partitioning approach for fitting a sequential circuit onto limited-connectivity EPLDs (electrically programmable logic devices) is presented. The fitting problem is stated as a graph monomorphism problem. Global, local, and adjacency routing constraints are used to define the partitioning properties of the graph representing chip resources. This approach very effectively limits the solution space of the graph monomorphism problem in the early stages of the search. The program which uses the proposed algorithm to solve the fitting problem for the CY7C361 device, from Cypress Semiconductor, has been implemented and tested. Solutions to a number of problems unsolved by the previous fitter were found. The experimental results are presented.<>
{"title":"Partitioning approach to find an exact solution to the fitting problem in an application-specific EPLD device","authors":"M. Chrzanowska-Jeske, Steffen Goller","doi":"10.1109/EURDAC.1993.410614","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410614","url":null,"abstract":"A new routing-driven partitioning approach for fitting a sequential circuit onto limited-connectivity EPLDs (electrically programmable logic devices) is presented. The fitting problem is stated as a graph monomorphism problem. Global, local, and adjacency routing constraints are used to define the partitioning properties of the graph representing chip resources. This approach very effectively limits the solution space of the graph monomorphism problem in the early stages of the search. The program which uses the proposed algorithm to solve the fitting problem for the CY7C361 device, from Cypress Semiconductor, has been implemented and tested. Solutions to a number of problems unsolved by the previous fitter were found. The experimental results are presented.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129008178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-09-20DOI: 10.1109/EURDAC.1993.410665
H. Martin
Combining existing retiming techniques in a single method is a promising way to exploit the optimization potential of all these techniques. The author's method, which joins together the techniques of relocation and clock delay adjustment, is such an approach towards timing improvement of synchronous sequential circuits. The related linear programming approach is presented, and experimental results for benchmarks are shown.<>
{"title":"Retiming by combination of relocation and clock delay adjustment","authors":"H. Martin","doi":"10.1109/EURDAC.1993.410665","DOIUrl":"https://doi.org/10.1109/EURDAC.1993.410665","url":null,"abstract":"Combining existing retiming techniques in a single method is a promising way to exploit the optimization potential of all these techniques. The author's method, which joins together the techniques of relocation and clock delay adjustment, is such an approach towards timing improvement of synchronous sequential circuits. The related linear programming approach is presented, and experimental results for benchmarks are shown.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128844263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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