Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306769
C. Jin, Y. Sasaki, K. Tsutsui, H. Tamura, B. Mizuno, R. Higaki, T. Satoh, K. Majima, H. Sauddin, K. Takagi, S. Ohmi, H. Iwai
We evaluated the optical absorption properties of ultra-shallow (<10 nm) plasma doping (PD) layers by spectroscopic ellipsometry (SE). The optical absorption coefficients of PD layers are much larger than that of crystalline Si (c-Si) substrate by one figure at maximum in the wavelength range from 400 nm to 800 nm. We also found that higher DC bias during PD resulted in higher optical absorption coefficient for the same PD time of 60 seconds.
{"title":"Estimation of ultra-shallow plasma doping (PD) layer's optical absorption properties by spectroscopic ellipsometry (SE)","authors":"C. Jin, Y. Sasaki, K. Tsutsui, H. Tamura, B. Mizuno, R. Higaki, T. Satoh, K. Majima, H. Sauddin, K. Takagi, S. Ohmi, H. Iwai","doi":"10.1109/IWJT.2004.1306769","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306769","url":null,"abstract":"We evaluated the optical absorption properties of ultra-shallow (<10 nm) plasma doping (PD) layers by spectroscopic ellipsometry (SE). The optical absorption coefficients of PD layers are much larger than that of crystalline Si (c-Si) substrate by one figure at maximum in the wavelength range from 400 nm to 800 nm. We also found that higher DC bias during PD resulted in higher optical absorption coefficient for the same PD time of 60 seconds.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131197181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306871
G. Du, Xiaoyan Liu, Meng Liu, Lei Sun, R. Han
A double-gate Schottky barrier tunneling transistor (DGSBTT) structure is investigated by a 2-D full-band Monte Carlo device simulator. A Schottky barrier contact model including tunneling effect and Schottky effect has been implemented in this simulator. The result shows that DGSBTF has a big performance improvement compare to single gate SBTT, its Ion/Ioff is more than 10/sup 5/ at Vds= 1.0 V.
{"title":"Characterizations of double-gate SBTT studying by a 2-D full-band Monte Carlo device simulator","authors":"G. Du, Xiaoyan Liu, Meng Liu, Lei Sun, R. Han","doi":"10.1109/IWJT.2004.1306871","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306871","url":null,"abstract":"A double-gate Schottky barrier tunneling transistor (DGSBTT) structure is investigated by a 2-D full-band Monte Carlo device simulator. A Schottky barrier contact model including tunneling effect and Schottky effect has been implemented in this simulator. The result shows that DGSBTF has a big performance improvement compare to single gate SBTT, its Ion/Ioff is more than 10/sup 5/ at Vds= 1.0 V.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125467555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306761
A. Agarwal, H. Gossmann
The most recent release of the ITRS, the 2003 edition, describes a paradigm change in Si chip manufacturing expected around the 65 nm node. This is due to the rapid introduction of new materials and device structures required for further scaling of performance, such as strained Si, ultra-thin-body and multiple metal-gate devices. These novel architectures raise fundamentally new questions for shallow junction formation. We discuss several related issues from the perspective of future challenges for ion implantation and rapid thermal annealing: whether high tilt implantation is necessary to achieve sufficient extension overlap; is an ultra-shallow junction technology required for thin body devices; the role of ion implantation in metal-gate technology; and the challenge for RTP in an era of ever increasing system on chip integration and shrinking thermal budgets.
{"title":"Ultra-shallow junctions for novel device architectures beyond 65 nm node","authors":"A. Agarwal, H. Gossmann","doi":"10.1109/IWJT.2004.1306761","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306761","url":null,"abstract":"The most recent release of the ITRS, the 2003 edition, describes a paradigm change in Si chip manufacturing expected around the 65 nm node. This is due to the rapid introduction of new materials and device structures required for further scaling of performance, such as strained Si, ultra-thin-body and multiple metal-gate devices. These novel architectures raise fundamentally new questions for shallow junction formation. We discuss several related issues from the perspective of future challenges for ion implantation and rapid thermal annealing: whether high tilt implantation is necessary to achieve sufficient extension overlap; is an ultra-shallow junction technology required for thin body devices; the role of ion implantation in metal-gate technology; and the challenge for RTP in an era of ever increasing system on chip integration and shrinking thermal budgets.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124651368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306860
C. Uang, H. Chuang, T. Shen -Fu, K. Thei, P. Lai, S. Fu, Y. Tsai, Wen-Chau Liu
The temperature-dependent characteristics of polysilicon and diffused resistors have been studied. By using the 0.18 /spl mu/m CMOS technology, cobalt salicide process is employed and silicide is formed at the ends of resistors. Based on a simple and useful model, some important parameters of resistors including bulk sheet resistance (R/sub bulk/) and interface resistance (R/sub interface/) are obtained at different temperature. For diffused resistors, the R/sub bulk/ and R/sub interface/, values are increased and decreased with the increase of temperature, respectively. Positive values of temperature coefficient of resistance (TCR) are observed. Furthermore, TCR values are decreased with the decrease of resistor size. For polysilicon resistors, the Rinterface values are decreased with the increase of temperature. In addition, negative and positive TCR values of RNA are found in n/sup +/ and p/sup +/ polysilicon resistors, respectively. In conclusion, by comparing the studied diffused and polysilicon resistors, the negative trends of TCR are observed when the resistor sizes are decreased.
{"title":"Temperature-dependent characteristics of diffused and polysilicon resistors for ULSI applications","authors":"C. Uang, H. Chuang, T. Shen -Fu, K. Thei, P. Lai, S. Fu, Y. Tsai, Wen-Chau Liu","doi":"10.1109/IWJT.2004.1306860","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306860","url":null,"abstract":"The temperature-dependent characteristics of polysilicon and diffused resistors have been studied. By using the 0.18 /spl mu/m CMOS technology, cobalt salicide process is employed and silicide is formed at the ends of resistors. Based on a simple and useful model, some important parameters of resistors including bulk sheet resistance (R/sub bulk/) and interface resistance (R/sub interface/) are obtained at different temperature. For diffused resistors, the R/sub bulk/ and R/sub interface/, values are increased and decreased with the increase of temperature, respectively. Positive values of temperature coefficient of resistance (TCR) are observed. Furthermore, TCR values are decreased with the decrease of resistor size. For polysilicon resistors, the Rinterface values are decreased with the increase of temperature. In addition, negative and positive TCR values of RNA are found in n/sup +/ and p/sup +/ polysilicon resistors, respectively. In conclusion, by comparing the studied diffused and polysilicon resistors, the negative trends of TCR are observed when the resistor sizes are decreased.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126714630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306867
Huihui Ji, Min Yu, Hao Shi, Xiaokang Shi, Ru Huang, Xing Zhang, K. Suzuki, H. Oka
Molecular dynamics (MD) method has not been reported to predict range profiles of implantation into HfO/sub 2/ and stopping power models especially electronic stopping power model has not been studied specifically. In this article, MD method is successfully applied to simulate B, As and P implantation into HfO/sub 2/. An efficient electronic stopping model with only one free parameter, i.e., the single electron radius, is carefully discussed. A reliable fitting value of the single electron radius is firstly given for B, As and P implantation into HfO/sub 2/. Using the obtained fitting value, simulation results agree with SIMS data excellently over the energy range of 5 - 40 keV.
{"title":"Simulation of implantation into HfO/sub 2/ by MD method","authors":"Huihui Ji, Min Yu, Hao Shi, Xiaokang Shi, Ru Huang, Xing Zhang, K. Suzuki, H. Oka","doi":"10.1109/IWJT.2004.1306867","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306867","url":null,"abstract":"Molecular dynamics (MD) method has not been reported to predict range profiles of implantation into HfO/sub 2/ and stopping power models especially electronic stopping power model has not been studied specifically. In this article, MD method is successfully applied to simulate B, As and P implantation into HfO/sub 2/. An efficient electronic stopping model with only one free parameter, i.e., the single electron radius, is carefully discussed. A reliable fitting value of the single electron radius is firstly given for B, As and P implantation into HfO/sub 2/. Using the obtained fitting value, simulation results agree with SIMS data excellently over the energy range of 5 - 40 keV.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127371334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/iwjt.2004.1306875
A. Agarwal, H. Gossmann
The most recent release of the ITRS, the 2003 edition, describes a paradigm change that Si chip manufacturing is expected to undergo around the 65nm node. This is due to the rapid introduction of new materials and device structures required for further scaling of performance, such as strained Si, ultra-thin-body and multiple metal-gate devices. These novel architectures raise fundamentally new questions for shallow junction formation. We discuss several related issues from the perspective of future challenges for ion implantation and rapid thermal annealing: if high tilt implantation is necessary to achieve sufficient extension overlap; is an ultra-shallow junction technology required for thin body devices; the role of ion implantation in metal-gate technology; and the challenge for RTP in an era of ever increasing system on chip integration and shrinking thermal budgets.
{"title":"Ultra-shallow junctions for novel device architectures beyond the 65 nm node","authors":"A. Agarwal, H. Gossmann","doi":"10.1109/iwjt.2004.1306875","DOIUrl":"https://doi.org/10.1109/iwjt.2004.1306875","url":null,"abstract":"The most recent release of the ITRS, the 2003 edition, describes a paradigm change that Si chip manufacturing is expected to undergo around the 65nm node. This is due to the rapid introduction of new materials and device structures required for further scaling of performance, such as strained Si, ultra-thin-body and multiple metal-gate devices. These novel architectures raise fundamentally new questions for shallow junction formation. We discuss several related issues from the perspective of future challenges for ion implantation and rapid thermal annealing: if high tilt implantation is necessary to achieve sufficient extension overlap; is an ultra-shallow junction technology required for thin body devices; the role of ion implantation in metal-gate technology; and the challenge for RTP in an era of ever increasing system on chip integration and shrinking thermal budgets.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122977044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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