Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306763
M. Takai, S. Ichihara, S. Abo, F. Wakaya, H. Sayama, T. Eimori, Y. Inoue
Medium Energy Ion Scattering (MEIS) using a toroidal electrostatic analyzer (TEA) with an energy resolution (/spl Delta/E/E) of 4 x 10/sup -3/ has been used for ultra-shallow depth profiling of As implanted in Si at 1-5 keV to a dose of 1.2 /spl times/ 10/sup 15/ ions/cm/sup 2/ before and after RTA and spike annealing. Depth profiling results extracted from MEIS spectra were compared with those of simulation and SIMS measurement. The arsenic re-distribution close to the surface after spike annealing was found by MEIS and SIMS measurements.
{"title":"Ultra-shallow arsenic profiling using enhanced depth-resolution analysis technique with medium energy ion scattering","authors":"M. Takai, S. Ichihara, S. Abo, F. Wakaya, H. Sayama, T. Eimori, Y. Inoue","doi":"10.1109/IWJT.2004.1306763","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306763","url":null,"abstract":"Medium Energy Ion Scattering (MEIS) using a toroidal electrostatic analyzer (TEA) with an energy resolution (/spl Delta/E/E) of 4 x 10/sup -3/ has been used for ultra-shallow depth profiling of As implanted in Si at 1-5 keV to a dose of 1.2 /spl times/ 10/sup 15/ ions/cm/sup 2/ before and after RTA and spike annealing. Depth profiling results extracted from MEIS spectra were compared with those of simulation and SIMS measurement. The arsenic re-distribution close to the surface after spike annealing was found by MEIS and SIMS measurements.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125495573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306859
M. Zhu, P. Chen, R. Fu, W. Liu, C. Lin, P. Chu
Al/sub 2/O/sub 3/-ZrO/sub 2/ composite films were prepared on silicon-on-insulator (SOI) substrate by ultra-high vacuum electron-beam co-evaporation. The crystallization temperature, microstructures and surface morphology of the films during high temperature rapid thermal annealing (RTA) in N/sub 2/ ambient were studied by x-ray diffraction (XRD), transmission electron microscopy (TEM) and atomic force microscopy (AFM). The amorphous structure of the Al/sub 2/O/sub 3/-ZrO/sub 2/ film is maintained up to a post-annealing temperature of 900/spl deg/C and the expansion of the interfacial layer at high temperature is suppressed. Moreover, the current-voltage characteristic was measured with an Al/Al/sub 2/O/sub 3/-ZrO/sub 2//Si MIS structure fabricated on the films, and the result indicates excellent leakage current properties.
{"title":"Structural and electrical properties of Al/sub 2/O/sub 3/-ZrO/sub 2/ gate dielectrics on silicon-on-insulator","authors":"M. Zhu, P. Chen, R. Fu, W. Liu, C. Lin, P. Chu","doi":"10.1109/IWJT.2004.1306859","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306859","url":null,"abstract":"Al/sub 2/O/sub 3/-ZrO/sub 2/ composite films were prepared on silicon-on-insulator (SOI) substrate by ultra-high vacuum electron-beam co-evaporation. The crystallization temperature, microstructures and surface morphology of the films during high temperature rapid thermal annealing (RTA) in N/sub 2/ ambient were studied by x-ray diffraction (XRD), transmission electron microscopy (TEM) and atomic force microscopy (AFM). The amorphous structure of the Al/sub 2/O/sub 3/-ZrO/sub 2/ film is maintained up to a post-annealing temperature of 900/spl deg/C and the expansion of the interfacial layer at high temperature is suppressed. Moreover, the current-voltage characteristic was measured with an Al/Al/sub 2/O/sub 3/-ZrO/sub 2//Si MIS structure fabricated on the films, and the result indicates excellent leakage current properties.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"429 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131797229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The changes of flow pattern defects (FPDs), one kind of grown-in defects in CZ-Si, in RTA annealed wafers were investigated in this paper. The wafers were rapid thermal annealed in N/sub 2/, N/sub 2//O/sub 2/ and Ar atmosphere respectively under RTA processes. A void was found on the apex of the parabola outline of FPDs by AFM and optical microscopy. It's shown that the hole on the tip of FPDs became shallower in depth and larger in width obviously when annealed above 1100/spl deg/C, esp. annealed in Ar atmosphere 1200/spl deg/C. Furthermore, it's also shown that the density of FPDs to reduce when annealed above 1100/spl deg/C, and most of FPDs in CZ-Si would disappear during RTA process in Ar atmosphere above 1200/spl deg/C.
{"title":"The effects of RTA processes on flow pattern defects in Czochralski silicon","authors":"Hanfeng Zhang, Caichi Liu, Qigang Zhou, Jing Wang, Qiuyan Hao, Hongdi Zhang, Yangxiang Li","doi":"10.1109/IWJT.2004.1306758","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306758","url":null,"abstract":"The changes of flow pattern defects (FPDs), one kind of grown-in defects in CZ-Si, in RTA annealed wafers were investigated in this paper. The wafers were rapid thermal annealed in N/sub 2/, N/sub 2//O/sub 2/ and Ar atmosphere respectively under RTA processes. A void was found on the apex of the parabola outline of FPDs by AFM and optical microscopy. It's shown that the hole on the tip of FPDs became shallower in depth and larger in width obviously when annealed above 1100/spl deg/C, esp. annealed in Ar atmosphere 1200/spl deg/C. Furthermore, it's also shown that the density of FPDs to reduce when annealed above 1100/spl deg/C, and most of FPDs in CZ-Si would disappear during RTA process in Ar atmosphere above 1200/spl deg/C.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132796004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306854
R. Yang, J.F. Li, H. Qian, Z. Han
Novel integration structures of SOI LDMOS/ NMOS/inductor/capacitor/resistor for RFIC are proposed, combined with several key techniques, including body contact with asymmetrical source/drain junctions, SiO/sub 2//Si/sub 3/N/sub 4/ dual sidewalls and Ti-salicide, etc. These devices are integrated into the SIMOX substrate with simplified process steps. Experimental or simulated results show that floating body effects are well restrained, and DC characteristics are good, while the cutoff frequency of LDMOS is higher than that of conventional devices with lateral body-contact structures.
{"title":"An asymmetrical source/drain junction structure for SOI RFIC: immune to floating body effects","authors":"R. Yang, J.F. Li, H. Qian, Z. Han","doi":"10.1109/IWJT.2004.1306854","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306854","url":null,"abstract":"Novel integration structures of SOI LDMOS/ NMOS/inductor/capacitor/resistor for RFIC are proposed, combined with several key techniques, including body contact with asymmetrical source/drain junctions, SiO/sub 2//Si/sub 3/N/sub 4/ dual sidewalls and Ti-salicide, etc. These devices are integrated into the SIMOX substrate with simplified process steps. Experimental or simulated results show that floating body effects are well restrained, and DC characteristics are good, while the cutoff frequency of LDMOS is higher than that of conventional devices with lateral body-contact structures.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128686596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Efficient simulations of ion implantation are very important to ultra shallow junction technology. In this paper, a new splitting method is developed, based on the quantitative description and sensitivity analysis of statistical noise. A series of formulas are deduced and some disadvantages of existing splitting methods are pointed out.
{"title":"A new simulation method of ion implantation","authors":"Xiaokang Shi, M. Yul, Huihui Jil, Ru Huang, Xing Zhang, Jinyu Zhang","doi":"10.1109/IWJT.2004.1306864","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306864","url":null,"abstract":"Efficient simulations of ion implantation are very important to ultra shallow junction technology. In this paper, a new splitting method is developed, based on the quantitative description and sensitivity analysis of statistical noise. A series of formulas are deduced and some disadvantages of existing splitting methods are pointed out.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121891487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306777
Bin-Feng Huang, Soon-Young Oh, J. Yun, Y. Park, H. Ji, Yong-Goo Kim, Jin-Suk Wang, Han-Seob Cha, S. Heo, Jeong‐gun Lee, Yeong-Cheol Kim, H. Lee
In this paper, to enhance the thermal stability of the Ni germano-silicide especially on the doped substrate, various kinds of tri-layer structures of Ti/Ni/TiN, Ni/Ti/TiN, Co/Ni/TiN and Ni/Co/TiN were applied. Contrary to the conventional Ni silicide, two-step RTP is also applied to enhance the thermal stability of Ni germano-silicide. Among these structures, a highly stable Ni germano-silicide can be formed by Ni/Co/TiN with high Co concentration along with 2-step RTP. Co/Ni/TiN and Ti/Ni/TiN, especially Co/Ni/TiN with high Co concentration using 2-step RTP, are found to be effective in preventing the abnormal increase of sheet resistance on the As doped substrate during post-silicidation annealing higher than 613/spl deg/C.
{"title":"Improvement of thermal stability of Ni germano-silicide for nano-scale CMOS technology","authors":"Bin-Feng Huang, Soon-Young Oh, J. Yun, Y. Park, H. Ji, Yong-Goo Kim, Jin-Suk Wang, Han-Seob Cha, S. Heo, Jeong‐gun Lee, Yeong-Cheol Kim, H. Lee","doi":"10.1109/IWJT.2004.1306777","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306777","url":null,"abstract":"In this paper, to enhance the thermal stability of the Ni germano-silicide especially on the doped substrate, various kinds of tri-layer structures of Ti/Ni/TiN, Ni/Ti/TiN, Co/Ni/TiN and Ni/Co/TiN were applied. Contrary to the conventional Ni silicide, two-step RTP is also applied to enhance the thermal stability of Ni germano-silicide. Among these structures, a highly stable Ni germano-silicide can be formed by Ni/Co/TiN with high Co concentration along with 2-step RTP. Co/Ni/TiN and Ti/Ni/TiN, especially Co/Ni/TiN with high Co concentration using 2-step RTP, are found to be effective in preventing the abnormal increase of sheet resistance on the As doped substrate during post-silicidation annealing higher than 613/spl deg/C.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130194523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306785
B. Shen, N. Tang, Jie Lu, Z. Zheng, Dunjun Chen, Y. Gui, Qiu Zhijun, C. Jiang, S. Gu, J. Chu, Rong Zhang, Youdou Zheng
Magnetotransport properties of modulation-doped Al/sub x/Ga/sub 1-x/N/GaN heterostructures were studied at low temperatures and high magnetic fields. The strong Shubnikov-de Hass oscillations with the double periodicity is clearly observed, indicating the two-dimensional electron gas (2DEG) occupation of the double subbands in the triangular quantum well at the heterointerfaces. It is determined that the 2DEG occupation of the double subbands occurs when the 2DEG sheet concentration reaches 9.0 /spl times/ 10/sup 12/cm/sup -2/, and the energy separation between the first and the second subbands is 75 meV. The quantum scattering time related to the first subband is determined to be 8.4 /spl times/ 10/sup -14/ s. The mobilities of the 2DEG in the first and the second subbands, magnetointersubband scattering oscillations of the 2DEG and the spin splitting of the 2DEG have also been studied.
{"title":"Transport properties of the two-dimensional electron gas in Al/sub x/Ga/sub 1-x/N/GaN heterostructures","authors":"B. Shen, N. Tang, Jie Lu, Z. Zheng, Dunjun Chen, Y. Gui, Qiu Zhijun, C. Jiang, S. Gu, J. Chu, Rong Zhang, Youdou Zheng","doi":"10.1109/IWJT.2004.1306785","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306785","url":null,"abstract":"Magnetotransport properties of modulation-doped Al/sub x/Ga/sub 1-x/N/GaN heterostructures were studied at low temperatures and high magnetic fields. The strong Shubnikov-de Hass oscillations with the double periodicity is clearly observed, indicating the two-dimensional electron gas (2DEG) occupation of the double subbands in the triangular quantum well at the heterointerfaces. It is determined that the 2DEG occupation of the double subbands occurs when the 2DEG sheet concentration reaches 9.0 /spl times/ 10/sup 12/cm/sup -2/, and the energy separation between the first and the second subbands is 75 meV. The quantum scattering time related to the first subband is determined to be 8.4 /spl times/ 10/sup -14/ s. The mobilities of the 2DEG in the first and the second subbands, magnetointersubband scattering oscillations of the 2DEG and the spin splitting of the 2DEG have also been studied.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130043031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306872
Xinfu Liu, K.Y. Wu, Jianghua Ju, H. Ho, Xing Yu, S. Chen
In this work, CMOS devices with very low leakage current (Ioff) are studied for Ultra Low Power (ULP) applications. The ULP is targeted for worst-case Ioff <0.5 pA//spl mu/m. We used our 0.15 /spl mu/m and 0.18 /spl mu/m base line process to optimize the Vt, LDD, pocket and S/D implant to reduce device GIDL, poly edge junction leakage, band to band leakage and DIBL. A ULP product, CMOS I Mbit SRAM with measured minimum standby current < 10 /spl mu/A were fabricated successfully.
{"title":"Deep sub-micron ultra-low power CMOS device design and optimization","authors":"Xinfu Liu, K.Y. Wu, Jianghua Ju, H. Ho, Xing Yu, S. Chen","doi":"10.1109/IWJT.2004.1306872","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306872","url":null,"abstract":"In this work, CMOS devices with very low leakage current (Ioff) are studied for Ultra Low Power (ULP) applications. The ULP is targeted for worst-case Ioff <0.5 pA//spl mu/m. We used our 0.15 /spl mu/m and 0.18 /spl mu/m base line process to optimize the Vt, LDD, pocket and S/D implant to reduce device GIDL, poly edge junction leakage, band to band leakage and DIBL. A ULP product, CMOS I Mbit SRAM with measured minimum standby current < 10 /spl mu/A were fabricated successfully.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120899506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306762
R. Lindsay, S. Severi, B. Pawlak, K. Henson, A. Lauwers, X. Pagès, A. Satta, R. Surdeanu, H. Lendzian, K. Maex
Ultra-shallow junction formation by solid phase epitaxial regrowth (SPER) has been shown to produce excellent junction profiles beyond that of conventional spike annealing. However residual damage can degrade various aspects of the transistor performance, annihilating any:improvement due to the junction profile. In this work we look at optimizing the junction and channel conditions to meet the dopant profile and transistor requirements for the 45 nm CMOS node. We show how an optimised junction implant and low temperature SPER spike anneal can further increase the activation level and profile of the junction. In devices we show results on the effect of SPER processing on both the substrate and gate doping. This includes junction overlap, channel deactivation, contact resistance, junction leakage, poly depletion, and gate leakage. We address each of these concerns for both pMOS and nMOS and identify what are the main strengths and weaknesses of SPER in devices.
{"title":"SPER junction optimisation in 45 nm CMOS devices","authors":"R. Lindsay, S. Severi, B. Pawlak, K. Henson, A. Lauwers, X. Pagès, A. Satta, R. Surdeanu, H. Lendzian, K. Maex","doi":"10.1109/IWJT.2004.1306762","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306762","url":null,"abstract":"Ultra-shallow junction formation by solid phase epitaxial regrowth (SPER) has been shown to produce excellent junction profiles beyond that of conventional spike annealing. However residual damage can degrade various aspects of the transistor performance, annihilating any:improvement due to the junction profile. In this work we look at optimizing the junction and channel conditions to meet the dopant profile and transistor requirements for the 45 nm CMOS node. We show how an optimised junction implant and low temperature SPER spike anneal can further increase the activation level and profile of the junction. In devices we show results on the effect of SPER processing on both the substrate and gate doping. This includes junction overlap, channel deactivation, contact resistance, junction leakage, poly depletion, and gate leakage. We address each of these concerns for both pMOS and nMOS and identify what are the main strengths and weaknesses of SPER in devices.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126546590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306852
Z.J. Chen, F. Zhang, X. Wang, S. Zou
In this paper, a study on the dry thermal oxidation of a graded SiGe layer is proposed. By oxidation of a graded SiGe layer, the effect of Ge pileup was reduced and dependence of the oxidation ambient was analyzed. During oxidation at pure oxide ambient, pure compositions of silicon dioxide are formed without dislocation, and it was clearly proved by the TEM, EDS, SE, and AFM results. Whereas, after oxidation under atmospheric pressure with 21/min mix gas flow of Ar50%+O/sub 2/50%, composition of SiGeO/sub 2/ was found at the top layer. This result can propose an oxidation method optimization of SiGe/Si heterostructures.
{"title":"Structural characterization of SiGe/Si dry thermal oxidation","authors":"Z.J. Chen, F. Zhang, X. Wang, S. Zou","doi":"10.1109/IWJT.2004.1306852","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306852","url":null,"abstract":"In this paper, a study on the dry thermal oxidation of a graded SiGe layer is proposed. By oxidation of a graded SiGe layer, the effect of Ge pileup was reduced and dependence of the oxidation ambient was analyzed. During oxidation at pure oxide ambient, pure compositions of silicon dioxide are formed without dislocation, and it was clearly proved by the TEM, EDS, SE, and AFM results. Whereas, after oxidation under atmospheric pressure with 21/min mix gas flow of Ar50%+O/sub 2/50%, composition of SiGeO/sub 2/ was found at the top layer. This result can propose an oxidation method optimization of SiGe/Si heterostructures.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115153560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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