Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306752
Hanming Wu, S. Lee, Xing Yu, Yong Liu, J. Chen
In the present paper, high-density plasma implantation is proposed for shallow junction formation. The inevitable low energy component in ion energy distribution function (IEDF) has been studied by theoretical and numerical methods. Finally, the device effects induced by such a low energy component in IEDF in plasma implantation are analyzed and discussed.
{"title":"Device effect of low energy implantation in high density plasma","authors":"Hanming Wu, S. Lee, Xing Yu, Yong Liu, J. Chen","doi":"10.1109/IWJT.2004.1306752","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306752","url":null,"abstract":"In the present paper, high-density plasma implantation is proposed for shallow junction formation. The inevitable low energy component in ion energy distribution function (IEDF) has been studied by theoretical and numerical methods. Finally, the device effects induced by such a low energy component in IEDF in plasma implantation are analyzed and discussed.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124093425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306853
L. Sun, X.Y. Liu, G. Du, J. Kang, X. Guan, R. Han
The Schottky barrier MOSFETs with channel length of 70 nm have been fabricated with sidewall etchback technology. The conventional lithography is applied for the definition of the sub-100 nm channel region. In the process, the advanced lithography technology has not been involved. The SOI structure has been used to take place of the bulk silicon substrate, and the silicon on the source and drain has been transformed to silicide. The thermal emission leakage current is reduced due to the decrease of the area of the source/drain Schottky contact.
{"title":"Fabrication of the sub-100 nm thin body SOI Schottky barrier tunneling transistors with sidewall etchback technology","authors":"L. Sun, X.Y. Liu, G. Du, J. Kang, X. Guan, R. Han","doi":"10.1109/IWJT.2004.1306853","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306853","url":null,"abstract":"The Schottky barrier MOSFETs with channel length of 70 nm have been fabricated with sidewall etchback technology. The conventional lithography is applied for the definition of the sub-100 nm channel region. In the process, the advanced lithography technology has not been involved. The SOI structure has been used to take place of the bulk silicon substrate, and the silicon on the source and drain has been transformed to silicide. The thermal emission leakage current is reduced due to the decrease of the area of the source/drain Schottky contact.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126869251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306755
K. Tsutsui, R. Higaki, Y. Sasaki, T. Sato, H. Tamura, B. Mizuno, H. Iwai
In the low energy plasma doping process, the contribution of not only ionized species but also neutral species to the doping process should be considered. In order to investigate such a contribution, the experiments of gas phase doping combined with Ar or He plasma pre-treatment were carried out. Gas phase impurity absorption should be affected by surface condition of Si substrates. As a result, significant increase of boron dose from neutral gas phase was observed when the substrate surface was pre-treated by Ar or He plasma prior to exposure to neutral B/sub 2/H/sub 6//He gas. It was also found that the gas phase impurity absorption was affected by substrate temperature when the surface was exposed to the neutral B/sub 2/H/sub 6//He gas.
{"title":"Contribution and control of neutral gas absorption effects in the plasma doping of boron into Si","authors":"K. Tsutsui, R. Higaki, Y. Sasaki, T. Sato, H. Tamura, B. Mizuno, H. Iwai","doi":"10.1109/IWJT.2004.1306755","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306755","url":null,"abstract":"In the low energy plasma doping process, the contribution of not only ionized species but also neutral species to the doping process should be considered. In order to investigate such a contribution, the experiments of gas phase doping combined with Ar or He plasma pre-treatment were carried out. Gas phase impurity absorption should be affected by surface condition of Si substrates. As a result, significant increase of boron dose from neutral gas phase was observed when the substrate surface was pre-treated by Ar or He plasma prior to exposure to neutral B/sub 2/H/sub 6//He gas. It was also found that the gas phase impurity absorption was affected by substrate temperature when the surface was exposed to the neutral B/sub 2/H/sub 6//He gas.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128979155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306775
J. Yun, Soon-Young Oh, H. Ji, Bin-Feng Huang, Y. Park, Seong-Hyung Park, Heui-Seung Lee, Dae-Byung Kim, Ui-Sik Kim, Han-Seob Cha, Sang Hu, Jeong‐gun Lee, H. Lee
NiSi is an attractive silicide material to be applied in the nanoscale CMOSFETs. However, degradation of NiSi film after the post-silicidation annealing is one of serious demerits of NiSi. Ni/Co bi-layer is known as one of the most stable silicide structure for the improvement of the thermal stability. The formed bi-layer consists of the upper protection layer (CoSi/sub x/) and the lower conduction layer (NiSi) and their roles are different from each other. In this study, optimization of Ni/Co ratio and process condition is investigated for the nanoscale CMOSFETs.
{"title":"Optimal Ni/Co thickness extraction and two step rapid thermal process of the nickel-silicide for nanoscale complementary metal oxide semiconductor (CMOS) application","authors":"J. Yun, Soon-Young Oh, H. Ji, Bin-Feng Huang, Y. Park, Seong-Hyung Park, Heui-Seung Lee, Dae-Byung Kim, Ui-Sik Kim, Han-Seob Cha, Sang Hu, Jeong‐gun Lee, H. Lee","doi":"10.1109/IWJT.2004.1306775","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306775","url":null,"abstract":"NiSi is an attractive silicide material to be applied in the nanoscale CMOSFETs. However, degradation of NiSi film after the post-silicidation annealing is one of serious demerits of NiSi. Ni/Co bi-layer is known as one of the most stable silicide structure for the improvement of the thermal stability. The formed bi-layer consists of the upper protection layer (CoSi/sub x/) and the lower conduction layer (NiSi) and their roles are different from each other. In this study, optimization of Ni/Co ratio and process condition is investigated for the nanoscale CMOSFETs.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131742863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306771
W. Taylor, E. Verret, C. Capasso, J. Nguyen, L. La, E. Luckowski, A. Martínez, C. Happ, J. Schaeffer, M. Raymond, P. Tobin
It is well accepted that one of the key parasitic resistances in ULSI transistors is the contact resistance between the silicide and the doped source/drain. In this paper, we investigate the individual components of this parameter. We show that the contact length is already a contributor at the 90 and 65nm nodes. Changing active doping in the Si via dose/energy modulations can reduce contact resistance in a low temperature flow, but not sufficiently to match results at high temperature. The largest knob is barrier height, leading some to consider moving to 2 different materials for contact to N+ and P+ regions (to replace a single silicide) which, although more complicated for processing may provide significant reductions in resistance. Using modifications to standard test structures and evaluation techniques, it becomes feasible to isolate the individual components of resistance, and to make significant progress in reducing this resistance.
{"title":"Contacts and junctions for the 45nm node","authors":"W. Taylor, E. Verret, C. Capasso, J. Nguyen, L. La, E. Luckowski, A. Martínez, C. Happ, J. Schaeffer, M. Raymond, P. Tobin","doi":"10.1109/IWJT.2004.1306771","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306771","url":null,"abstract":"It is well accepted that one of the key parasitic resistances in ULSI transistors is the contact resistance between the silicide and the doped source/drain. In this paper, we investigate the individual components of this parameter. We show that the contact length is already a contributor at the 90 and 65nm nodes. Changing active doping in the Si via dose/energy modulations can reduce contact resistance in a low temperature flow, but not sufficiently to match results at high temperature. The largest knob is barrier height, leading some to consider moving to 2 different materials for contact to N+ and P+ regions (to replace a single silicide) which, although more complicated for processing may provide significant reductions in resistance. Using modifications to standard test structures and evaluation techniques, it becomes feasible to isolate the individual components of resistance, and to make significant progress in reducing this resistance.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134379173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306844
L. Chou, H. Lu, L. Chen, J. Huang
Effects of ion-implantation and substrate orientation on nanostructures and photoluminescence (PL) of the ultra-thin /spl beta/-FeSi/sub 2/ films were investigated. Ion-implantation was found to enhance the formation of /spl beta/-FeSi/sub 2/. PL characteristics were strongly affected by implantation species and substrate orientation. The strongest intensity of PL was observed in epitaxial /spl beta/-FeSi/sub 2/ ultra-thin films on BF/sub 2//sup +/-implanted (111)Si.
{"title":"Effects of ion-implantation on light-emitting FeSi/sub 2/ shallow junction","authors":"L. Chou, H. Lu, L. Chen, J. Huang","doi":"10.1109/IWJT.2004.1306844","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306844","url":null,"abstract":"Effects of ion-implantation and substrate orientation on nanostructures and photoluminescence (PL) of the ultra-thin /spl beta/-FeSi/sub 2/ films were investigated. Ion-implantation was found to enhance the formation of /spl beta/-FeSi/sub 2/. PL characteristics were strongly affected by implantation species and substrate orientation. The strongest intensity of PL was observed in epitaxial /spl beta/-FeSi/sub 2/ ultra-thin films on BF/sub 2//sup +/-implanted (111)Si.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117290893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306745
Simon Yang, Hanming Wu
Providing leading edge Si foundry service is a complicated operation. It requires advanced technology, consistent quality, and flexible service at low cost. Optimizing technology development strategies in terms of research directions, capital investment timing, rapid execution, and smooth manufacturing transition are of pivotal importance to the success of a premium foundry provider. In this talk, we would like to share our experiences and learning on the technology requirement for operating a leading edge foundry in mainland China, together with our research & development practices to provide these technologies. The talk will focus on the following areas: Timing for core technology development equipment maturity vs time; development cost vs time; foundry volume ramp vs time. Technology performance benchmark with world leaders and technology development roadmap. Integrated technology portfolio for providing premium services to world-class customers with SOC requirements. Partnership with schools, research institutes, equipment vendors, and customers.
{"title":"Technology requirement for leading edge foundry operation in mainland China","authors":"Simon Yang, Hanming Wu","doi":"10.1109/IWJT.2004.1306745","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306745","url":null,"abstract":"Providing leading edge Si foundry service is a complicated operation. It requires advanced technology, consistent quality, and flexible service at low cost. Optimizing technology development strategies in terms of research directions, capital investment timing, rapid execution, and smooth manufacturing transition are of pivotal importance to the success of a premium foundry provider. In this talk, we would like to share our experiences and learning on the technology requirement for operating a leading edge foundry in mainland China, together with our research & development practices to provide these technologies. The talk will focus on the following areas: Timing for core technology development equipment maturity vs time; development cost vs time; foundry volume ramp vs time. Technology performance benchmark with world leaders and technology development roadmap. Integrated technology portfolio for providing premium services to world-class customers with SOC requirements. Partnership with schools, research institutes, equipment vendors, and customers.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114580530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306845
R. Yang, J.S. Luo, J. Tu, R. Zhang
Sub-threshold characteristics of strained SiGe PMOSFETs and Si PMOSFETs are theoretically analyzed with simplified but effective models, then are simulated and compared by using a two-dimensional simulator. Sub-threshold current and sub-threshold slope varying with vertical structure parameters are also studied. Simulation results are well consistent with the theoretical analysis, and show that the sub-threshold characteristics of strained SiGe PMOSFETs, which are worse than those of Si PMOSFETs, are sensitive to vertical structure parameters and worth carefully paying attention to.
{"title":"The influence of strained SiGe thin layer and correlative structure parameters on sub-threshold characteristics of SiGe PMOSFETs","authors":"R. Yang, J.S. Luo, J. Tu, R. Zhang","doi":"10.1109/IWJT.2004.1306845","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306845","url":null,"abstract":"Sub-threshold characteristics of strained SiGe PMOSFETs and Si PMOSFETs are theoretically analyzed with simplified but effective models, then are simulated and compared by using a two-dimensional simulator. Sub-threshold current and sub-threshold slope varying with vertical structure parameters are also studied. Simulation results are well consistent with the theoretical analysis, and show that the sub-threshold characteristics of strained SiGe PMOSFETs, which are worse than those of Si PMOSFETs, are sensitive to vertical structure parameters and worth carefully paying attention to.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114820740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306766
T. Matsukawa, C. Yasumuro, M. Masahara, H. Tanoue, S. Kanemaru
We used scanning nonlinear dielectric microscopy (SNDM) to diagnose doping integrity in a transistor. Non-linear capacitance (dC/dV) profiling and pinpoint capacitance-voltage analysis were implemented by SNDM and the results clearly discriminated a depletion layer in a n/sup +//p junction and tailing of the carrier distribution due to out-diffusion of dopants. The carrier state analysis was applied to n/sup +//p/n/sup +/ transistor-channel structures formed with different process parameters. An increase in the n/sup +/ activation temperature from 800 to 950/spl deg/C caused narrowing of the p-type region in the channel. A decrease in the substrate doping concentration from 10/sup 18/ to 10/sup 17/ cm/sup -3/ caused depletion of the entire channel when the gate length was less than 200 nm.
{"title":"Accurate profiling of PN junction carrier concentration by scanning nonlinear dielectric microscopy (SNDM)","authors":"T. Matsukawa, C. Yasumuro, M. Masahara, H. Tanoue, S. Kanemaru","doi":"10.1109/IWJT.2004.1306766","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306766","url":null,"abstract":"We used scanning nonlinear dielectric microscopy (SNDM) to diagnose doping integrity in a transistor. Non-linear capacitance (dC/dV) profiling and pinpoint capacitance-voltage analysis were implemented by SNDM and the results clearly discriminated a depletion layer in a n/sup +//p junction and tailing of the carrier distribution due to out-diffusion of dopants. The carrier state analysis was applied to n/sup +//p/n/sup +/ transistor-channel structures formed with different process parameters. An increase in the n/sup +/ activation temperature from 800 to 950/spl deg/C caused narrowing of the p-type region in the channel. A decrease in the substrate doping concentration from 10/sup 18/ to 10/sup 17/ cm/sup -3/ caused depletion of the entire channel when the gate length was less than 200 nm.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127569538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306757
S. Baek, S. Heo, Hyejuncg Choi, H. Hwang
The low-temperature pre-annealing effects on ultrashallow junctions were investigated. p/sup +//n and n/sup +//p ultrashallow junctions were prepared by low energy B/sub 2/H/sub 6/ & PH/sub 3/ plasma doping (PLAD) and excimer laser annealing (ELA). For the p/sup +//n junction, the junction depth was reduced significantly with increasing the pre-annealing temperature from 300/spl deg/C to 500/spl deg/. For the n/sup +//p junction, the dopant deactivation with subsequent annealing was reduced from 60/spl sim/80% to 20/spl sim/40% by low-temperature pre-annealing. The significant improvements of ultrashallow junction characteristics were attributed to the reduction of point defects by low-temperature preannealing.
{"title":"Characteristics of low-temperature preannealing effects on laser-annealed P/sup +//N and N/sup +//P ultra-shallow junctions","authors":"S. Baek, S. Heo, Hyejuncg Choi, H. Hwang","doi":"10.1109/IWJT.2004.1306757","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306757","url":null,"abstract":"The low-temperature pre-annealing effects on ultrashallow junctions were investigated. p/sup +//n and n/sup +//p ultrashallow junctions were prepared by low energy B/sub 2/H/sub 6/ & PH/sub 3/ plasma doping (PLAD) and excimer laser annealing (ELA). For the p/sup +//n junction, the junction depth was reduced significantly with increasing the pre-annealing temperature from 300/spl deg/C to 500/spl deg/. For the n/sup +//p junction, the dopant deactivation with subsequent annealing was reduced from 60/spl sim/80% to 20/spl sim/40% by low-temperature pre-annealing. The significant improvements of ultrashallow junction characteristics were attributed to the reduction of point defects by low-temperature preannealing.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123707499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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