Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306801
S. Tan, H.R. Chen, W.T. Chen, M. Chu, W. Lour
We have been successfully implemented for the InGaP/GaAs heterojunction bipolar transistors (HBTs) with the sulfur-treated GaAs base layer comparing with HBTs fabricated using emitter-edge thinning InGaP layer. As compared with non-passivated HBTs with an exposed extrinsic GaAs base, the improved base leakage current for InGaP-passivated HBTs is due to the inherent low surface recombination velocity associated with an InGaP layer. In views of the sulfur-passivated HBTs exhibited an enhanced current gain is attributed to the modification of the GaAs surface electronic properties. The maximum dc current gain available is 75 at low base current for sulfur-passivated HBTs. The sulfur-passivated devices also exhibit very good linearity in wide range of collector (10/sup -5/ to 10/sup -1/ A). Furthermore, detailed sulfur-treatment conditions and effects on device performance are investigated.
{"title":"Sulfur- and InGaP-passivated heterojunction bipolar transistors","authors":"S. Tan, H.R. Chen, W.T. Chen, M. Chu, W. Lour","doi":"10.1109/IWJT.2004.1306801","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306801","url":null,"abstract":"We have been successfully implemented for the InGaP/GaAs heterojunction bipolar transistors (HBTs) with the sulfur-treated GaAs base layer comparing with HBTs fabricated using emitter-edge thinning InGaP layer. As compared with non-passivated HBTs with an exposed extrinsic GaAs base, the improved base leakage current for InGaP-passivated HBTs is due to the inherent low surface recombination velocity associated with an InGaP layer. In views of the sulfur-passivated HBTs exhibited an enhanced current gain is attributed to the modification of the GaAs surface electronic properties. The maximum dc current gain available is 75 at low base current for sulfur-passivated HBTs. The sulfur-passivated devices also exhibit very good linearity in wide range of collector (10/sup -5/ to 10/sup -1/ A). Furthermore, detailed sulfur-treatment conditions and effects on device performance are investigated.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127099243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306865
Xiaokang Shi, Min Yu, Jun Yin, Guoyan Zhang, Ru Huang, Xing Zhang
The paper addresses a precise and efficient analytical method of realistic dopant fluctuations in shallow junction formation. To reach the analytical method, millions of simulations are finished, and data of simulation results are analyzed. The analytical function of the method is without any additional fitting parameters and can be used to calculate the standard deviation and normalized standard deviation at different depths of the shallow junctions. And some simulation results of characteristics variation of devices are also shown in this paper.
{"title":"A precise and efficient analytical method of realistic dopant fluctuations in shallow junction formation","authors":"Xiaokang Shi, Min Yu, Jun Yin, Guoyan Zhang, Ru Huang, Xing Zhang","doi":"10.1109/IWJT.2004.1306865","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306865","url":null,"abstract":"The paper addresses a precise and efficient analytical method of realistic dopant fluctuations in shallow junction formation. To reach the analytical method, millions of simulations are finished, and data of simulation results are analyzed. The analytical function of the method is without any additional fitting parameters and can be used to calculate the standard deviation and normalized standard deviation at different depths of the shallow junctions. And some simulation results of characteristics variation of devices are also shown in this paper.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"418 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113967126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306797
S. Tan, W.T. Chen, M. Chu, W. Lour
This paper reports a new sub-0.5-/spl mu/m gate-length FET processing technique by using conventional i-line optical lithography. The key methodology is to thermally re-flow the patterned photo-resist upon two-step spin-coated SOG. According to this new process, the deposited gate metal has its final length and thickness be separately determined by taped resist profile and SOG thickness. The implemented gate length is as short as 0.41 /spl mu/m. Then it was successfully applied to fabrication of a newly designed hetero-doped-channel field-effect transistor with digital-graded In/sub x/Ga/sub 1-x/As multi-layer forming a HEMT-like channel. This digital-graded In/sub x/Ga/sub l-x/As channel by changing x values from 0.1 to 0.2 has most electrons be closer to gate metal. The measured sheet carrier density and mobility are 4.3 /spl times/ 10/sup 12/ cm/sup -2/ and 3560 cm/sup 2/V/sup -1/s/sup -1/ while the peak carrier concentration is larger than 1 /spl times/ 10/sup 19/ cm/sup -3/. A fabricated 0.41 /spl times/ 100 /spl mu/m/sup 2/ HDCFET exhibits the maximum transconductance of 370 mS/mm with an output current lager than 535 mA/mm and ft (f max) of 26 (32) GHz.
{"title":"An economic method for fabrication sub-quarter-/spl mu/m gate doped-channel FET's by photolithography","authors":"S. Tan, W.T. Chen, M. Chu, W. Lour","doi":"10.1109/IWJT.2004.1306797","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306797","url":null,"abstract":"This paper reports a new sub-0.5-/spl mu/m gate-length FET processing technique by using conventional i-line optical lithography. The key methodology is to thermally re-flow the patterned photo-resist upon two-step spin-coated SOG. According to this new process, the deposited gate metal has its final length and thickness be separately determined by taped resist profile and SOG thickness. The implemented gate length is as short as 0.41 /spl mu/m. Then it was successfully applied to fabrication of a newly designed hetero-doped-channel field-effect transistor with digital-graded In/sub x/Ga/sub 1-x/As multi-layer forming a HEMT-like channel. This digital-graded In/sub x/Ga/sub l-x/As channel by changing x values from 0.1 to 0.2 has most electrons be closer to gate metal. The measured sheet carrier density and mobility are 4.3 /spl times/ 10/sup 12/ cm/sup -2/ and 3560 cm/sup 2/V/sup -1/s/sup -1/ while the peak carrier concentration is larger than 1 /spl times/ 10/sup 19/ cm/sup -3/. A fabricated 0.41 /spl times/ 100 /spl mu/m/sup 2/ HDCFET exhibits the maximum transconductance of 370 mS/mm with an output current lager than 535 mA/mm and ft (f max) of 26 (32) GHz.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114531456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306870
Jin He, X. Xi, H. Wan, M. Chan, A. Niknejad, C. Hu
This paper outlines the advanced Surface-Potential-Plus (SPP) approach for the next generation CMOS device modeling. The main object of this approach is to develop a continuous, completely symmetric and accurate advanced charge-based MOS transistor model from the basic device physics including various physics effects. A unified exact inversion charge relation valid for uniform and retrograde doping cases is first obtained. Various small dimensional effects are elucidated and integrated concisely into this model. Comparison with measured data is finally presented to validate the new model. Importantly, it was also extended to UTB and double-gate MOSFETs.
{"title":"Surface-potential-plus approach for next generation CMOS device modeling","authors":"Jin He, X. Xi, H. Wan, M. Chan, A. Niknejad, C. Hu","doi":"10.1109/IWJT.2004.1306870","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306870","url":null,"abstract":"This paper outlines the advanced Surface-Potential-Plus (SPP) approach for the next generation CMOS device modeling. The main object of this approach is to develop a continuous, completely symmetric and accurate advanced charge-based MOS transistor model from the basic device physics including various physics effects. A unified exact inversion charge relation valid for uniform and retrograde doping cases is first obtained. Various small dimensional effects are elucidated and integrated concisely into this model. Comparison with measured data is finally presented to validate the new model. Importantly, it was also extended to UTB and double-gate MOSFETs.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122955152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306853
L. Sun, X.Y. Liu, G. Du, J. Kang, X. Guan, R. Han
The Schottky barrier MOSFETs with channel length of 70 nm have been fabricated with sidewall etchback technology. The conventional lithography is applied for the definition of the sub-100 nm channel region. In the process, the advanced lithography technology has not been involved. The SOI structure has been used to take place of the bulk silicon substrate, and the silicon on the source and drain has been transformed to silicide. The thermal emission leakage current is reduced due to the decrease of the area of the source/drain Schottky contact.
{"title":"Fabrication of the sub-100 nm thin body SOI Schottky barrier tunneling transistors with sidewall etchback technology","authors":"L. Sun, X.Y. Liu, G. Du, J. Kang, X. Guan, R. Han","doi":"10.1109/IWJT.2004.1306853","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306853","url":null,"abstract":"The Schottky barrier MOSFETs with channel length of 70 nm have been fabricated with sidewall etchback technology. The conventional lithography is applied for the definition of the sub-100 nm channel region. In the process, the advanced lithography technology has not been involved. The SOI structure has been used to take place of the bulk silicon substrate, and the silicon on the source and drain has been transformed to silicide. The thermal emission leakage current is reduced due to the decrease of the area of the source/drain Schottky contact.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126869251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306844
L. Chou, H. Lu, L. Chen, J. Huang
Effects of ion-implantation and substrate orientation on nanostructures and photoluminescence (PL) of the ultra-thin /spl beta/-FeSi/sub 2/ films were investigated. Ion-implantation was found to enhance the formation of /spl beta/-FeSi/sub 2/. PL characteristics were strongly affected by implantation species and substrate orientation. The strongest intensity of PL was observed in epitaxial /spl beta/-FeSi/sub 2/ ultra-thin films on BF/sub 2//sup +/-implanted (111)Si.
{"title":"Effects of ion-implantation on light-emitting FeSi/sub 2/ shallow junction","authors":"L. Chou, H. Lu, L. Chen, J. Huang","doi":"10.1109/IWJT.2004.1306844","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306844","url":null,"abstract":"Effects of ion-implantation and substrate orientation on nanostructures and photoluminescence (PL) of the ultra-thin /spl beta/-FeSi/sub 2/ films were investigated. Ion-implantation was found to enhance the formation of /spl beta/-FeSi/sub 2/. PL characteristics were strongly affected by implantation species and substrate orientation. The strongest intensity of PL was observed in epitaxial /spl beta/-FeSi/sub 2/ ultra-thin films on BF/sub 2//sup +/-implanted (111)Si.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117290893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306745
Simon Yang, Hanming Wu
Providing leading edge Si foundry service is a complicated operation. It requires advanced technology, consistent quality, and flexible service at low cost. Optimizing technology development strategies in terms of research directions, capital investment timing, rapid execution, and smooth manufacturing transition are of pivotal importance to the success of a premium foundry provider. In this talk, we would like to share our experiences and learning on the technology requirement for operating a leading edge foundry in mainland China, together with our research & development practices to provide these technologies. The talk will focus on the following areas: Timing for core technology development equipment maturity vs time; development cost vs time; foundry volume ramp vs time. Technology performance benchmark with world leaders and technology development roadmap. Integrated technology portfolio for providing premium services to world-class customers with SOC requirements. Partnership with schools, research institutes, equipment vendors, and customers.
{"title":"Technology requirement for leading edge foundry operation in mainland China","authors":"Simon Yang, Hanming Wu","doi":"10.1109/IWJT.2004.1306745","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306745","url":null,"abstract":"Providing leading edge Si foundry service is a complicated operation. It requires advanced technology, consistent quality, and flexible service at low cost. Optimizing technology development strategies in terms of research directions, capital investment timing, rapid execution, and smooth manufacturing transition are of pivotal importance to the success of a premium foundry provider. In this talk, we would like to share our experiences and learning on the technology requirement for operating a leading edge foundry in mainland China, together with our research & development practices to provide these technologies. The talk will focus on the following areas: Timing for core technology development equipment maturity vs time; development cost vs time; foundry volume ramp vs time. Technology performance benchmark with world leaders and technology development roadmap. Integrated technology portfolio for providing premium services to world-class customers with SOC requirements. Partnership with schools, research institutes, equipment vendors, and customers.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114580530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306845
R. Yang, J.S. Luo, J. Tu, R. Zhang
Sub-threshold characteristics of strained SiGe PMOSFETs and Si PMOSFETs are theoretically analyzed with simplified but effective models, then are simulated and compared by using a two-dimensional simulator. Sub-threshold current and sub-threshold slope varying with vertical structure parameters are also studied. Simulation results are well consistent with the theoretical analysis, and show that the sub-threshold characteristics of strained SiGe PMOSFETs, which are worse than those of Si PMOSFETs, are sensitive to vertical structure parameters and worth carefully paying attention to.
{"title":"The influence of strained SiGe thin layer and correlative structure parameters on sub-threshold characteristics of SiGe PMOSFETs","authors":"R. Yang, J.S. Luo, J. Tu, R. Zhang","doi":"10.1109/IWJT.2004.1306845","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306845","url":null,"abstract":"Sub-threshold characteristics of strained SiGe PMOSFETs and Si PMOSFETs are theoretically analyzed with simplified but effective models, then are simulated and compared by using a two-dimensional simulator. Sub-threshold current and sub-threshold slope varying with vertical structure parameters are also studied. Simulation results are well consistent with the theoretical analysis, and show that the sub-threshold characteristics of strained SiGe PMOSFETs, which are worse than those of Si PMOSFETs, are sensitive to vertical structure parameters and worth carefully paying attention to.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114820740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306766
T. Matsukawa, C. Yasumuro, M. Masahara, H. Tanoue, S. Kanemaru
We used scanning nonlinear dielectric microscopy (SNDM) to diagnose doping integrity in a transistor. Non-linear capacitance (dC/dV) profiling and pinpoint capacitance-voltage analysis were implemented by SNDM and the results clearly discriminated a depletion layer in a n/sup +//p junction and tailing of the carrier distribution due to out-diffusion of dopants. The carrier state analysis was applied to n/sup +//p/n/sup +/ transistor-channel structures formed with different process parameters. An increase in the n/sup +/ activation temperature from 800 to 950/spl deg/C caused narrowing of the p-type region in the channel. A decrease in the substrate doping concentration from 10/sup 18/ to 10/sup 17/ cm/sup -3/ caused depletion of the entire channel when the gate length was less than 200 nm.
{"title":"Accurate profiling of PN junction carrier concentration by scanning nonlinear dielectric microscopy (SNDM)","authors":"T. Matsukawa, C. Yasumuro, M. Masahara, H. Tanoue, S. Kanemaru","doi":"10.1109/IWJT.2004.1306766","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306766","url":null,"abstract":"We used scanning nonlinear dielectric microscopy (SNDM) to diagnose doping integrity in a transistor. Non-linear capacitance (dC/dV) profiling and pinpoint capacitance-voltage analysis were implemented by SNDM and the results clearly discriminated a depletion layer in a n/sup +//p junction and tailing of the carrier distribution due to out-diffusion of dopants. The carrier state analysis was applied to n/sup +//p/n/sup +/ transistor-channel structures formed with different process parameters. An increase in the n/sup +/ activation temperature from 800 to 950/spl deg/C caused narrowing of the p-type region in the channel. A decrease in the substrate doping concentration from 10/sup 18/ to 10/sup 17/ cm/sup -3/ caused depletion of the entire channel when the gate length was less than 200 nm.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127569538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306757
S. Baek, S. Heo, Hyejuncg Choi, H. Hwang
The low-temperature pre-annealing effects on ultrashallow junctions were investigated. p/sup +//n and n/sup +//p ultrashallow junctions were prepared by low energy B/sub 2/H/sub 6/ & PH/sub 3/ plasma doping (PLAD) and excimer laser annealing (ELA). For the p/sup +//n junction, the junction depth was reduced significantly with increasing the pre-annealing temperature from 300/spl deg/C to 500/spl deg/. For the n/sup +//p junction, the dopant deactivation with subsequent annealing was reduced from 60/spl sim/80% to 20/spl sim/40% by low-temperature pre-annealing. The significant improvements of ultrashallow junction characteristics were attributed to the reduction of point defects by low-temperature preannealing.
{"title":"Characteristics of low-temperature preannealing effects on laser-annealed P/sup +//N and N/sup +//P ultra-shallow junctions","authors":"S. Baek, S. Heo, Hyejuncg Choi, H. Hwang","doi":"10.1109/IWJT.2004.1306757","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306757","url":null,"abstract":"The low-temperature pre-annealing effects on ultrashallow junctions were investigated. p/sup +//n and n/sup +//p ultrashallow junctions were prepared by low energy B/sub 2/H/sub 6/ & PH/sub 3/ plasma doping (PLAD) and excimer laser annealing (ELA). For the p/sup +//n junction, the junction depth was reduced significantly with increasing the pre-annealing temperature from 300/spl deg/C to 500/spl deg/. For the n/sup +//p junction, the dopant deactivation with subsequent annealing was reduced from 60/spl sim/80% to 20/spl sim/40% by low-temperature pre-annealing. The significant improvements of ultrashallow junction characteristics were attributed to the reduction of point defects by low-temperature preannealing.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123707499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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