Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306826
S. Tan, W.T. Chen, M. Chu, W. Lour
We reported the fabrication, characterization and modeling of a heterojunction phototransistor. Both Gummel-plot and common-emitter configurations are employed to characterize HPT's performances and to clearly demonstrate what difference between a voltage-biased and a current-biased HPT. The performances of the voltage- and current-source biased HPTs were also compared to the results from a newly proposed HPT model and related circuit with good agreement found. Although an independent voltage source pushes HBT's operating point to a higher current level. where the dc current gain is larger, however, the photocurrent generated within B-C region gives very little contribution to final collector current. The optical gain obtained from high-voltage-source biased HPT is even smaller than that of a HPT with a floating base. In addition, a modified extended Ebers-Moll model was successfully used to analyze what the common-emitter characteristics and Gummel-plot differences with input base current as well as base-en-Litter voltage between the dark and illumination situation.
{"title":"A new model for the phototransistor","authors":"S. Tan, W.T. Chen, M. Chu, W. Lour","doi":"10.1109/IWJT.2004.1306826","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306826","url":null,"abstract":"We reported the fabrication, characterization and modeling of a heterojunction phototransistor. Both Gummel-plot and common-emitter configurations are employed to characterize HPT's performances and to clearly demonstrate what difference between a voltage-biased and a current-biased HPT. The performances of the voltage- and current-source biased HPTs were also compared to the results from a newly proposed HPT model and related circuit with good agreement found. Although an independent voltage source pushes HBT's operating point to a higher current level. where the dc current gain is larger, however, the photocurrent generated within B-C region gives very little contribution to final collector current. The optical gain obtained from high-voltage-source biased HPT is even smaller than that of a HPT with a floating base. In addition, a modified extended Ebers-Moll model was successfully used to analyze what the common-emitter characteristics and Gummel-plot differences with input base current as well as base-en-Litter voltage between the dark and illumination situation.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122780918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306848
Ning Deng, L. Pan, Lei Zhang, Pei-yi Chen
A modified memory cell using self-assembled Ge quantum dots as float gate is proposed for DRAM application. The vertical structure is strained SiGe channel/n-Si/i-SiGe/n-Si/Ge dots/SiO/sub 2//poly-Si gate. The inside n-Si/i-SiGe/n-Si double barrier acts as tunneling barrier for hole instead of conventional tunneling silicon oxide layer. The function and advantages of the device were analyzed primarily. This novel structure can also be developed to realize non-volatile memory operating at low voltage, if hetero-structure materials system with appropriate band alignment is found.
{"title":"Ge quantum dot memory realized with vertical Si/SiGe resonant tunneling structure","authors":"Ning Deng, L. Pan, Lei Zhang, Pei-yi Chen","doi":"10.1109/IWJT.2004.1306848","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306848","url":null,"abstract":"A modified memory cell using self-assembled Ge quantum dots as float gate is proposed for DRAM application. The vertical structure is strained SiGe channel/n-Si/i-SiGe/n-Si/Ge dots/SiO/sub 2//poly-Si gate. The inside n-Si/i-SiGe/n-Si double barrier acts as tunneling barrier for hole instead of conventional tunneling silicon oxide layer. The function and advantages of the device were analyzed primarily. This novel structure can also be developed to realize non-volatile memory operating at low voltage, if hetero-structure materials system with appropriate band alignment is found.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127565311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306861
Min Yu, Ru Huang, Xiaokang Shil, Huihui Jil, Xing Zhang, Yangyuan Wang, H. Oka
Atomistic modeling has been applied in studying and simulating the advanced junction technologies. We present in this paper the application of molecular dynamics method in simulation of low energy ion implantation and that of kinetic Monte Carlo method in simulation of enhanced diffusion in annealing. The dose dependent ultra-low energy implantation is well simulated. The simulation indicates that energy contamination is not as serious as it looks. The dissipation of Si extended defects are simulated for both 40 keV and 5 keV Si implantation cases. Enhanced diffusion is simulated.
{"title":"Studying shallow junction technology by atomistic modeling","authors":"Min Yu, Ru Huang, Xiaokang Shil, Huihui Jil, Xing Zhang, Yangyuan Wang, H. Oka","doi":"10.1109/IWJT.2004.1306861","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306861","url":null,"abstract":"Atomistic modeling has been applied in studying and simulating the advanced junction technologies. We present in this paper the application of molecular dynamics method in simulation of low energy ion implantation and that of kinetic Monte Carlo method in simulation of enhanced diffusion in annealing. The dose dependent ultra-low energy implantation is well simulated. The simulation indicates that energy contamination is not as serious as it looks. The dissipation of Si extended defects are simulated for both 40 keV and 5 keV Si implantation cases. Enhanced diffusion is simulated.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"2005 20","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132679893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306868
T. Toyabe
A 2D and 3D density gradient model is described. Drain current characteristics taking quantum effects into consideration are simulated for extremely scaled bulk nMOSFETs with nanometer channel length and decananoscale tri-gate FinFETs.
{"title":"Two and three dimensional MOSFETs simulation with density gradient model","authors":"T. Toyabe","doi":"10.1109/IWJT.2004.1306868","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306868","url":null,"abstract":"A 2D and 3D density gradient model is described. Drain current characteristics taking quantum effects into consideration are simulated for extremely scaled bulk nMOSFETs with nanometer channel length and decananoscale tri-gate FinFETs.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132348258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306799
Chun-Yuan Chen, C. Uang, S. Cheng, H. Chuang, S. Fu, Ching-Hsiu Tsai, Chi-Yuan Chang, Wen-Chau Liu
The DC performances of a novel InP/InGaAs tunneling emitter bipolar transistor (TEBT) are studied and demonstrated. The studied device can be operated under an extremely wide collector current regime larger than 11 decades in magnitude (10/sup -12/ to 10/sup -1/A). A current gain of 3 is obtained even operated at an ultra-low collector current of 3.9 /spl times/ 10/sup -12/A (1.56 /spl times/ 10/sup -7/ A/cm/sup 2/). The common-emitter and common-base breakdown voltages of the studied device are higher than 2 and 5V, respectively. Furthermore, a very low collector-emitter offset voltage of 40mV is found. The temperature-dependent DC characteristics of the TEBT are measured and studied. Consequentially, based on experimental results, the studied device provides the promise for low-power electronics applications.
{"title":"Characteristics of an InP/InGaAs tunneling emitter bipolar transistor (TEBT)","authors":"Chun-Yuan Chen, C. Uang, S. Cheng, H. Chuang, S. Fu, Ching-Hsiu Tsai, Chi-Yuan Chang, Wen-Chau Liu","doi":"10.1109/IWJT.2004.1306799","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306799","url":null,"abstract":"The DC performances of a novel InP/InGaAs tunneling emitter bipolar transistor (TEBT) are studied and demonstrated. The studied device can be operated under an extremely wide collector current regime larger than 11 decades in magnitude (10/sup -12/ to 10/sup -1/A). A current gain of 3 is obtained even operated at an ultra-low collector current of 3.9 /spl times/ 10/sup -12/A (1.56 /spl times/ 10/sup -7/ A/cm/sup 2/). The common-emitter and common-base breakdown voltages of the studied device are higher than 2 and 5V, respectively. Furthermore, a very low collector-emitter offset voltage of 40mV is found. The temperature-dependent DC characteristics of the TEBT are measured and studied. Consequentially, based on experimental results, the studied device provides the promise for low-power electronics applications.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134294054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Graded Ge fraction SiGe film was grown by using newly-designed SGE500 SiGe UHV/CVD system. The film quality was determined by X-ray diffraction. SiGe hetero-junction bipolar transistor (HBT) device with this SiGe film was made. Results showed that the quality of the graded SiGe film was high and the SiGe HBT device had good electrical performance.
{"title":"Growth of graded SiGe films by novel UHV/CVD system","authors":"Wentao Huang, Changchun Chen, Xiaoyi Xiong, Zhihong Liu, Wei Zhang, P. Tsien","doi":"10.1109/IWJT.2004.1306856","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306856","url":null,"abstract":"Graded Ge fraction SiGe film was grown by using newly-designed SGE500 SiGe UHV/CVD system. The film quality was determined by X-ray diffraction. SiGe hetero-junction bipolar transistor (HBT) device with this SiGe film was made. Results showed that the quality of the graded SiGe film was high and the SiGe HBT device had good electrical performance.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"232 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133051581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306775
J. Yun, Soon-Young Oh, H. Ji, Bin-Feng Huang, Y. Park, Seong-Hyung Park, Heui-Seung Lee, Dae-Byung Kim, Ui-Sik Kim, Han-Seob Cha, Sang Hu, Jeong‐gun Lee, H. Lee
NiSi is an attractive silicide material to be applied in the nanoscale CMOSFETs. However, degradation of NiSi film after the post-silicidation annealing is one of serious demerits of NiSi. Ni/Co bi-layer is known as one of the most stable silicide structure for the improvement of the thermal stability. The formed bi-layer consists of the upper protection layer (CoSi/sub x/) and the lower conduction layer (NiSi) and their roles are different from each other. In this study, optimization of Ni/Co ratio and process condition is investigated for the nanoscale CMOSFETs.
{"title":"Optimal Ni/Co thickness extraction and two step rapid thermal process of the nickel-silicide for nanoscale complementary metal oxide semiconductor (CMOS) application","authors":"J. Yun, Soon-Young Oh, H. Ji, Bin-Feng Huang, Y. Park, Seong-Hyung Park, Heui-Seung Lee, Dae-Byung Kim, Ui-Sik Kim, Han-Seob Cha, Sang Hu, Jeong‐gun Lee, H. Lee","doi":"10.1109/IWJT.2004.1306775","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306775","url":null,"abstract":"NiSi is an attractive silicide material to be applied in the nanoscale CMOSFETs. However, degradation of NiSi film after the post-silicidation annealing is one of serious demerits of NiSi. Ni/Co bi-layer is known as one of the most stable silicide structure for the improvement of the thermal stability. The formed bi-layer consists of the upper protection layer (CoSi/sub x/) and the lower conduction layer (NiSi) and their roles are different from each other. In this study, optimization of Ni/Co ratio and process condition is investigated for the nanoscale CMOSFETs.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131742863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306771
W. Taylor, E. Verret, C. Capasso, J. Nguyen, L. La, E. Luckowski, A. Martínez, C. Happ, J. Schaeffer, M. Raymond, P. Tobin
It is well accepted that one of the key parasitic resistances in ULSI transistors is the contact resistance between the silicide and the doped source/drain. In this paper, we investigate the individual components of this parameter. We show that the contact length is already a contributor at the 90 and 65nm nodes. Changing active doping in the Si via dose/energy modulations can reduce contact resistance in a low temperature flow, but not sufficiently to match results at high temperature. The largest knob is barrier height, leading some to consider moving to 2 different materials for contact to N+ and P+ regions (to replace a single silicide) which, although more complicated for processing may provide significant reductions in resistance. Using modifications to standard test structures and evaluation techniques, it becomes feasible to isolate the individual components of resistance, and to make significant progress in reducing this resistance.
{"title":"Contacts and junctions for the 45nm node","authors":"W. Taylor, E. Verret, C. Capasso, J. Nguyen, L. La, E. Luckowski, A. Martínez, C. Happ, J. Schaeffer, M. Raymond, P. Tobin","doi":"10.1109/IWJT.2004.1306771","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306771","url":null,"abstract":"It is well accepted that one of the key parasitic resistances in ULSI transistors is the contact resistance between the silicide and the doped source/drain. In this paper, we investigate the individual components of this parameter. We show that the contact length is already a contributor at the 90 and 65nm nodes. Changing active doping in the Si via dose/energy modulations can reduce contact resistance in a low temperature flow, but not sufficiently to match results at high temperature. The largest knob is barrier height, leading some to consider moving to 2 different materials for contact to N+ and P+ regions (to replace a single silicide) which, although more complicated for processing may provide significant reductions in resistance. Using modifications to standard test structures and evaluation techniques, it becomes feasible to isolate the individual components of resistance, and to make significant progress in reducing this resistance.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134379173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306752
Hanming Wu, S. Lee, Xing Yu, Yong Liu, J. Chen
In the present paper, high-density plasma implantation is proposed for shallow junction formation. The inevitable low energy component in ion energy distribution function (IEDF) has been studied by theoretical and numerical methods. Finally, the device effects induced by such a low energy component in IEDF in plasma implantation are analyzed and discussed.
{"title":"Device effect of low energy implantation in high density plasma","authors":"Hanming Wu, S. Lee, Xing Yu, Yong Liu, J. Chen","doi":"10.1109/IWJT.2004.1306752","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306752","url":null,"abstract":"In the present paper, high-density plasma implantation is proposed for shallow junction formation. The inevitable low energy component in ion energy distribution function (IEDF) has been studied by theoretical and numerical methods. Finally, the device effects induced by such a low energy component in IEDF in plasma implantation are analyzed and discussed.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124093425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306755
K. Tsutsui, R. Higaki, Y. Sasaki, T. Sato, H. Tamura, B. Mizuno, H. Iwai
In the low energy plasma doping process, the contribution of not only ionized species but also neutral species to the doping process should be considered. In order to investigate such a contribution, the experiments of gas phase doping combined with Ar or He plasma pre-treatment were carried out. Gas phase impurity absorption should be affected by surface condition of Si substrates. As a result, significant increase of boron dose from neutral gas phase was observed when the substrate surface was pre-treated by Ar or He plasma prior to exposure to neutral B/sub 2/H/sub 6//He gas. It was also found that the gas phase impurity absorption was affected by substrate temperature when the surface was exposed to the neutral B/sub 2/H/sub 6//He gas.
{"title":"Contribution and control of neutral gas absorption effects in the plasma doping of boron into Si","authors":"K. Tsutsui, R. Higaki, Y. Sasaki, T. Sato, H. Tamura, B. Mizuno, H. Iwai","doi":"10.1109/IWJT.2004.1306755","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306755","url":null,"abstract":"In the low energy plasma doping process, the contribution of not only ionized species but also neutral species to the doping process should be considered. In order to investigate such a contribution, the experiments of gas phase doping combined with Ar or He plasma pre-treatment were carried out. Gas phase impurity absorption should be affected by surface condition of Si substrates. As a result, significant increase of boron dose from neutral gas phase was observed when the substrate surface was pre-treated by Ar or He plasma prior to exposure to neutral B/sub 2/H/sub 6//He gas. It was also found that the gas phase impurity absorption was affected by substrate temperature when the surface was exposed to the neutral B/sub 2/H/sub 6//He gas.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128979155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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