Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306826
S. Tan, W.T. Chen, M. Chu, W. Lour
We reported the fabrication, characterization and modeling of a heterojunction phototransistor. Both Gummel-plot and common-emitter configurations are employed to characterize HPT's performances and to clearly demonstrate what difference between a voltage-biased and a current-biased HPT. The performances of the voltage- and current-source biased HPTs were also compared to the results from a newly proposed HPT model and related circuit with good agreement found. Although an independent voltage source pushes HBT's operating point to a higher current level. where the dc current gain is larger, however, the photocurrent generated within B-C region gives very little contribution to final collector current. The optical gain obtained from high-voltage-source biased HPT is even smaller than that of a HPT with a floating base. In addition, a modified extended Ebers-Moll model was successfully used to analyze what the common-emitter characteristics and Gummel-plot differences with input base current as well as base-en-Litter voltage between the dark and illumination situation.
{"title":"A new model for the phototransistor","authors":"S. Tan, W.T. Chen, M. Chu, W. Lour","doi":"10.1109/IWJT.2004.1306826","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306826","url":null,"abstract":"We reported the fabrication, characterization and modeling of a heterojunction phototransistor. Both Gummel-plot and common-emitter configurations are employed to characterize HPT's performances and to clearly demonstrate what difference between a voltage-biased and a current-biased HPT. The performances of the voltage- and current-source biased HPTs were also compared to the results from a newly proposed HPT model and related circuit with good agreement found. Although an independent voltage source pushes HBT's operating point to a higher current level. where the dc current gain is larger, however, the photocurrent generated within B-C region gives very little contribution to final collector current. The optical gain obtained from high-voltage-source biased HPT is even smaller than that of a HPT with a floating base. In addition, a modified extended Ebers-Moll model was successfully used to analyze what the common-emitter characteristics and Gummel-plot differences with input base current as well as base-en-Litter voltage between the dark and illumination situation.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122780918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306848
Ning Deng, L. Pan, Lei Zhang, Pei-yi Chen
A modified memory cell using self-assembled Ge quantum dots as float gate is proposed for DRAM application. The vertical structure is strained SiGe channel/n-Si/i-SiGe/n-Si/Ge dots/SiO/sub 2//poly-Si gate. The inside n-Si/i-SiGe/n-Si double barrier acts as tunneling barrier for hole instead of conventional tunneling silicon oxide layer. The function and advantages of the device were analyzed primarily. This novel structure can also be developed to realize non-volatile memory operating at low voltage, if hetero-structure materials system with appropriate band alignment is found.
{"title":"Ge quantum dot memory realized with vertical Si/SiGe resonant tunneling structure","authors":"Ning Deng, L. Pan, Lei Zhang, Pei-yi Chen","doi":"10.1109/IWJT.2004.1306848","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306848","url":null,"abstract":"A modified memory cell using self-assembled Ge quantum dots as float gate is proposed for DRAM application. The vertical structure is strained SiGe channel/n-Si/i-SiGe/n-Si/Ge dots/SiO/sub 2//poly-Si gate. The inside n-Si/i-SiGe/n-Si double barrier acts as tunneling barrier for hole instead of conventional tunneling silicon oxide layer. The function and advantages of the device were analyzed primarily. This novel structure can also be developed to realize non-volatile memory operating at low voltage, if hetero-structure materials system with appropriate band alignment is found.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127565311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306861
Min Yu, Ru Huang, Xiaokang Shil, Huihui Jil, Xing Zhang, Yangyuan Wang, H. Oka
Atomistic modeling has been applied in studying and simulating the advanced junction technologies. We present in this paper the application of molecular dynamics method in simulation of low energy ion implantation and that of kinetic Monte Carlo method in simulation of enhanced diffusion in annealing. The dose dependent ultra-low energy implantation is well simulated. The simulation indicates that energy contamination is not as serious as it looks. The dissipation of Si extended defects are simulated for both 40 keV and 5 keV Si implantation cases. Enhanced diffusion is simulated.
{"title":"Studying shallow junction technology by atomistic modeling","authors":"Min Yu, Ru Huang, Xiaokang Shil, Huihui Jil, Xing Zhang, Yangyuan Wang, H. Oka","doi":"10.1109/IWJT.2004.1306861","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306861","url":null,"abstract":"Atomistic modeling has been applied in studying and simulating the advanced junction technologies. We present in this paper the application of molecular dynamics method in simulation of low energy ion implantation and that of kinetic Monte Carlo method in simulation of enhanced diffusion in annealing. The dose dependent ultra-low energy implantation is well simulated. The simulation indicates that energy contamination is not as serious as it looks. The dissipation of Si extended defects are simulated for both 40 keV and 5 keV Si implantation cases. Enhanced diffusion is simulated.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"2005 20","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132679893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306868
T. Toyabe
A 2D and 3D density gradient model is described. Drain current characteristics taking quantum effects into consideration are simulated for extremely scaled bulk nMOSFETs with nanometer channel length and decananoscale tri-gate FinFETs.
{"title":"Two and three dimensional MOSFETs simulation with density gradient model","authors":"T. Toyabe","doi":"10.1109/IWJT.2004.1306868","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306868","url":null,"abstract":"A 2D and 3D density gradient model is described. Drain current characteristics taking quantum effects into consideration are simulated for extremely scaled bulk nMOSFETs with nanometer channel length and decananoscale tri-gate FinFETs.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132348258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306799
Chun-Yuan Chen, C. Uang, S. Cheng, H. Chuang, S. Fu, Ching-Hsiu Tsai, Chi-Yuan Chang, Wen-Chau Liu
The DC performances of a novel InP/InGaAs tunneling emitter bipolar transistor (TEBT) are studied and demonstrated. The studied device can be operated under an extremely wide collector current regime larger than 11 decades in magnitude (10/sup -12/ to 10/sup -1/A). A current gain of 3 is obtained even operated at an ultra-low collector current of 3.9 /spl times/ 10/sup -12/A (1.56 /spl times/ 10/sup -7/ A/cm/sup 2/). The common-emitter and common-base breakdown voltages of the studied device are higher than 2 and 5V, respectively. Furthermore, a very low collector-emitter offset voltage of 40mV is found. The temperature-dependent DC characteristics of the TEBT are measured and studied. Consequentially, based on experimental results, the studied device provides the promise for low-power electronics applications.
{"title":"Characteristics of an InP/InGaAs tunneling emitter bipolar transistor (TEBT)","authors":"Chun-Yuan Chen, C. Uang, S. Cheng, H. Chuang, S. Fu, Ching-Hsiu Tsai, Chi-Yuan Chang, Wen-Chau Liu","doi":"10.1109/IWJT.2004.1306799","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306799","url":null,"abstract":"The DC performances of a novel InP/InGaAs tunneling emitter bipolar transistor (TEBT) are studied and demonstrated. The studied device can be operated under an extremely wide collector current regime larger than 11 decades in magnitude (10/sup -12/ to 10/sup -1/A). A current gain of 3 is obtained even operated at an ultra-low collector current of 3.9 /spl times/ 10/sup -12/A (1.56 /spl times/ 10/sup -7/ A/cm/sup 2/). The common-emitter and common-base breakdown voltages of the studied device are higher than 2 and 5V, respectively. Furthermore, a very low collector-emitter offset voltage of 40mV is found. The temperature-dependent DC characteristics of the TEBT are measured and studied. Consequentially, based on experimental results, the studied device provides the promise for low-power electronics applications.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134294054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Graded Ge fraction SiGe film was grown by using newly-designed SGE500 SiGe UHV/CVD system. The film quality was determined by X-ray diffraction. SiGe hetero-junction bipolar transistor (HBT) device with this SiGe film was made. Results showed that the quality of the graded SiGe film was high and the SiGe HBT device had good electrical performance.
{"title":"Growth of graded SiGe films by novel UHV/CVD system","authors":"Wentao Huang, Changchun Chen, Xiaoyi Xiong, Zhihong Liu, Wei Zhang, P. Tsien","doi":"10.1109/IWJT.2004.1306856","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306856","url":null,"abstract":"Graded Ge fraction SiGe film was grown by using newly-designed SGE500 SiGe UHV/CVD system. The film quality was determined by X-ray diffraction. SiGe hetero-junction bipolar transistor (HBT) device with this SiGe film was made. Results showed that the quality of the graded SiGe film was high and the SiGe HBT device had good electrical performance.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"232 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133051581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306797
S. Tan, W.T. Chen, M. Chu, W. Lour
This paper reports a new sub-0.5-/spl mu/m gate-length FET processing technique by using conventional i-line optical lithography. The key methodology is to thermally re-flow the patterned photo-resist upon two-step spin-coated SOG. According to this new process, the deposited gate metal has its final length and thickness be separately determined by taped resist profile and SOG thickness. The implemented gate length is as short as 0.41 /spl mu/m. Then it was successfully applied to fabrication of a newly designed hetero-doped-channel field-effect transistor with digital-graded In/sub x/Ga/sub 1-x/As multi-layer forming a HEMT-like channel. This digital-graded In/sub x/Ga/sub l-x/As channel by changing x values from 0.1 to 0.2 has most electrons be closer to gate metal. The measured sheet carrier density and mobility are 4.3 /spl times/ 10/sup 12/ cm/sup -2/ and 3560 cm/sup 2/V/sup -1/s/sup -1/ while the peak carrier concentration is larger than 1 /spl times/ 10/sup 19/ cm/sup -3/. A fabricated 0.41 /spl times/ 100 /spl mu/m/sup 2/ HDCFET exhibits the maximum transconductance of 370 mS/mm with an output current lager than 535 mA/mm and ft (f max) of 26 (32) GHz.
{"title":"An economic method for fabrication sub-quarter-/spl mu/m gate doped-channel FET's by photolithography","authors":"S. Tan, W.T. Chen, M. Chu, W. Lour","doi":"10.1109/IWJT.2004.1306797","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306797","url":null,"abstract":"This paper reports a new sub-0.5-/spl mu/m gate-length FET processing technique by using conventional i-line optical lithography. The key methodology is to thermally re-flow the patterned photo-resist upon two-step spin-coated SOG. According to this new process, the deposited gate metal has its final length and thickness be separately determined by taped resist profile and SOG thickness. The implemented gate length is as short as 0.41 /spl mu/m. Then it was successfully applied to fabrication of a newly designed hetero-doped-channel field-effect transistor with digital-graded In/sub x/Ga/sub 1-x/As multi-layer forming a HEMT-like channel. This digital-graded In/sub x/Ga/sub l-x/As channel by changing x values from 0.1 to 0.2 has most electrons be closer to gate metal. The measured sheet carrier density and mobility are 4.3 /spl times/ 10/sup 12/ cm/sup -2/ and 3560 cm/sup 2/V/sup -1/s/sup -1/ while the peak carrier concentration is larger than 1 /spl times/ 10/sup 19/ cm/sup -3/. A fabricated 0.41 /spl times/ 100 /spl mu/m/sup 2/ HDCFET exhibits the maximum transconductance of 370 mS/mm with an output current lager than 535 mA/mm and ft (f max) of 26 (32) GHz.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114531456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306870
Jin He, X. Xi, H. Wan, M. Chan, A. Niknejad, C. Hu
This paper outlines the advanced Surface-Potential-Plus (SPP) approach for the next generation CMOS device modeling. The main object of this approach is to develop a continuous, completely symmetric and accurate advanced charge-based MOS transistor model from the basic device physics including various physics effects. A unified exact inversion charge relation valid for uniform and retrograde doping cases is first obtained. Various small dimensional effects are elucidated and integrated concisely into this model. Comparison with measured data is finally presented to validate the new model. Importantly, it was also extended to UTB and double-gate MOSFETs.
{"title":"Surface-potential-plus approach for next generation CMOS device modeling","authors":"Jin He, X. Xi, H. Wan, M. Chan, A. Niknejad, C. Hu","doi":"10.1109/IWJT.2004.1306870","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306870","url":null,"abstract":"This paper outlines the advanced Surface-Potential-Plus (SPP) approach for the next generation CMOS device modeling. The main object of this approach is to develop a continuous, completely symmetric and accurate advanced charge-based MOS transistor model from the basic device physics including various physics effects. A unified exact inversion charge relation valid for uniform and retrograde doping cases is first obtained. Various small dimensional effects are elucidated and integrated concisely into this model. Comparison with measured data is finally presented to validate the new model. Importantly, it was also extended to UTB and double-gate MOSFETs.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122955152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306865
Xiaokang Shi, Min Yu, Jun Yin, Guoyan Zhang, Ru Huang, Xing Zhang
The paper addresses a precise and efficient analytical method of realistic dopant fluctuations in shallow junction formation. To reach the analytical method, millions of simulations are finished, and data of simulation results are analyzed. The analytical function of the method is without any additional fitting parameters and can be used to calculate the standard deviation and normalized standard deviation at different depths of the shallow junctions. And some simulation results of characteristics variation of devices are also shown in this paper.
{"title":"A precise and efficient analytical method of realistic dopant fluctuations in shallow junction formation","authors":"Xiaokang Shi, Min Yu, Jun Yin, Guoyan Zhang, Ru Huang, Xing Zhang","doi":"10.1109/IWJT.2004.1306865","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306865","url":null,"abstract":"The paper addresses a precise and efficient analytical method of realistic dopant fluctuations in shallow junction formation. To reach the analytical method, millions of simulations are finished, and data of simulation results are analyzed. The analytical function of the method is without any additional fitting parameters and can be used to calculate the standard deviation and normalized standard deviation at different depths of the shallow junctions. And some simulation results of characteristics variation of devices are also shown in this paper.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"418 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113967126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-15DOI: 10.1109/IWJT.2004.1306801
S. Tan, H.R. Chen, W.T. Chen, M. Chu, W. Lour
We have been successfully implemented for the InGaP/GaAs heterojunction bipolar transistors (HBTs) with the sulfur-treated GaAs base layer comparing with HBTs fabricated using emitter-edge thinning InGaP layer. As compared with non-passivated HBTs with an exposed extrinsic GaAs base, the improved base leakage current for InGaP-passivated HBTs is due to the inherent low surface recombination velocity associated with an InGaP layer. In views of the sulfur-passivated HBTs exhibited an enhanced current gain is attributed to the modification of the GaAs surface electronic properties. The maximum dc current gain available is 75 at low base current for sulfur-passivated HBTs. The sulfur-passivated devices also exhibit very good linearity in wide range of collector (10/sup -5/ to 10/sup -1/ A). Furthermore, detailed sulfur-treatment conditions and effects on device performance are investigated.
{"title":"Sulfur- and InGaP-passivated heterojunction bipolar transistors","authors":"S. Tan, H.R. Chen, W.T. Chen, M. Chu, W. Lour","doi":"10.1109/IWJT.2004.1306801","DOIUrl":"https://doi.org/10.1109/IWJT.2004.1306801","url":null,"abstract":"We have been successfully implemented for the InGaP/GaAs heterojunction bipolar transistors (HBTs) with the sulfur-treated GaAs base layer comparing with HBTs fabricated using emitter-edge thinning InGaP layer. As compared with non-passivated HBTs with an exposed extrinsic GaAs base, the improved base leakage current for InGaP-passivated HBTs is due to the inherent low surface recombination velocity associated with an InGaP layer. In views of the sulfur-passivated HBTs exhibited an enhanced current gain is attributed to the modification of the GaAs surface electronic properties. The maximum dc current gain available is 75 at low base current for sulfur-passivated HBTs. The sulfur-passivated devices also exhibit very good linearity in wide range of collector (10/sup -5/ to 10/sup -1/ A). Furthermore, detailed sulfur-treatment conditions and effects on device performance are investigated.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127099243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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