Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770499
M. Ghosh, A. Acharyya
The static, small-signal and noise characteristics of multiple quantum well (MQW) impact avalanche transit time (IMPATT) diodes operating at 94, 140, 220, 300 and 500 GHz frequencies have been investigated in this paper. The said MQW structures have been implemented by using Si~3C-SiC heterostructures. A self-consistent quantum drift-diffusion (SCQDD) model based simulation method has been used for the above mentioned studies. Simulation results show that Si~3C-SiC MQW IMPATT sources are highly proficient to provide considerably higher power output with significantly lower noise measure at aforementioned frequency bands as compared to conventional flat Si IMPATT sources.
{"title":"Multiple Quantum Well IMPATT Sources based on Si~3C-SiC Heterostructures Operating at Millimeter-Wave and Terahertz Frequency Bands","authors":"M. Ghosh, A. Acharyya","doi":"10.1109/EDKCON.2018.8770499","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770499","url":null,"abstract":"The static, small-signal and noise characteristics of multiple quantum well (MQW) impact avalanche transit time (IMPATT) diodes operating at 94, 140, 220, 300 and 500 GHz frequencies have been investigated in this paper. The said MQW structures have been implemented by using Si~3C-SiC heterostructures. A self-consistent quantum drift-diffusion (SCQDD) model based simulation method has been used for the above mentioned studies. Simulation results show that Si~3C-SiC MQW IMPATT sources are highly proficient to provide considerably higher power output with significantly lower noise measure at aforementioned frequency bands as compared to conventional flat Si IMPATT sources.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123549522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770435
Supratim Das
This paper proposes a novel work function engineered dual material gate Tunnel FET structure. The proposed device has similar structural configuration with that of a normal double gate (DG) TFET and therefore feasible in aspect of fabrication. The proposed device is run by 2D TCAD Sentaurus simulator and simulation results are analyzed. Based on simulation results, it is found that there is an improvement in drive current (1.37×102times)and subthreshold slope (~ 40 mV/decade) compared to normal DG TFET. The electrical performance of the proposed device is good by virtue of having dual material as gate electrode with different work function and composition percentage.
{"title":"Simulation based Performance Analysis of a Double Gate Work Function Engineered Doped Tunnel FET","authors":"Supratim Das","doi":"10.1109/EDKCON.2018.8770435","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770435","url":null,"abstract":"This paper proposes a novel work function engineered dual material gate Tunnel FET structure. The proposed device has similar structural configuration with that of a normal double gate (DG) TFET and therefore feasible in aspect of fabrication. The proposed device is run by 2D TCAD Sentaurus simulator and simulation results are analyzed. Based on simulation results, it is found that there is an improvement in drive current (1.37×102times)and subthreshold slope (~ 40 mV/decade) compared to normal DG TFET. The electrical performance of the proposed device is good by virtue of having dual material as gate electrode with different work function and composition percentage.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116886400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770475
Biswajit Baral, S. Biswal, P. Priya, Sarita Pani, S. Swain
In this work, a thorough inspection of DC, Analog, RF, Linearity and SCE's parameter analysis of Gate-Engineered TM-DG heterostructure MOSFET is carried out taking in to account the effect of changing the thickness of the barrier layer. The performance of the proposed device is investigated by evaluating some standard figure of merits (FOMs) like transconductance (gm), Output resistance (ROUT), Intrinsic Gain (gmRout), Transconductance Generation factor (gm/ID), gate capacitance, cutoff frequency(fT), maximum frequency of oscillation (fmax), Gain Bandwidth Product (GBW), VIP2, VIP3and 1 dB compression. All these FOMs are analyzed by varying the thickness of the barrier from 1 nm to 4 nm using TCAD simulation. The simulation results clarifies that performance of TM-DG heterostructure Metal field effect transistor (1:2:3) is affected as thickness of the barrier is scaled down.
{"title":"Impact of Variation in Barrier Thickness on a Gate-Engineered TM-DG Heterostructure MOSFET to Suppress SCE's and it's Analog, RF, Linearity Performance Investigation for SOC Applications","authors":"Biswajit Baral, S. Biswal, P. Priya, Sarita Pani, S. Swain","doi":"10.1109/EDKCON.2018.8770475","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770475","url":null,"abstract":"In this work, a thorough inspection of DC, Analog, RF, Linearity and SCE's parameter analysis of Gate-Engineered TM-DG heterostructure MOSFET is carried out taking in to account the effect of changing the thickness of the barrier layer. The performance of the proposed device is investigated by evaluating some standard figure of merits (FOMs) like transconductance (g<inf>m</inf>), Output resistance (R<inf>OUT</inf>), Intrinsic Gain (g<inf>m</inf>R<inf>out</inf>), Transconductance Generation factor (g<inf>m</inf>/I<inf>D</inf>), gate capacitance, cutoff frequency(f<inf>T</inf>), maximum frequency of oscillation (f<inf>max</inf>), Gain Bandwidth Product (GBW), VIP2, VIP<inf>3</inf>and 1 dB compression. All these FOMs are analyzed by varying the thickness of the barrier from 1 nm to 4 nm using TCAD simulation. The simulation results clarifies that performance of TM-DG heterostructure Metal field effect transistor (1:2:3) is affected as thickness of the barrier is scaled down.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124622636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770453
Merin Loukrakpam, C. L. Singh, Madhuchhanda Choudhury
In recent years, there has been a high demand for executing digital signal processing and machine learning applications on energy-constrained devices. Squaring is a vital arithmetic operation used in such applications. Hence, improving the energy efficiency of squaring is crucial. In this paper, a novel approximation method based on piecewise linear segmentation of the square function is proposed. An energy-efficient 32-bit approximate hardware for squaring was implemented using this method. The proposed hardware achieved a mean relative error of 0.43% and delivered up to 47% energy saving when compared with state-of-the-art approximate multipliers. The comparison also revealed that the proposed hardware is the most efficient design in terms of error-area-delay-power product.
{"title":"Energy-Efficient Approximate Squaring Hardware for Error-Resilient Digital Systems","authors":"Merin Loukrakpam, C. L. Singh, Madhuchhanda Choudhury","doi":"10.1109/EDKCON.2018.8770453","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770453","url":null,"abstract":"In recent years, there has been a high demand for executing digital signal processing and machine learning applications on energy-constrained devices. Squaring is a vital arithmetic operation used in such applications. Hence, improving the energy efficiency of squaring is crucial. In this paper, a novel approximation method based on piecewise linear segmentation of the square function is proposed. An energy-efficient 32-bit approximate hardware for squaring was implemented using this method. The proposed hardware achieved a mean relative error of 0.43% and delivered up to 47% energy saving when compared with state-of-the-art approximate multipliers. The comparison also revealed that the proposed hardware is the most efficient design in terms of error-area-delay-power product.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123881142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770425
Shankaranand Jha, S. K. Choudhary
Multi-gate (MG)metal-oxide semiconductor field-effect transistors (MOSFETs)are the preferred choice to overcome the limitations of scaling. In this paper, we have investigated the dependency of threshold voltage of Double-gate (DG), Tri-gate (TG) and Gate-All-Around (GAA) MOSFETs on various device parameters. Threshold voltage model of DG MOSFET has been extended to other gate architectures using geometrical transformations. The effort is to compare MG devices using simple and less time consuming mathematical calculations which reproduce the simulated/fabricated results with deviations within 5%.
{"title":"Impact of Device Parameters on the Threshold Voltage of Double-Gate, Tri-Gate and Gate-All-Around MOSFETs","authors":"Shankaranand Jha, S. K. Choudhary","doi":"10.1109/EDKCON.2018.8770425","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770425","url":null,"abstract":"Multi-gate (MG)metal-oxide semiconductor field-effect transistors (MOSFETs)are the preferred choice to overcome the limitations of scaling. In this paper, we have investigated the dependency of threshold voltage of Double-gate (DG), Tri-gate (TG) and Gate-All-Around (GAA) MOSFETs on various device parameters. Threshold voltage model of DG MOSFET has been extended to other gate architectures using geometrical transformations. The effort is to compare MG devices using simple and less time consuming mathematical calculations which reproduce the simulated/fabricated results with deviations within 5%.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123044485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770503
Ankit Dixit, N. Gupta
The main objective of this paper is to select the suitable gate dielectric material for the carbon nanotube field effect transistor (CNFET) using Technique for Order Preference by Similarity to Ideal Solution (TOPSIS). The selection of dielectric material is based on various material indices which include relative dielectric constant $(varepsilon_{mathrm{r}})$, conduction band offset (CBO), energy band gap $(mathrm{E}_{mathrm{g}})$ and coefficient of thermal expansion (CTE). Based on the analysis it was observed that $text{La}2mathrm{O}_{3}$ is the most suitable material followed by HfO2 and $mathrm{ZrO}_{2}$ for gate dielectric material in CNFET.
本文的主要目的是利用TOPSIS (Order Preference by Similarity to Ideal Solution)技术选择适合碳纳米管场效应晶体管(CNFET)的栅极介质材料。介质材料的选择是基于各种材料指标，包括相对介电常数$(varepsilon_{mathrm{r}})$、导带偏移(CBO)、能带隙$(mathrm{E}_{mathrm{g}})$和热膨胀系数(CTE)。通过分析发现，$text{La}2mathrm{O}_{3}$是CNFET栅极介质材料中最合适的材料，其次是HfO2和$mathrm{ZrO}_{2}$。
{"title":"Analysis of Different Gate Dielectric Materials in Carbon Nanotube Field Effect Transistor (CNFET) Using Optimization Technique","authors":"Ankit Dixit, N. Gupta","doi":"10.1109/EDKCON.2018.8770503","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770503","url":null,"abstract":"The main objective of this paper is to select the suitable gate dielectric material for the carbon nanotube field effect transistor (CNFET) using Technique for Order Preference by Similarity to Ideal Solution (TOPSIS). The selection of dielectric material is based on various material indices which include relative dielectric constant $(varepsilon_{mathrm{r}})$, conduction band offset (CBO), energy band gap $(mathrm{E}_{mathrm{g}})$ and coefficient of thermal expansion (CTE). Based on the analysis it was observed that $text{La}2mathrm{O}_{3}$ is the most suitable material followed by HfO2 and $mathrm{ZrO}_{2}$ for gate dielectric material in CNFET.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123466519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770450
Sujit Chatterjee, B. Tiru
For efficient data transfer, it is necessary that every component of a communication system be optimized. The same is the case for Visible Light Communication where the components are optoelectronic devices like the light emitting diodes, photodiodes, solar cells and the necessary transmitting and receiving electronics. In this paper, such a system is studied and optimized for efficient data transfer. The experimental arrangement for this is described in detail and the efficiency of the system in terms of distance, maximum bit rate and bit error rate are studied. The variability analyzed are different types of drivers used to drive the light emitting diode and photo detectors namely photodiode and solar cell. It is found that with this experimental arrangement, a 1W LED can be used to transfer data at a rate of more than 1 Mbps through a distance of 30 cm which, though decreases, maintains more than 0.7 Mbps at 475 cm using a photodiode. The maximum bit rate obtained in photodiode is 15.06 and 22.5 times that of a solar cell at a transceiver distance of 30 cm and 225 cm respectively. The distance of significant reception depends on the type of driver and photo detector used. An experimental arrangement is proposed that reduces flicker, both for low and high data rates. The results of the study can be used in future development of a successful system. The setup is also used for online monitoring of the ambient temperature and data transfer between PC's.
{"title":"Optimization of the Components of a Visible Light Communication System for Efficient Data Transfer","authors":"Sujit Chatterjee, B. Tiru","doi":"10.1109/EDKCON.2018.8770450","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770450","url":null,"abstract":"For efficient data transfer, it is necessary that every component of a communication system be optimized. The same is the case for Visible Light Communication where the components are optoelectronic devices like the light emitting diodes, photodiodes, solar cells and the necessary transmitting and receiving electronics. In this paper, such a system is studied and optimized for efficient data transfer. The experimental arrangement for this is described in detail and the efficiency of the system in terms of distance, maximum bit rate and bit error rate are studied. The variability analyzed are different types of drivers used to drive the light emitting diode and photo detectors namely photodiode and solar cell. It is found that with this experimental arrangement, a 1W LED can be used to transfer data at a rate of more than 1 Mbps through a distance of 30 cm which, though decreases, maintains more than 0.7 Mbps at 475 cm using a photodiode. The maximum bit rate obtained in photodiode is 15.06 and 22.5 times that of a solar cell at a transceiver distance of 30 cm and 225 cm respectively. The distance of significant reception depends on the type of driver and photo detector used. An experimental arrangement is proposed that reduces flicker, both for low and high data rates. The results of the study can be used in future development of a successful system. The setup is also used for online monitoring of the ambient temperature and data transfer between PC's.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127678274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770488
Samruddhi Chikhalikar, Omkar Khandekar, C. Bhattacharya
Micro-electro-mechanical systems (MEMS) devices such as accelerometers, gyroscopes have now become indispensable sensors for automobile usages as well as for guidance subsystems such as inertial navigational units, etc. for aerial moving platforms. This paper presents real-time filtering of noise in the acquired acceleration data by the MEMS devices such as ADXL345. The MEMS accelerometer sensor is fitted on a motorized platform for acquiring noisy acceleration data in the x-y coordinates by running the platform on uneven surfaces. The novelty in our approach is that we have used the same microcontroller that is mounted on the motorized platform for acquiring the acceleration data as well as for filtering the noisy data in real-time. The finite impulse response (FIR) filter used for removal of noise is designed using Filter Design & Analysis (FDA) tool in MATLAB. Results of filtering noisy data in the microcontroller are matched with the results obtained by offline filtering done in MATLAB environment.
{"title":"Design of Real-Time Acquisition and Filtering for MEMS-based Accelerometer Data in Microcontroller","authors":"Samruddhi Chikhalikar, Omkar Khandekar, C. Bhattacharya","doi":"10.1109/EDKCON.2018.8770488","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770488","url":null,"abstract":"Micro-electro-mechanical systems (MEMS) devices such as accelerometers, gyroscopes have now become indispensable sensors for automobile usages as well as for guidance subsystems such as inertial navigational units, etc. for aerial moving platforms. This paper presents real-time filtering of noise in the acquired acceleration data by the MEMS devices such as ADXL345. The MEMS accelerometer sensor is fitted on a motorized platform for acquiring noisy acceleration data in the x-y coordinates by running the platform on uneven surfaces. The novelty in our approach is that we have used the same microcontroller that is mounted on the motorized platform for acquiring the acceleration data as well as for filtering the noisy data in real-time. The finite impulse response (FIR) filter used for removal of noise is designed using Filter Design & Analysis (FDA) tool in MATLAB. Results of filtering noisy data in the microcontroller are matched with the results obtained by offline filtering done in MATLAB environment.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130181044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770504
Devanshi Gupta, N. Gupta
In this paper, distinct desirable and potential materials for the IR sensitive material of a microbolometer along with the material performance properties such as Temperature co-efficient of resistance (TCR), Responsivity, Detectivity, Time constant, Thermal conductance and mass are taken into consideration and Ashby's, VlseKriterijumska Optimizacija I Kompromisno Resenje in Serbian (VIKOR) and Technique for order preference by similarity to ideal solution (TOPSIS)approaches are applied to attain the most suitable IR sensitive material. The analysis results propose that atomic layer deposited (ALD) ZnO is the most advisable IR sensitive material for the better performance of the microbolometer.
本文考虑了微测热计红外敏感材料的不同理想材料和潜在材料，以及材料的性能，如电阻温度系数(TCR)、响应性、探测性、时间常数、热导率和质量。采用塞尔维亚语VlseKriterijumska Optimizacija I Kompromisno Resenje (VIKOR)和TOPSIS方法获得最合适的红外敏感材料。分析结果表明，原子层沉积(ALD) ZnO是最理想的红外敏感材料，具有更好的微热计性能。
{"title":"Investigations on Infrared(IR) Sensitive Material for Microbolometer Using Material Selection Approaches","authors":"Devanshi Gupta, N. Gupta","doi":"10.1109/EDKCON.2018.8770504","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770504","url":null,"abstract":"In this paper, distinct desirable and potential materials for the IR sensitive material of a microbolometer along with the material performance properties such as Temperature co-efficient of resistance (TCR), Responsivity, Detectivity, Time constant, Thermal conductance and mass are taken into consideration and Ashby's, VlseKriterijumska Optimizacija I Kompromisno Resenje in Serbian (VIKOR) and Technique for order preference by similarity to ideal solution (TOPSIS)approaches are applied to attain the most suitable IR sensitive material. The analysis results propose that atomic layer deposited (ALD) ZnO is the most advisable IR sensitive material for the better performance of the microbolometer.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127821008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/EDKCON.2018.8770463
Aniruddha Ghosh, A. Sinha
Digital signal processing (DSP) based applications are designed using various types of DSP algorithms which are computationally intensive. So, DSP-based applications widely utilize Multiply-Accumulate (MA C) operation for accomplishing speed. In contrast with the binary number system, Residue Number Systems (RNS) is considered to be more prominent because of their abilities of carrying out carry-free arithmetic operations like addition, subtraction. Ternary value logic (TVL) offers several advantages like reduced chip area as well as overall delay, over conventional binary number system. Designing superior adder and multiplier have become the major concern for implementing high performance signal processing applications. To improve the performance of MA C unit, a new architecture is proposed in this paper. In this paper, MA C unit is implemented using ternary multiplier and RNS adder in TVL domain. The major bottleneck of TVL to RNS conversion and vice versa has introduced huge complexity which leads to decreased efficiency of performance due to large conversion time. The performance of RNS based system can be enhanced by choosing relative prime moduli set as improper selection of moduli will affect system speed, dynamic range and hardware complexity. Proposed MAC unit is mapped on field programmable gate array (FPGA) for analysis its performance.
{"title":"FPGA Implementation of RNS Adder Based MAC Unit in Ternary Value Logic Domain for Signal Processing Algorithm and its Performance Analysis","authors":"Aniruddha Ghosh, A. Sinha","doi":"10.1109/EDKCON.2018.8770463","DOIUrl":"https://doi.org/10.1109/EDKCON.2018.8770463","url":null,"abstract":"Digital signal processing (DSP) based applications are designed using various types of DSP algorithms which are computationally intensive. So, DSP-based applications widely utilize Multiply-Accumulate (MA C) operation for accomplishing speed. In contrast with the binary number system, Residue Number Systems (RNS) is considered to be more prominent because of their abilities of carrying out carry-free arithmetic operations like addition, subtraction. Ternary value logic (TVL) offers several advantages like reduced chip area as well as overall delay, over conventional binary number system. Designing superior adder and multiplier have become the major concern for implementing high performance signal processing applications. To improve the performance of MA C unit, a new architecture is proposed in this paper. In this paper, MA C unit is implemented using ternary multiplier and RNS adder in TVL domain. The major bottleneck of TVL to RNS conversion and vice versa has introduced huge complexity which leads to decreased efficiency of performance due to large conversion time. The performance of RNS based system can be enhanced by choosing relative prime moduli set as improper selection of moduli will affect system speed, dynamic range and hardware complexity. Proposed MAC unit is mapped on field programmable gate array (FPGA) for analysis its performance.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116680348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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