Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269281
Soon-Moon Jung, H. Lim, W. Cho, Hoosung Cho, H. Hong, Jaehun Jeong, Sugwoo Jung, H. Park, Byoungkeun Son, Y. Jang, Kinam Kim
The smallest SRAM cell, 0.46 um/sup 2/, is realized by a single pitch cell layout, gate poly trim mask technique, 80 nm contact holes formed by polymer attaching process, and a 193 nm ArF lithography process. The MIM (metal-insulator-metal) node capacitor is developed and used for the first time in the SRAM cell to reduce the radiation induced soft error rate, dramatically. The high performance transistors are developed with a channel length of 70 nm, plasma nitrided 13 /spl Aring/ gate oxide, low thermal budget sidewall spacer, and CoSix.
{"title":"Soft error immune 0.46 /spl mu/m/sup 2/ SRAM cell with MIM node capacitor by 65 nm CMOS technology for ultra high speed SRAM","authors":"Soon-Moon Jung, H. Lim, W. Cho, Hoosung Cho, H. Hong, Jaehun Jeong, Sugwoo Jung, H. Park, Byoungkeun Son, Y. Jang, Kinam Kim","doi":"10.1109/IEDM.2003.1269281","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269281","url":null,"abstract":"The smallest SRAM cell, 0.46 um/sup 2/, is realized by a single pitch cell layout, gate poly trim mask technique, 80 nm contact holes formed by polymer attaching process, and a 193 nm ArF lithography process. The MIM (metal-insulator-metal) node capacitor is developed and used for the first time in the SRAM cell to reduce the radiation induced soft error rate, dramatically. The high performance transistors are developed with a channel length of 70 nm, plasma nitrided 13 /spl Aring/ gate oxide, low thermal budget sidewall spacer, and CoSix.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131797028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269187
S. Kondo, B. Yoon, S. Tokitoh, K. Misawa, S. Sone, H.J. Shin, N. Ohashi, N. Kobayashi
Toward the 45 nm technology node, multilevel Cu dual-damascene interconnects with hybrid-structure low-k ILDs (inter-line dielectrics) consisting of porous MSQ (methyl silsesquioxane) (k<1.6-1.8) and organic polymer films are successfully integrated on 300 mm wafers for the first time with a low-pressure CMP and dummy pattern technology, which supports the poor mechanical properties of ultra low-k films.
{"title":"Low-pressure CMP for 300-mm ultra low-k (k=1.6-1.8)/Cu integration","authors":"S. Kondo, B. Yoon, S. Tokitoh, K. Misawa, S. Sone, H.J. Shin, N. Ohashi, N. Kobayashi","doi":"10.1109/IEDM.2003.1269187","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269187","url":null,"abstract":"Toward the 45 nm technology node, multilevel Cu dual-damascene interconnects with hybrid-structure low-k ILDs (inter-line dielectrics) consisting of porous MSQ (methyl silsesquioxane) (k<1.6-1.8) and organic polymer films are successfully integrated on 300 mm wafers for the first time with a low-pressure CMP and dummy pattern technology, which supports the poor mechanical properties of ultra low-k films.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134642220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269241
J. B. Lee, Vivek Subramanian
For the first time, we demonstrate flexible transistors formed directly on fibers. This represents a significant step towards the realization of electronics textiles. Fiber transistors exhibit mobilities of >10/sup -2/ cm/sup 2//V-s measured at 20 V V/sub DD/. The entire transistor is fabricated without resorting to conventional lithography techniques. Patterning is achieved via shadowing from overwoven fibers. The process is compatible with textile manufacturing, and is therefore a promising technology for scalable e-textile fabrication.
{"title":"Organic transistors on fiber: a first step towards electronic textiles","authors":"J. B. Lee, Vivek Subramanian","doi":"10.1109/IEDM.2003.1269241","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269241","url":null,"abstract":"For the first time, we demonstrate flexible transistors formed directly on fibers. This represents a significant step towards the realization of electronics textiles. Fiber transistors exhibit mobilities of >10/sup -2/ cm/sup 2//V-s measured at 20 V V/sub DD/. The entire transistor is fabricated without resorting to conventional lithography techniques. Patterning is achieved via shadowing from overwoven fibers. The process is compatible with textile manufacturing, and is therefore a promising technology for scalable e-textile fabrication.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133502226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269346
R. Quay, A. Tessmann, R. Kiefer, R. Weber, F. van Raay, M. Kuri, M. Riessle, H. Massler, S. Muller, M. Schlechtweg, G. Weimann
The operation of AlGaN/GaN HEMTs on SiC substrate at V-band frequencies (50-75 GHz) is discussed. Both common source and dual-gate AlGaN/GaN HEMTs on SiC substrate are optimized and investigated by active and passive load-pull measurements. At 60 GHz, a power density of /spl ges/0.5 W/mm can be measured for a small common source AlGaN/GaN HEMT limited so far by the available input power of the newly developed load-pull system. A common source HEMT with W/sub g/=0.18 mm yields a power density of 1.9 W/mm at 40 GHz and a linear power gain of /spl ges/5 dB at 60 GHz, while several dual-gate AlGaN/GaN HEMTs of W/sub g/=0.18 mm and 0.36 mm yield MSG/MAG values /spl ges/12 dB at 60 GHz.
{"title":"AlGaN/GaN HEMTs on SiC: towards power operation at V-band","authors":"R. Quay, A. Tessmann, R. Kiefer, R. Weber, F. van Raay, M. Kuri, M. Riessle, H. Massler, S. Muller, M. Schlechtweg, G. Weimann","doi":"10.1109/IEDM.2003.1269346","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269346","url":null,"abstract":"The operation of AlGaN/GaN HEMTs on SiC substrate at V-band frequencies (50-75 GHz) is discussed. Both common source and dual-gate AlGaN/GaN HEMTs on SiC substrate are optimized and investigated by active and passive load-pull measurements. At 60 GHz, a power density of /spl ges/0.5 W/mm can be measured for a small common source AlGaN/GaN HEMT limited so far by the available input power of the newly developed load-pull system. A common source HEMT with W/sub g/=0.18 mm yields a power density of 1.9 W/mm at 40 GHz and a linear power gain of /spl ges/5 dB at 60 GHz, while several dual-gate AlGaN/GaN HEMTs of W/sub g/=0.18 mm and 0.36 mm yield MSG/MAG values /spl ges/12 dB at 60 GHz.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"310 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129363778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269290
Jae-Hoon Lee, You-Seok Suh, H. Lazar, R. Jha, J. Gurganus, Yanxia Lin, V. Misra
Dual metal electrodes such as Ru, Ru-Ta alloy, TaN and TaSiN were investigated on low EOT single layer HfO/sub 2/ and stacked HfO/sub 2//SiO/sub 2/ gate dielectrics. It was found that the work function values of metal gates on HfO/sub 2/ and on SiO/sub 2/ are similar. Thermal anneal studies of selected metals on the above dielectrics were also performed to evaluate the change in EOT and V/sub FB/ values.
{"title":"Compatibility of dual metal gate electrodes with high-k dielectrics for CMOS","authors":"Jae-Hoon Lee, You-Seok Suh, H. Lazar, R. Jha, J. Gurganus, Yanxia Lin, V. Misra","doi":"10.1109/IEDM.2003.1269290","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269290","url":null,"abstract":"Dual metal electrodes such as Ru, Ru-Ta alloy, TaN and TaSiN were investigated on low EOT single layer HfO/sub 2/ and stacked HfO/sub 2//SiO/sub 2/ gate dielectrics. It was found that the work function values of metal gates on HfO/sub 2/ and on SiO/sub 2/ are similar. Thermal anneal studies of selected metals on the above dielectrics were also performed to evaluate the change in EOT and V/sub FB/ values.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126947712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269260
P. Solomon, D. Frank, J. Jopling, C. D'Emic, O. Dokumaci, P. Ronsheim, W. Haensch
Band-to-band tunneling was studied experimentally in ion-implanted PN junction diodes with profiles representative of present and future silicon CMOS transistors. Measurements were done over a wide range of temperatures and implant parameters. Profile parameters were derived from analysis of CV characteristics, and compared to SIMS analysis. When tunneling current was plotted against distance (tunneling distance, corrected for band curvature) a quasi-universal exponential reduction of tunneling current vs. tunneling distance was found with an attenuation length of 0.38 nm, and an extrapolated tunneling current at zero tunnel distance of 5.3/spl times/10/sup 7/ A/cm/sup 2/ at 300 K. These results were used to estimate drain-substrate currents in future scaled CMOS, and it was concluded that it will be challenging to make the ITRS 2002 roadmap projections on leakage current for the low operating power and low standby power options without more innovation and device design changes.
对离子注入PN结二极管的带间隧道效应进行了实验研究，该二极管具有代表当前和未来硅CMOS晶体管的轮廓。测量是在很宽的温度和植入物参数范围内完成的。从CV特征分析中得出剖面参数，并与SIMS分析进行比较。当隧道电流与隧道距离(隧道距离，修正了带曲率)的关系时，发现隧道电流随隧道距离的准普遍指数减少，衰减长度为0.38 nm，并且在300 K时，零隧道距离时的外推隧道电流为5.3/spl乘以/10/sup 7/ a /cm/sup 2/。这些结果被用于估计未来规模CMOS的漏极-衬底电流，并得出结论，如果没有更多的创新和器件设计变化，要对低工作功率和低待机功率选项进行ITRS 2002路线图预测将是具有挑战性的。
{"title":"Tunnel current measurements on P/N junction diodes and implications for future device design","authors":"P. Solomon, D. Frank, J. Jopling, C. D'Emic, O. Dokumaci, P. Ronsheim, W. Haensch","doi":"10.1109/IEDM.2003.1269260","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269260","url":null,"abstract":"Band-to-band tunneling was studied experimentally in ion-implanted PN junction diodes with profiles representative of present and future silicon CMOS transistors. Measurements were done over a wide range of temperatures and implant parameters. Profile parameters were derived from analysis of CV characteristics, and compared to SIMS analysis. When tunneling current was plotted against distance (tunneling distance, corrected for band curvature) a quasi-universal exponential reduction of tunneling current vs. tunneling distance was found with an attenuation length of 0.38 nm, and an extrapolated tunneling current at zero tunnel distance of 5.3/spl times/10/sup 7/ A/cm/sup 2/ at 300 K. These results were used to estimate drain-substrate currents in future scaled CMOS, and it was concluded that it will be challenging to make the ITRS 2002 roadmap projections on leakage current for the low operating power and low standby power options without more innovation and device design changes.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116417436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269199
F. Driussi, F. Widdershoven, D. Esseni, M. van Duuren
This work presents a new model to describe the statistical properties of SILC in non-volatile memory (NVM) arrays and a procedure to extract the average number of oxide traps and the probability density of the gate leakage current induced by a single trap directly from the measured histogram of SILC. The model and the extraction procedure have been validated on SILC distributions with known parameters, generated by Monte Carlo simulations, and applied to measurements performed on FLASH memory arrays. The sensitivity of the extracted parameters on the measurement resolution is discussed in detail.
{"title":"A new statistical model to extract the stress induced oxide trap number and the probability density distribution of the gate current produced by a single trap","authors":"F. Driussi, F. Widdershoven, D. Esseni, M. van Duuren","doi":"10.1109/IEDM.2003.1269199","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269199","url":null,"abstract":"This work presents a new model to describe the statistical properties of SILC in non-volatile memory (NVM) arrays and a procedure to extract the average number of oxide traps and the probability density of the gate leakage current induced by a single trap directly from the measured histogram of SILC. The model and the extraction procedure have been validated on SILC distributions with known parameters, generated by Monte Carlo simulations, and applied to measurements performed on FLASH memory arrays. The sensitivity of the extracted parameters on the measurement resolution is discussed in detail.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123498840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269159
C. Oh, M. Oh, Hee-Sung Kang, Chang-hyun Park, B.J. Oh, Yoon-hae Kim, H. Rhee, Y. W. Kim, K. Suh
Double raised source/drain (DR) ultra thin film (UTF) SOI CMOSFETs were experimented for the first time. Double Si selective epitaxial growth (SEG) process before source/drain extension and deep source/drain implant is greatly recommended for excellent device performance with a reduced series resistance. Fully depleted (FD) SOI devices with 50 nm gate length for embedded SRAM technology were investigated for different SOI film thickness. Transistor performances of 700 /spl mu/A//spl mu/m and 355 /spl mu/A//spl mu/m at 1.0 V operation and Ioff = 90 nA//spl mu/m was obtained for NMOS and PMOS devices, respectively. Drain induced barrier lowering (DIBL) was improved as the SOI film thickness was scaled down to 17 nm from 50 nm. The static noise margin (SNM) for a 1.1 /spl mu/m/sup 2/ SRAM cell was 210 mV and ring oscillator speed was improved by 24% compared to bulk devices.
{"title":"Double raised source/drain transistor with 50 nm gate length on 17 nm UTF-SOI for 1.1 /spl mu/m/sup 2/ embedded SRAM technology","authors":"C. Oh, M. Oh, Hee-Sung Kang, Chang-hyun Park, B.J. Oh, Yoon-hae Kim, H. Rhee, Y. W. Kim, K. Suh","doi":"10.1109/IEDM.2003.1269159","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269159","url":null,"abstract":"Double raised source/drain (DR) ultra thin film (UTF) SOI CMOSFETs were experimented for the first time. Double Si selective epitaxial growth (SEG) process before source/drain extension and deep source/drain implant is greatly recommended for excellent device performance with a reduced series resistance. Fully depleted (FD) SOI devices with 50 nm gate length for embedded SRAM technology were investigated for different SOI film thickness. Transistor performances of 700 /spl mu/A//spl mu/m and 355 /spl mu/A//spl mu/m at 1.0 V operation and Ioff = 90 nA//spl mu/m was obtained for NMOS and PMOS devices, respectively. Drain induced barrier lowering (DIBL) was improved as the SOI film thickness was scaled down to 17 nm from 50 nm. The static noise margin (SNM) for a 1.1 /spl mu/m/sup 2/ SRAM cell was 210 mV and ring oscillator speed was improved by 24% compared to bulk devices.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122292216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269292
L. Selmi, D. Esseni, P. Palestri
This paper reviews some important degradation mechanisms in MOS devices. In particular, we describe how the transition toward non-local, ballistic transport in ultrashort channels and ultra-thin oxides, which is increasingly relevant in modern devices, has made carrier energy emerge as the driving force of apparently different degradation mechanisms in the fields of hot carrier, oxide wearout and BTI (bias-temperature instability) limited reliability. The role of transport simulations in support of a better understanding of microscopic degradation mechanisms is addressed.
{"title":"Towards microscopic understanding of MOSFET reliability: the role of carrier energy and transport simulations","authors":"L. Selmi, D. Esseni, P. Palestri","doi":"10.1109/IEDM.2003.1269292","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269292","url":null,"abstract":"This paper reviews some important degradation mechanisms in MOS devices. In particular, we describe how the transition toward non-local, ballistic transport in ultrashort channels and ultra-thin oxides, which is increasingly relevant in modern devices, has made carrier energy emerge as the driving force of apparently different degradation mechanisms in the fields of hot carrier, oxide wearout and BTI (bias-temperature instability) limited reliability. The role of transport simulations in support of a better understanding of microscopic degradation mechanisms is addressed.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124938879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269355
Peiqi Xuan, Min She, B. Harteneck, A. Liddle, J. Bokor, T. King
FD-SOI (fully depleted silicon-on-insulator) FinFET SONOS flash memory devices are investigated for the first time, and they are found to be scalable to a gate length of 40 nm. Although the FinFET SONOS device does not have a body contact, excellent program/erase characteristics are achieved, together with high endurance, long retention time and low reading disturbance. Devices fabricated on [100] and [110] silicon surfaces are compared.
{"title":"FinFET SONOS flash memory for embedded applications","authors":"Peiqi Xuan, Min She, B. Harteneck, A. Liddle, J. Bokor, T. King","doi":"10.1109/IEDM.2003.1269355","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269355","url":null,"abstract":"FD-SOI (fully depleted silicon-on-insulator) FinFET SONOS flash memory devices are investigated for the first time, and they are found to be scalable to a gate length of 40 nm. Although the FinFET SONOS device does not have a body contact, excellent program/erase characteristics are achieved, together with high endurance, long retention time and low reading disturbance. Devices fabricated on [100] and [110] silicon surfaces are compared.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130101943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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