Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269336
P. Hazucha, T. Karnik, J. Maiz, S. Walstra, B. Bloechel, J. Tschanz, G. Dermer, S. Hareland, P. Armstrong, S. Borkar
The neutron soft error rate (SER) dependency on voltage and area was measured for a state-of-the-art 90-nm CMOS technology. The SER increased by 18% for a 10% reduction in voltage, and scaled linearly with diode area. The measured SER per bit of SRAMs in 0.25 /spl mu/m, 0.18 /spl mu/m, 0.13 /spl mu/m, and 90 nm showed an increase of 8% per generation.
{"title":"Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation","authors":"P. Hazucha, T. Karnik, J. Maiz, S. Walstra, B. Bloechel, J. Tschanz, G. Dermer, S. Hareland, P. Armstrong, S. Borkar","doi":"10.1109/IEDM.2003.1269336","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269336","url":null,"abstract":"The neutron soft error rate (SER) dependency on voltage and area was measured for a state-of-the-art 90-nm CMOS technology. The SER increased by 18% for a 10% reduction in voltage, and scaled linearly with diode area. The measured SER per bit of SRAMs in 0.25 /spl mu/m, 0.18 /spl mu/m, 0.13 /spl mu/m, and 90 nm showed an increase of 8% per generation.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121525822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269257
R. Gusmeroli, A. Spinelli, A. Pirovano, A. Lacaita, F. Boeuf, T. Skotnicki
Two-dimensional quantum-mechanical (2D QM) simulations of non-overlapped MOS devices are presented, validated through comparison against experimental data. It is shown that 2D QM simulations are needed to accurately predict the experiments and can thus be used to explore the design trade-offs and optimize the performance. Simulations show that nonoverlapped MOS structures can provide an improvement in switching time up to about 50% with respect to conventional approaches.
{"title":"2D QM simulation and optimization of decanano non-overlapped MOS devices","authors":"R. Gusmeroli, A. Spinelli, A. Pirovano, A. Lacaita, F. Boeuf, T. Skotnicki","doi":"10.1109/IEDM.2003.1269257","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269257","url":null,"abstract":"Two-dimensional quantum-mechanical (2D QM) simulations of non-overlapped MOS devices are presented, validated through comparison against experimental data. It is shown that 2D QM simulations are needed to accurately predict the experiments and can thus be used to explore the design trade-offs and optimize the performance. Simulations show that nonoverlapped MOS structures can provide an improvement in switching time up to about 50% with respect to conventional approaches.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122054633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269327
H. Fukutome, Y. Momiyama, H. Nakao, T. Aoyama, H. Arimoto
We conclude that fluorine implantation in the extension region (F-tub) makes the Vth roll-off characteristic dramatically improve without degrading the drive current. Using scanning tunneling microscopy (STM) for two-dimensional (2D) carrier profiling, we directly confirmed that such an improvement of the device performance was induced by the reduction of the overlap length and the steep lateral abruptness on the nanometer scale.
{"title":"Fluorine implantation impact in extension region on the electrical performance of sub-50nm P-MOSFETs","authors":"H. Fukutome, Y. Momiyama, H. Nakao, T. Aoyama, H. Arimoto","doi":"10.1109/IEDM.2003.1269327","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269327","url":null,"abstract":"We conclude that fluorine implantation in the extension region (F-tub) makes the Vth roll-off characteristic dramatically improve without degrading the drive current. Using scanning tunneling microscopy (STM) for two-dimensional (2D) carrier profiling, we directly confirmed that such an improvement of the device performance was induced by the reduction of the overlap length and the steep lateral abruptness on the nanometer scale.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116589814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269339
S. Gowda, G. Mathur, Qihang Li, S. Surthi, Q. Zhao, J. Lindsey, K. Mobley, D. F. Bocian, V. Misra
The properties of silicon in hybrid CMOS/molecular capacitors were successfully engineered to produce multiple bit and long retention-time devices. Charge storage molecules were attached to silicon substrates to produce multiple bit and long retention time characteristics that may be attractive for nanoscale high density memory applications.
{"title":"Hybrid silicon/molecular memories: co-engineering for novel functionality","authors":"S. Gowda, G. Mathur, Qihang Li, S. Surthi, Q. Zhao, J. Lindsey, K. Mobley, D. F. Bocian, V. Misra","doi":"10.1109/IEDM.2003.1269339","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269339","url":null,"abstract":"The properties of silicon in hybrid CMOS/molecular capacitors were successfully engineered to produce multiple bit and long retention-time devices. Charge storage molecules were attached to silicon substrates to produce multiple bit and long retention time characteristics that may be attractive for nanoscale high density memory applications.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"5 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132452985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269296
A. Krishnan, V. Reddy, S. Chakravarthi, J. Rodriguez, S. John, S. Krishnan
We describe a quantitative relationship between I/sub D/ and V/sub T/ driven NBTI specifications. Mobility degradation is shown to be a significant (/spl sim/40%) contributor to I/sub D/ degradation. We report for the first time, degradation in gate-drain capacitance (C/sub GD/) due to NBTI. The impact of this C/sub GD/ degradation on circuit performance is quantified for both digital and analog circuits. We find that C/sub GD/ degradation has a greater impact on the analog circuit studied than the digital circuit. We demonstrate that there is an optimum operating voltage that balances NBTI degradation against transistor voltage headroom. Further, a numerical model based on the reaction-diffusion theory has been developed, which is found to satisfactorily describe degradation, recovery and post-recovery response to stress.
{"title":"NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs]","authors":"A. Krishnan, V. Reddy, S. Chakravarthi, J. Rodriguez, S. John, S. Krishnan","doi":"10.1109/IEDM.2003.1269296","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269296","url":null,"abstract":"We describe a quantitative relationship between I/sub D/ and V/sub T/ driven NBTI specifications. Mobility degradation is shown to be a significant (/spl sim/40%) contributor to I/sub D/ degradation. We report for the first time, degradation in gate-drain capacitance (C/sub GD/) due to NBTI. The impact of this C/sub GD/ degradation on circuit performance is quantified for both digital and analog circuits. We find that C/sub GD/ degradation has a greater impact on the analog circuit studied than the digital circuit. We demonstrate that there is an optimum operating voltage that balances NBTI degradation against transistor voltage headroom. Further, a numerical model based on the reaction-diffusion theory has been developed, which is found to satisfactorily describe degradation, recovery and post-recovery response to stress.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134512091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269403
T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, T. Maeda, S. Takagi
In this paper, in order to evaluate the higher hole mobility of the [110]-surface devices against that of the [100]-surface MOSFETs, we have studied the [110]-surface hole mobility behaviors of thin film (TF) strained-SOI, unstrained-SOI, and unstrained-bulk MOSFETs in detail, as functions of E/sub eff/, current flow direction, and temperature. We have introduced a model for [110]-surface hole mobility. We discuss the V/sub th/ control of the strained-SOIs by applying the back-gate bias under the buried oxide without controlling the channel dopant, as well as the transconductance enhancement down to the quarter-micron region. A device design concept for strained-CMOS is proposed to optimize the channel surface orientation and the drain current flow direction of n- and p-MOSFETs.
{"title":"Physical mechanism for high hole mobility in [110]-surface strained- and unstrained-MOSFETs","authors":"T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, T. Maeda, S. Takagi","doi":"10.1109/IEDM.2003.1269403","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269403","url":null,"abstract":"In this paper, in order to evaluate the higher hole mobility of the [110]-surface devices against that of the [100]-surface MOSFETs, we have studied the [110]-surface hole mobility behaviors of thin film (TF) strained-SOI, unstrained-SOI, and unstrained-bulk MOSFETs in detail, as functions of E/sub eff/, current flow direction, and temperature. We have introduced a model for [110]-surface hole mobility. We discuss the V/sub th/ control of the strained-SOIs by applying the back-gate bias under the buried oxide without controlling the channel dopant, as well as the transconductance enhancement down to the quarter-micron region. A device design concept for strained-CMOS is proposed to optimize the channel surface orientation and the drain current flow direction of n- and p-MOSFETs.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115147374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269407
J. Park, W. Jeong, J. Oh, H.C. Koo, G. Koh, G. Jeong, H. Jeong, Y.J. Jeong, S.L. Cho, J. Lee, H.J. Kim, K. Kim
A novel 8F/sup 2/ cell structure for high density magnetic random access memory (MRAM) and its operating characteristics are proposed. In this new scheme, we formed bottom electrode contact (BEC) through twin metal lines (MLs) and a magnetic tunnel junction (MTJ) was located just on the BEC for the reduction of cell size. From the results of simulation and experiment, we have confirmed that the generated magnetic field in the new scheme is more uniform than that in the conventional scheme with a negligible reduction of writing field strength. We adopted a self-aligned BEC process to prevent electrical shorting between ML and BEC. To avoid electrical shorting and improve the magnetic properties of MTJs, a chemical mechanical polishing (CMP) process was adopted before MTJ deposition. As a result, we confirmed the feasibility of high-density 1T1MTJ MRAM, composed of 8F/sup 2/ cells with optimal MTJ characteristics.
{"title":"An 8F/sup 2/ MRAM technology using modified metal lines","authors":"J. Park, W. Jeong, J. Oh, H.C. Koo, G. Koh, G. Jeong, H. Jeong, Y.J. Jeong, S.L. Cho, J. Lee, H.J. Kim, K. Kim","doi":"10.1109/IEDM.2003.1269407","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269407","url":null,"abstract":"A novel 8F/sup 2/ cell structure for high density magnetic random access memory (MRAM) and its operating characteristics are proposed. In this new scheme, we formed bottom electrode contact (BEC) through twin metal lines (MLs) and a magnetic tunnel junction (MTJ) was located just on the BEC for the reduction of cell size. From the results of simulation and experiment, we have confirmed that the generated magnetic field in the new scheme is more uniform than that in the conventional scheme with a negligible reduction of writing field strength. We adopted a self-aligned BEC process to prevent electrical shorting between ML and BEC. To avoid electrical shorting and improve the magnetic properties of MTJs, a chemical mechanical polishing (CMP) process was adopted before MTJ deposition. As a result, we confirmed the feasibility of high-density 1T1MTJ MRAM, composed of 8F/sup 2/ cells with optimal MTJ characteristics.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114284560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269410
P. Moon, V. Dubin, S. Johnston, J. Leu, K. Raol, C. Wu
Copper interconnects require two types of barrier layers: a liner on the sides and bottoms of the damascene features and a cap on top of the damascene features. The key functions of the barrier layers are to prevent copper and oxygen diffusion and promote adhesion with both the interlayer dielectric (ILD) and the copper. The cap layer must also protect the copper from corrosion during subsequent patterning steps and act as an etchstop for partially landed vias. Most copper damascene processes use a PVD Ta and/or Ta(N) alloy liner and PECVD SiN or SiCN dielectric cap. However, as copper interconnects continue to scale to finer dimensions these metal barrier technologies become problematic due to wiring resistance and current density issues. This paper describes some of the alternative liner and cap technologies that are being developed to address these issues.
{"title":"Process roadmap and challenges for metal barriers [copper interconnects]","authors":"P. Moon, V. Dubin, S. Johnston, J. Leu, K. Raol, C. Wu","doi":"10.1109/IEDM.2003.1269410","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269410","url":null,"abstract":"Copper interconnects require two types of barrier layers: a liner on the sides and bottoms of the damascene features and a cap on top of the damascene features. The key functions of the barrier layers are to prevent copper and oxygen diffusion and promote adhesion with both the interlayer dielectric (ILD) and the copper. The cap layer must also protect the copper from corrosion during subsequent patterning steps and act as an etchstop for partially landed vias. Most copper damascene processes use a PVD Ta and/or Ta(N) alloy liner and PECVD SiN or SiCN dielectric cap. However, as copper interconnects continue to scale to finer dimensions these metal barrier technologies become problematic due to wiring resistance and current density issues. This paper describes some of the alternative liner and cap technologies that are being developed to address these issues.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114285397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269275
S. Ahn, G. Koh, K. Kwon, S. Baik, G. Jung, Y. Hwang, H. Jeong, Kinam Kim
The technological challenges associated with STTM (scalable two transistor memory) cells were reviewed. First of all, the basic operating principles of the memory cell are discussed. This is followed by the introduction of the memory array formation and co-process of the I/O transistor, applying a 0.24 /spl mu/m design rule test vehicle. A new cell structure of a surrounded gate STTM structure is introduced. In addition, the process technology and the performance of the memory cell are presented.
{"title":"Highly scalable and CMOS-compatible STTM cell technology","authors":"S. Ahn, G. Koh, K. Kwon, S. Baik, G. Jung, Y. Hwang, H. Jeong, Kinam Kim","doi":"10.1109/IEDM.2003.1269275","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269275","url":null,"abstract":"The technological challenges associated with STTM (scalable two transistor memory) cells were reviewed. First of all, the basic operating principles of the memory cell are discussed. This is followed by the introduction of the memory array formation and co-process of the I/O transistor, applying a 0.24 /spl mu/m design rule test vehicle. A new cell structure of a surrounded gate STTM structure is introduced. In addition, the process technology and the performance of the memory cell are presented.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116168612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269411
M. Tada, Y. Harada, T. Tamura, N. Inoue, F. Ito, M. Yoshiki, H. Ohtake, M. Narihiro, M. Tagami, M. Ueki, K. Hijioka, M. Abe, T. Takeuchi, S. Saito, T. Onodera, N. Furutake, K. Arai, K. Fujii, Y. Hayashi
A highly reliable, 65 nm-node Cu interconnect technology has been developed with 180 nm/200 nm-pitched lines connected through /spl phi/100 nm-vias. A porous SiOCH film (k=2.5) with sub-nanometer pores is introduced for the inter-metal dielectrics (IMD) on a non-porous, rigid SiOCH film (k=2.9) for the via-infra-line dielectrics (via-ILD). A key breakthrough is a special pore-seal technique, in which the trench-etched surface of the porous SiOCH is covered with an ultra-thin, low-k organic silica film (k=2.7), thus improving the line-to-line TDDB (time dependent dielectric breakdown) reliability of the narrow-pitched Cu lines. The fully-scaled-down, 65 nm-node Cu interconnects with the porous-on-rigid SiOCH hybrid structure achieve excellent performance and reliability.
{"title":"A 65nm-node, Cu interconnect technology using porous SiOCH film (k=2.5) covered with ultra-thin, low-k pore seal (k=2.7)","authors":"M. Tada, Y. Harada, T. Tamura, N. Inoue, F. Ito, M. Yoshiki, H. Ohtake, M. Narihiro, M. Tagami, M. Ueki, K. Hijioka, M. Abe, T. Takeuchi, S. Saito, T. Onodera, N. Furutake, K. Arai, K. Fujii, Y. Hayashi","doi":"10.1109/IEDM.2003.1269411","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269411","url":null,"abstract":"A highly reliable, 65 nm-node Cu interconnect technology has been developed with 180 nm/200 nm-pitched lines connected through /spl phi/100 nm-vias. A porous SiOCH film (k=2.5) with sub-nanometer pores is introduced for the inter-metal dielectrics (IMD) on a non-porous, rigid SiOCH film (k=2.9) for the via-infra-line dielectrics (via-ILD). A key breakthrough is a special pore-seal technique, in which the trench-etched surface of the porous SiOCH is covered with an ultra-thin, low-k organic silica film (k=2.7), thus improving the line-to-line TDDB (time dependent dielectric breakdown) reliability of the narrow-pitched Cu lines. The fully-scaled-down, 65 nm-node Cu interconnects with the porous-on-rigid SiOCH hybrid structure achieve excellent performance and reliability.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116725804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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