Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706544
I. Saad, H. M. Zuhir, C. Bun Seng, D. Pogaku, A. R. A. Bakar, A. M. Khairul, B. Ghosh, N. Bolong, R. Ismail, U. Hashim
The Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. There are significant drop in subthreshold slope (S) while threshold voltage is increase as the body doping concentration increases. It is notable that for body doping concentration above 1020, the S values keep increasing which is not recommended as the switching speed getting higher distracting performance of the device. An improved stability of threshold voltage, VTH was found for VESIMOS-DP device of various DP size ranging from 20nm to 80nm. The stability is due to the reducing charge sharing effects between source and drain region. In addition, the output characteristic was also highlighted a very good drain current at different gate voltage with the increasing of drain voltage for VESIMOS-DP with high body doping concentration. VESIMOS-DP with low body doping concentration suffers PBT effect that prevents the device from being able to switch off. Hence, high body doping concentrations are imperative for obtaining better device characteristics and ensure the device works in II mode.
{"title":"Body doping analysis of vertical strained-SiGe Impact Ionization MOSFET incorporating dielectric pocket (VESIMOS-DP)","authors":"I. Saad, H. M. Zuhir, C. Bun Seng, D. Pogaku, A. R. A. Bakar, A. M. Khairul, B. Ghosh, N. Bolong, R. Ismail, U. Hashim","doi":"10.1109/RSM.2013.6706544","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706544","url":null,"abstract":"The Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. There are significant drop in subthreshold slope (S) while threshold voltage is increase as the body doping concentration increases. It is notable that for body doping concentration above 1020, the S values keep increasing which is not recommended as the switching speed getting higher distracting performance of the device. An improved stability of threshold voltage, VTH was found for VESIMOS-DP device of various DP size ranging from 20nm to 80nm. The stability is due to the reducing charge sharing effects between source and drain region. In addition, the output characteristic was also highlighted a very good drain current at different gate voltage with the increasing of drain voltage for VESIMOS-DP with high body doping concentration. VESIMOS-DP with low body doping concentration suffers PBT effect that prevents the device from being able to switch off. Hence, high body doping concentrations are imperative for obtaining better device characteristics and ensure the device works in II mode.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114208027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706539
M. M. Ramli, S. S. Isa, S. Henley
Vacuum filtration method was applied to build optically homogeneous film of palladium (Pd) nanoparticles dispersed multi-walled carbon nanotubes (MWCNTs) networks on plastic substrate. Measurement of the sheet resistance as a function of MWCNTs concentration showed a transition from 2D percolation to 3D conduction behaviour when the concentration of MWCNTs exceeded 0.015 mg/ml. The electrical response to H2 gas exposure was investigated at room temperature.
{"title":"Fabrication of multi-walled carbon nanotubes hydrogen sensor on plastic","authors":"M. M. Ramli, S. S. Isa, S. Henley","doi":"10.1109/RSM.2013.6706539","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706539","url":null,"abstract":"Vacuum filtration method was applied to build optically homogeneous film of palladium (Pd) nanoparticles dispersed multi-walled carbon nanotubes (MWCNTs) networks on plastic substrate. Measurement of the sheet resistance as a function of MWCNTs concentration showed a transition from 2D percolation to 3D conduction behaviour when the concentration of MWCNTs exceeded 0.015 mg/ml. The electrical response to H2 gas exposure was investigated at room temperature.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114942238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706470
Noraini Marsi, B. Majlis, A. A. Hamzah, Faisal Mohd Yasin
Two silicon wafer size of 2.5 mm × 2.5 mm with 1 μm LPCVD silicon carbide (SiC) and 200 nm LPCVD silicon nitride, respectively has been characterize direct bonding between silicon nitride and silicon carbide surfaces. Chemical-mechanical polishing (CMP) treatment processes were performed to reduce the surface roughness of both surfaces before the surface are bonded to each other. The surface roughness shows about 1 μm before CMP treatment, while the smoothness of the surface roughness values as low as 20 nm was obtained after CMP treatment as measured by infinite focus microscopy (IFM). The interface between SiC/SiN layers on Si wafer was inspected by scanning electron microscopy (SEM). Heat treatment with different annealing temperatures is indentified that an optimized annealing process was at 400 °C for 2 hours to allow the bond-forming interface between silicon nitride and silicon carbide surfaces being bonded at 8.3467 MPa.
{"title":"Characterization direct bonding of SiC/SiN layer on Si wafer for MEMS capacitive pressure sensor","authors":"Noraini Marsi, B. Majlis, A. A. Hamzah, Faisal Mohd Yasin","doi":"10.1109/RSM.2013.6706470","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706470","url":null,"abstract":"Two silicon wafer size of 2.5 mm × 2.5 mm with 1 μm LPCVD silicon carbide (SiC) and 200 nm LPCVD silicon nitride, respectively has been characterize direct bonding between silicon nitride and silicon carbide surfaces. Chemical-mechanical polishing (CMP) treatment processes were performed to reduce the surface roughness of both surfaces before the surface are bonded to each other. The surface roughness shows about 1 μm before CMP treatment, while the smoothness of the surface roughness values as low as 20 nm was obtained after CMP treatment as measured by infinite focus microscopy (IFM). The interface between SiC/SiN layers on Si wafer was inspected by scanning electron microscopy (SEM). Heat treatment with different annealing temperatures is indentified that an optimized annealing process was at 400 °C for 2 hours to allow the bond-forming interface between silicon nitride and silicon carbide surfaces being bonded at 8.3467 MPa.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129760109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706547
S. Farhana, A. Alam, Sheroz Khan
In this paper, we describe the development of small signal model of a CNTFET. The development consist of high frequency response of CNTFET. The CNTFET generates higher output rather than the conventional Si MOSFET. An SPICE model for enhancement mode Carbon nanotube transistor has been developed. The performance analysis of the CNTFET shows the desirable performance parameter in terms of 10 Thz frequency with 1.8 mS.
{"title":"High frequency small signal modeling of CNTFET","authors":"S. Farhana, A. Alam, Sheroz Khan","doi":"10.1109/RSM.2013.6706547","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706547","url":null,"abstract":"In this paper, we describe the development of small signal model of a CNTFET. The development consist of high frequency response of CNTFET. The CNTFET generates higher output rather than the conventional Si MOSFET. An SPICE model for enhancement mode Carbon nanotube transistor has been developed. The performance analysis of the CNTFET shows the desirable performance parameter in terms of 10 Thz frequency with 1.8 mS.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129803978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706458
Aliza Aini Md Ralib, A. Nordin, U. Hashim
The performance of surface acoustic wave resonator in CMOS technology for single and double electrode (IDT) structure is presented. Interdigitated electrodes (IDT) structure in surface acoustic wave (SAW) resonator is the most crucial component for excitation of SAW devices. Possible configurations for the IDT are single electrode and double electrode. The performance of the resonator for single and double electrode is compared at a frequency range of 0.5 GHz to 1 GHz. 2D Finite element modeling of the CMOS SAW resonator was simulated using COMSOL Multiphysics® for three step analysis eigen frequency, frequency domain and time domain analysis. The structure and dimension of the device is based on 0.18 μm RF CMOS process where the pattern of IDT is fabricated using standard CMOS fabrication process. The simulated results shows high quality factor in the order of thousands for double electrode CMOS SAW resonator compared to single electrode CMOS SAW resonator.
{"title":"Finite element modeling of SAW resonator in CMOS technology for single and double interdigitated electrode (IDT) structure","authors":"Aliza Aini Md Ralib, A. Nordin, U. Hashim","doi":"10.1109/RSM.2013.6706458","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706458","url":null,"abstract":"The performance of surface acoustic wave resonator in CMOS technology for single and double electrode (IDT) structure is presented. Interdigitated electrodes (IDT) structure in surface acoustic wave (SAW) resonator is the most crucial component for excitation of SAW devices. Possible configurations for the IDT are single electrode and double electrode. The performance of the resonator for single and double electrode is compared at a frequency range of 0.5 GHz to 1 GHz. 2D Finite element modeling of the CMOS SAW resonator was simulated using COMSOL Multiphysics® for three step analysis eigen frequency, frequency domain and time domain analysis. The structure and dimension of the device is based on 0.18 μm RF CMOS process where the pattern of IDT is fabricated using standard CMOS fabrication process. The simulated results shows high quality factor in the order of thousands for double electrode CMOS SAW resonator compared to single electrode CMOS SAW resonator.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130064796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706536
R. Prasad, U. Hashim, K. L. Foo, M. Shafiq
Zinc oxide nanorods was synthesized by using hydrothermal growth due to simplicity and involve low temperature processing that is 930C. Low temperature processing is very essential for ZnO nanorod synthesis because defect on developing nano-device can be avoided. Development of nano-device with minimal defect is essential to ensure that the performances of the nano device is optimum for sensing bio-molecular substances. Zinc oxide has become the most remarkable choice among other metal oxides semiconductor due to many criteria such as economical cost, unique physical and electrical properties and biocompatible. Initially, ZnO thin films was prepared by using sol gel method. The ZnO seed solution was prepared using conventional sol-gel route. Zinc oxide solution was prepared in two different solvents which are isopropanol (IPA) and methanol (MeOH) in order to investigate the influence of solvent to the quality of ZnO nanorods. MEA, the sol stabilizer was added to the solution for the following 2 hours. Aluminum IDE electrode was deposited on the silicon wafer sample <;100> using traditional wet etching method. Positive photoresist (PR) was coated on the silicon wafer and followed with soft back for 90 seconds. IDE pattern transfer was done by exposing UV light (365nm) onto the PR for 10 seconds. After that, developing and etching process occurred for pattern transfer the IDE electrode onto the silicon wafer. The prepared seed solution was coated on silicon wafer by using speed coating method. Some of the coated samples underwent annealing process at temperature 2000C for 2 hours. The annealed and non-annealed sample undergoes hydrothermal growth method to synthesize ZnO nanorods. The synthesized nanorods underwent I-V test and capacitances to investigate the electrical behavior of ZnO nanorods. The annealed ZnO nanorods provided higher current, which was 900μA, as compared the non-annealed ZnO nanorods which was only 55 μA.
{"title":"Investigating the annealing effect on the conventional growth of ZnO nanorod through electrical characterization","authors":"R. Prasad, U. Hashim, K. L. Foo, M. Shafiq","doi":"10.1109/RSM.2013.6706536","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706536","url":null,"abstract":"Zinc oxide nanorods was synthesized by using hydrothermal growth due to simplicity and involve low temperature processing that is 930C. Low temperature processing is very essential for ZnO nanorod synthesis because defect on developing nano-device can be avoided. Development of nano-device with minimal defect is essential to ensure that the performances of the nano device is optimum for sensing bio-molecular substances. Zinc oxide has become the most remarkable choice among other metal oxides semiconductor due to many criteria such as economical cost, unique physical and electrical properties and biocompatible. Initially, ZnO thin films was prepared by using sol gel method. The ZnO seed solution was prepared using conventional sol-gel route. Zinc oxide solution was prepared in two different solvents which are isopropanol (IPA) and methanol (MeOH) in order to investigate the influence of solvent to the quality of ZnO nanorods. MEA, the sol stabilizer was added to the solution for the following 2 hours. Aluminum IDE electrode was deposited on the silicon wafer sample <;100> using traditional wet etching method. Positive photoresist (PR) was coated on the silicon wafer and followed with soft back for 90 seconds. IDE pattern transfer was done by exposing UV light (365nm) onto the PR for 10 seconds. After that, developing and etching process occurred for pattern transfer the IDE electrode onto the silicon wafer. The prepared seed solution was coated on silicon wafer by using speed coating method. Some of the coated samples underwent annealing process at temperature 2000C for 2 hours. The annealed and non-annealed sample undergoes hydrothermal growth method to synthesize ZnO nanorods. The synthesized nanorods underwent I-V test and capacitances to investigate the electrical behavior of ZnO nanorods. The annealed ZnO nanorods provided higher current, which was 900μA, as compared the non-annealed ZnO nanorods which was only 55 μA.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115879992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706575
A. Dehzangi, F. Larki, B. Majlis, M. Hamidon, M. Navasery, E. Gharibshahi, N. Khalilzadeh, M. Vakilian, E. Saion
Side gate p-type Junctionless Silicon transistor is fabricated by AFM nanolithography on low-doped (105 cm-3) SOI wafer. In this work, the simulation characteristic of the device using TCAD Sentaurus in on state will be studied. The results show that the device is the pinch off transistor, works in on state for zero gate voltage in depletion mode. Negative gate voltage drives the device into on state, but unable to make significant effect on drain current as accmulation mode. Simulation results for valence band energy, electric field and hole density are investigated along the active regions. The influence of the electric field due to the applied voltages of VDS and VG on charge distribution is much more when the device operates at the saturation region. The hole quasi-Fermi level has a positive slope showing the current flows from source to drain.
{"title":"Numerical study of side gate junction-less transistor in on state","authors":"A. Dehzangi, F. Larki, B. Majlis, M. Hamidon, M. Navasery, E. Gharibshahi, N. Khalilzadeh, M. Vakilian, E. Saion","doi":"10.1109/RSM.2013.6706575","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706575","url":null,"abstract":"Side gate p-type Junctionless Silicon transistor is fabricated by AFM nanolithography on low-doped (105 cm-3) SOI wafer. In this work, the simulation characteristic of the device using TCAD Sentaurus in on state will be studied. The results show that the device is the pinch off transistor, works in on state for zero gate voltage in depletion mode. Negative gate voltage drives the device into on state, but unable to make significant effect on drain current as accmulation mode. Simulation results for valence band energy, electric field and hole density are investigated along the active regions. The influence of the electric field due to the applied voltages of VDS and VG on charge distribution is much more when the device operates at the saturation region. The hole quasi-Fermi level has a positive slope showing the current flows from source to drain.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123308257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706461
S. R. Kasjoo, Arun K. Singh, U. Hashim, A. Song
A novel type of unipolar nanodiode, the self-switching diode (SSD), has recently shown promising properties as an ultra-high-speed detector at room temperature by the utilization of its nonlinear diode-like behavior and intrinsically low parasitic capacitance. In this report, a large SSD array with approximately 2,000 SSDs connected in parallel within the fingers of an interdigital structure was coupled with a printed-circuit-board- (PCB-) based wideband patch antenna, operating in the radio-frequency (RF) region. Such a large array was realized in a single lithography step without the need for interconnection layers. This allows for a simple, low-cost and reproducible fabrication process. Despite of the large impedance mismatch between the SSD array and the PCB-based antenna, the device was able to detect RF signals transmitted using a network analyzer via another patch antenna at distance of approximately 70 cm from it, at 2.45 GHz. The estimated room-temperature extrinsic voltage responsivity of the device and its noise-equivalent power, measured at 5 cm away from the transmitted RF signals and at zero bias, were 10 mV/mW and 1.2 nW/Hz1/2, respectively. The results have shown that the SSDs can be utilized in many RF applications at low cost.
{"title":"Characterization of unipolar nanorectifiers coupled with an RF antenna","authors":"S. R. Kasjoo, Arun K. Singh, U. Hashim, A. Song","doi":"10.1109/RSM.2013.6706461","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706461","url":null,"abstract":"A novel type of unipolar nanodiode, the self-switching diode (SSD), has recently shown promising properties as an ultra-high-speed detector at room temperature by the utilization of its nonlinear diode-like behavior and intrinsically low parasitic capacitance. In this report, a large SSD array with approximately 2,000 SSDs connected in parallel within the fingers of an interdigital structure was coupled with a printed-circuit-board- (PCB-) based wideband patch antenna, operating in the radio-frequency (RF) region. Such a large array was realized in a single lithography step without the need for interconnection layers. This allows for a simple, low-cost and reproducible fabrication process. Despite of the large impedance mismatch between the SSD array and the PCB-based antenna, the device was able to detect RF signals transmitted using a network analyzer via another patch antenna at distance of approximately 70 cm from it, at 2.45 GHz. The estimated room-temperature extrinsic voltage responsivity of the device and its noise-equivalent power, measured at 5 cm away from the transmitted RF signals and at zero bias, were 10 mV/mW and 1.2 nW/Hz1/2, respectively. The results have shown that the SSDs can be utilized in many RF applications at low cost.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127797393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706521
Intan Zubaidah Mazlan, M. Wahid, Ahmad Fariz Hassan, Mohd Azarulsani Md Azidin, Noor Aqsa Nadeea Mat Isa
Wavelength converter is simply a device for converting the injected signal light from one wavelength to another. A simulation wavelength converter made out of a semiconductor optical amplifier and an optical bandpass filter is presented in this paper. The wavelength converter has a simple configuration and allows future photonic integration.
{"title":"Four wave mixing and cross gain modulation wavelength converters in semiconductor optical amplifier","authors":"Intan Zubaidah Mazlan, M. Wahid, Ahmad Fariz Hassan, Mohd Azarulsani Md Azidin, Noor Aqsa Nadeea Mat Isa","doi":"10.1109/RSM.2013.6706521","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706521","url":null,"abstract":"Wavelength converter is simply a device for converting the injected signal light from one wavelength to another. A simulation wavelength converter made out of a semiconductor optical amplifier and an optical bandpass filter is presented in this paper. The wavelength converter has a simple configuration and allows future photonic integration.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123133289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-01DOI: 10.1109/RSM.2013.6706478
Siti Musliha Ajmal Binti Mokhtar, W. Abdullah
This paper will first review on some applications of newly found passive element, the memristor. Utilizing the beneficial characteristic of memristor where it can remember its last state, more and more improvements on today electronic designs has been proposed. However, it is crucial to observe the behavior of memristor model before applying into circuits, especially when the memristor is coupled with other devices. In this paper, LTspice memristor model is used to simulate memristor behavior and applied to the basic delay element circuit. The circuit used a tristate inverter as the delay element. It controls the current flowing to the parasitic capacitor, thus controlling the delay. The compatibility of memristor with the delay element is also in consideration to ensure the functionality of the circuits. At the end, a basic delay element using inverter and memristor is presented. This paper is divided into 4 sections, including the introduction where few examples of memristor applications are explained. It follows by next section where the inverter delay characteristic is narrated. Section 3 is about a mathematical model of memristor that been used to provide a specific memristor resistance in order to get certain delay value during simulation. Using LT spice, a memristor based delay circuit design is then proposed and the delay is observed by circuit simulation. In conclusion, the calculated R and delay value is then compared to the simulation result in order to verify circuit functionality.
{"title":"Memristor based delay element using current starved inverter","authors":"Siti Musliha Ajmal Binti Mokhtar, W. Abdullah","doi":"10.1109/RSM.2013.6706478","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706478","url":null,"abstract":"This paper will first review on some applications of newly found passive element, the memristor. Utilizing the beneficial characteristic of memristor where it can remember its last state, more and more improvements on today electronic designs has been proposed. However, it is crucial to observe the behavior of memristor model before applying into circuits, especially when the memristor is coupled with other devices. In this paper, LTspice memristor model is used to simulate memristor behavior and applied to the basic delay element circuit. The circuit used a tristate inverter as the delay element. It controls the current flowing to the parasitic capacitor, thus controlling the delay. The compatibility of memristor with the delay element is also in consideration to ensure the functionality of the circuits. At the end, a basic delay element using inverter and memristor is presented. This paper is divided into 4 sections, including the introduction where few examples of memristor applications are explained. It follows by next section where the inverter delay characteristic is narrated. Section 3 is about a mathematical model of memristor that been used to provide a specific memristor resistance in order to get certain delay value during simulation. Using LT spice, a memristor based delay circuit design is then proposed and the delay is observed by circuit simulation. In conclusion, the calculated R and delay value is then compared to the simulation result in order to verify circuit functionality.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"325 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123506653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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