Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654306
G. Refai-Ahmed, Hoa Do, Brian Philofsky, Anthony Torza
The evolution of wireless networks from 3G/4G to 5G will significantly increase the bandwidth, capacity and capability of these systems. To address these growing requirements, chip manufacturers are using aggressive node scaling coupled with tighter SoC integration to deliver the promises of the next generation network without negatively impacting system power. The combination of these techniques contribute to the breakdown of Dennard Scaling and result in higher power and thermal densities per device as we integrate more circuitry into smaller areas demanding a greater challenge to existing thermal design techniques and driving changes to this development. This paper will explore one such change using a lidless package paired with an innovative surface and mounting method to address this growing power density paradigm.
{"title":"Extending the Cooling Limit of Remote Radio Head (RRH) Systems Based on Level 1 Thermal Management","authors":"G. Refai-Ahmed, Hoa Do, Brian Philofsky, Anthony Torza","doi":"10.1109/EPTC.2018.8654306","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654306","url":null,"abstract":"The evolution of wireless networks from 3G/4G to 5G will significantly increase the bandwidth, capacity and capability of these systems. To address these growing requirements, chip manufacturers are using aggressive node scaling coupled with tighter SoC integration to deliver the promises of the next generation network without negatively impacting system power. The combination of these techniques contribute to the breakdown of Dennard Scaling and result in higher power and thermal densities per device as we integrate more circuitry into smaller areas demanding a greater challenge to existing thermal design techniques and driving changes to this development. This paper will explore one such change using a lidless package paired with an innovative surface and mounting method to address this growing power density paradigm.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122184013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654361
Y. Andriani, Xiaobai Wang, Songlin Liu, Zhaohui Chen, Xiaowu Zhang
The fan-out wafer-level packaging (FOWLP) has gained significant interests owing to the cost effectiveness, high performance, high I/O density, high integration capability, small form factor and diverse range of applications. FOWLP is currently seen as the best fit for the highly demanding mobile and wireless market, and is attractive for other markets focusing on high performance and small size. However, up to date, wafer warpage is still one of the unresolved challenges in this field. As an integral component of the electronic packaging, dielectric materials could also contribute to the overall warpage. Nonetheless, this contribution is sometimes excluded from the theoretical warpage calculation. Even when the dielectric material was included in the finite element modeling, the simulation results have not been able to duplicate the actual experimental results yet. The difference between the modeling and the experimental results could be due to the only incorporation of elastic properties of the polymer dielectric materials in the simulation, instead of the viscoelastic behavior. Here, we reported the thermomechanical, and viscoelastic properties of three commercial dielectric materials that have been used in the FOWLP and construct master curves via the time-temperature superposition principle to study the relaxation behaviors of the dielectric materials. These results could support the ongoing development of an accurate modeling system for prediction and control of wafer warpage in the FOWLP.
{"title":"Thermomechanical and Viscoelastic Properties of Dielectric Materials Used in Fan-Out Wafer-Level Packaging","authors":"Y. Andriani, Xiaobai Wang, Songlin Liu, Zhaohui Chen, Xiaowu Zhang","doi":"10.1109/EPTC.2018.8654361","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654361","url":null,"abstract":"The fan-out wafer-level packaging (FOWLP) has gained significant interests owing to the cost effectiveness, high performance, high I/O density, high integration capability, small form factor and diverse range of applications. FOWLP is currently seen as the best fit for the highly demanding mobile and wireless market, and is attractive for other markets focusing on high performance and small size. However, up to date, wafer warpage is still one of the unresolved challenges in this field. As an integral component of the electronic packaging, dielectric materials could also contribute to the overall warpage. Nonetheless, this contribution is sometimes excluded from the theoretical warpage calculation. Even when the dielectric material was included in the finite element modeling, the simulation results have not been able to duplicate the actual experimental results yet. The difference between the modeling and the experimental results could be due to the only incorporation of elastic properties of the polymer dielectric materials in the simulation, instead of the viscoelastic behavior. Here, we reported the thermomechanical, and viscoelastic properties of three commercial dielectric materials that have been used in the FOWLP and construct master curves via the time-temperature superposition principle to study the relaxation behaviors of the dielectric materials. These results could support the ongoing development of an accurate modeling system for prediction and control of wafer warpage in the FOWLP.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128204701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654315
Xiaobai Wang, Y. Andriani, Songlin Liu, Zhaohui Chen, Xiaowu Zhang
Wafer warpage has remained as a big issue in the semiconductor industry due to the defects it may cause, such as delamination and cracks in the molded devices. In the FOWLP process, the wafer warpage becomes even more critical due to the stringent process requirements. Although quite a few models have been set up to predict the shrinkage and warpage, research on the correlation between the Epoxy Molding Compound (EMC) cure shrinkage and warpage is still very limited due to the lack of experimental data input on the chemical cure shrinkage. In this paper, the chemical cure shrinkage of five main stream EMCs used in FOWLP were investigated in-situ. Differential Scanning Calorimeter (DSC) was used to monitor the curing process, in order to find out a suitable heating profile for shrinkage test. Thermomechanical analyzer (TMA) equipped with a dilatometer accessory was used to investigate the real-time shrinkage of EMCs at an isothermal curing condition. The results show that the chemical cure shrinkage of the selected EMCs is between 0.4% and 4%.
{"title":"In-situ Cure Shrinkage Characterization of Epoxy Molding Compounds for Fan-Out Wafer-Level Packaging","authors":"Xiaobai Wang, Y. Andriani, Songlin Liu, Zhaohui Chen, Xiaowu Zhang","doi":"10.1109/EPTC.2018.8654315","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654315","url":null,"abstract":"Wafer warpage has remained as a big issue in the semiconductor industry due to the defects it may cause, such as delamination and cracks in the molded devices. In the FOWLP process, the wafer warpage becomes even more critical due to the stringent process requirements. Although quite a few models have been set up to predict the shrinkage and warpage, research on the correlation between the Epoxy Molding Compound (EMC) cure shrinkage and warpage is still very limited due to the lack of experimental data input on the chemical cure shrinkage. In this paper, the chemical cure shrinkage of five main stream EMCs used in FOWLP were investigated in-situ. Differential Scanning Calorimeter (DSC) was used to monitor the curing process, in order to find out a suitable heating profile for shrinkage test. Thermomechanical analyzer (TMA) equipped with a dilatometer accessory was used to investigate the real-time shrinkage of EMCs at an isothermal curing condition. The results show that the chemical cure shrinkage of the selected EMCs is between 0.4% and 4%.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130575020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654446
R. Kandasamy, Pengfei Liu, H. Feng, T. Wong, K. Toh
An experimental investigation on closed-loop single nozzle spray cooling with and without the presence of non-condensable gas in the system was carried out. A circular bare copper heated surface of area 3.14 cm2 was spray cooled with dielectric liquid PF-5060 and FC-3284 in this study. Results showed that spray cooling without non-condensable gas showed a lower surface temperature for the same heat flux compared to that with non-condensable gas.
{"title":"Spray cooling enhancement studies using dielectric liquid","authors":"R. Kandasamy, Pengfei Liu, H. Feng, T. Wong, K. Toh","doi":"10.1109/EPTC.2018.8654446","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654446","url":null,"abstract":"An experimental investigation on closed-loop single nozzle spray cooling with and without the presence of non-condensable gas in the system was carried out. A circular bare copper heated surface of area 3.14 cm2 was spray cooled with dielectric liquid PF-5060 and FC-3284 in this study. Results showed that spray cooling without non-condensable gas showed a lower surface temperature for the same heat flux compared to that with non-condensable gas.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120974755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654390
A. Gu, John Auyoong
Existing technologies have become less effective for structural inspection and metrology for highly complex 3D semiconductor packages. It is virtually impossible to measure embedded structures of a semiconductor package without physically opening it. In this paper, we propose a new workflow to enable 3D structural measurements without physically altering or destroying a sample. Based on a high-resolution 3D X-ray tomography technique, we have developed a semi-automated metrology workflow to extract critical geometric information from intact packages. In the first case study, the test sample was a commercial DRAM package with a 4-die stack. We utilized the measurement workflow to have successfully extracted bond line thickness, solder volume and solder shape information. In the second case study, several smartphone camera modules were used to further validate this metrology workflow. The measurement was focused on two major components of the camera module: CMOS imaging sensor (CIS) package and lens optics assembly. After the samples were imaged with XRM at high resolution, a measurement workflow followed to measure Au bump height, volume, surface area, and other critical dimensions in the CIS package. In the case of lens optics measurement, lens gap, lens thickness, lens tilt and decentricity were measured from 3D tomographic images using the similar workflow. The workflow was scripted to test multiple repetitive parts for high repeatability and reproducibility.
{"title":"3D Measurement Workflow for Packaging Development and Production Control Using High-Resolution 3D X-ray Microscope","authors":"A. Gu, John Auyoong","doi":"10.1109/EPTC.2018.8654390","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654390","url":null,"abstract":"Existing technologies have become less effective for structural inspection and metrology for highly complex 3D semiconductor packages. It is virtually impossible to measure embedded structures of a semiconductor package without physically opening it. In this paper, we propose a new workflow to enable 3D structural measurements without physically altering or destroying a sample. Based on a high-resolution 3D X-ray tomography technique, we have developed a semi-automated metrology workflow to extract critical geometric information from intact packages. In the first case study, the test sample was a commercial DRAM package with a 4-die stack. We utilized the measurement workflow to have successfully extracted bond line thickness, solder volume and solder shape information. In the second case study, several smartphone camera modules were used to further validate this metrology workflow. The measurement was focused on two major components of the camera module: CMOS imaging sensor (CIS) package and lens optics assembly. After the samples were imaged with XRM at high resolution, a measurement workflow followed to measure Au bump height, volume, surface area, and other critical dimensions in the CIS package. In the case of lens optics measurement, lens gap, lens thickness, lens tilt and decentricity were measured from 3D tomographic images using the similar workflow. The workflow was scripted to test multiple repetitive parts for high repeatability and reproducibility.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121089054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654326
Li Wern Chew, Paik Wen Ong
Printed circuit board (PCB) design with full ground referencing for high speed signaling is generally preferred for better or cleaner signal return path. However, this has become very challenging when platform design is trending toward a smaller and thinner form factor where having full ground layers in between PCB stack-up is no longer feasible for practical hardware implementation. With the increase in popularity to have signal-to-power referencing in PCB design, signal-integrity (SI) and power-integrity (PI) co-simulation is however not that straight forward and often comes with sophisticated co-sim’s assumptions. This is because signaling quality is impacted by noise coupling suffered by the signal which has high dependency on the power plane sizes and shapes, area of power referenced, as well as how well the power delivery network (PDN) design is. In this paper, we evaluate the SI performance of a super speed input/output (I/O) buffer with full ground plane or partial power plane as its return path. Three controlled electrical parameters - voltage threshold, peak-to-peak noise and frequency are varied in our studies to investigate the impact of power referencing to signal eye margin. From the study, it is shown that power referencing is doable for high-speed I/O on the conditions that the power referenced voltage rail is a low frequency rails that has dominant frequency contents in the range of less than 5% of the targeted signal operating frequency and the total peak-to-peak noise is below 330mVpp. With these findings, platform routing guidelines for I/O design could be more relaxed and flexible, by allowing partial power referencing to the high speed signal traces.
{"title":"SIPI Co-Sim: Signal Performance of Super Speed Differential I/O with Power Referencing Design","authors":"Li Wern Chew, Paik Wen Ong","doi":"10.1109/EPTC.2018.8654326","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654326","url":null,"abstract":"Printed circuit board (PCB) design with full ground referencing for high speed signaling is generally preferred for better or cleaner signal return path. However, this has become very challenging when platform design is trending toward a smaller and thinner form factor where having full ground layers in between PCB stack-up is no longer feasible for practical hardware implementation. With the increase in popularity to have signal-to-power referencing in PCB design, signal-integrity (SI) and power-integrity (PI) co-simulation is however not that straight forward and often comes with sophisticated co-sim’s assumptions. This is because signaling quality is impacted by noise coupling suffered by the signal which has high dependency on the power plane sizes and shapes, area of power referenced, as well as how well the power delivery network (PDN) design is. In this paper, we evaluate the SI performance of a super speed input/output (I/O) buffer with full ground plane or partial power plane as its return path. Three controlled electrical parameters - voltage threshold, peak-to-peak noise and frequency are varied in our studies to investigate the impact of power referencing to signal eye margin. From the study, it is shown that power referencing is doable for high-speed I/O on the conditions that the power referenced voltage rail is a low frequency rails that has dominant frequency contents in the range of less than 5% of the targeted signal operating frequency and the total peak-to-peak noise is below 330mVpp. With these findings, platform routing guidelines for I/O design could be more relaxed and flexible, by allowing partial power referencing to the high speed signal traces.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129984197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654353
Kota Tsugami, T. Asano, H. Kanaya
This paper presents the design of wideband 1 x 2 one-sided directional slot array antenna for 1 THz band imaging device. The antenna element is composed of top metal, dielectric substrate, and bottom floating metal layer. This antenna array has 2 antenna elements to achieve a high gain and wideband. The THz signal is injected by CPW transmission line. The simulation result of return loss, antenna gain is presented in this paper. The bandwidth of proposed antenna is 210 GHz (0.88 THz – 1.09 THz), the relative bandwidth is 21.3 % and the peak gain is 5.87 dBi at 1.04 THz.
{"title":"Wideband slot array antenna for 1 THz band imaging device","authors":"Kota Tsugami, T. Asano, H. Kanaya","doi":"10.1109/EPTC.2018.8654353","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654353","url":null,"abstract":"This paper presents the design of wideband 1 x 2 one-sided directional slot array antenna for 1 THz band imaging device. The antenna element is composed of top metal, dielectric substrate, and bottom floating metal layer. This antenna array has 2 antenna elements to achieve a high gain and wideband. The THz signal is injected by CPW transmission line. The simulation result of return loss, antenna gain is presented in this paper. The bandwidth of proposed antenna is 210 GHz (0.88 THz – 1.09 THz), the relative bandwidth is 21.3 % and the peak gain is 5.87 dBi at 1.04 THz.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131158819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654406
R. Dudek, M. Hildebrandt, K. Kreyssig, S. Rzepka, R. Döring, B. Seiler, T. Fries, M. Zhang, R. Ortmann
Developments directed towards autonomous driving require complex smart functionalities at reasonable cost, e.g., combined sensing and high volume data processing. Reliability remains a key issue in that process. However, in various cases dedicated automotive grade components are lacking. Therefore, thermo-mechanical reliability issues are one focus of the European project TRACE, which studies the issues for transfer of consumer electronics (CE) into automotive electronics (AE). Gaps between these use scenarios are figured out and measures to be taken are searched [1].Besides the well-known harsh environmental AE requirements, mounting induced effects on components loadings need to be considered. These mounting conditions superimpose stresses driven by the component-board induced CTE mismatch and are in particular critical for leadless components like QFNs, LGAs; WLPs, characteristic of CE use. For evaluation of this loading scenario, a combined measuring-simulation technique has been developed. It uses an optical multi-sensor metrology system for the thermo-mechanical deformation measurement of electronic components and systems for different size and resolution ranges. An application to critical components in an electronic control unit (ECU) is depicted.The combined experimental-numerical method is applied to test-setups, to figure out effects from board mounting on component reliability and characteristic limits due to mounting. Test-boards with systems in QFNs are analyzed. It is shown, that system effects can have major impact on components stress and solder fatigue life.
{"title":"“3rd Level” Solder Joint Reliability Investigations for Transfer of Consumer Electronics in Automotive Use","authors":"R. Dudek, M. Hildebrandt, K. Kreyssig, S. Rzepka, R. Döring, B. Seiler, T. Fries, M. Zhang, R. Ortmann","doi":"10.1109/EPTC.2018.8654406","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654406","url":null,"abstract":"Developments directed towards autonomous driving require complex smart functionalities at reasonable cost, e.g., combined sensing and high volume data processing. Reliability remains a key issue in that process. However, in various cases dedicated automotive grade components are lacking. Therefore, thermo-mechanical reliability issues are one focus of the European project TRACE, which studies the issues for transfer of consumer electronics (CE) into automotive electronics (AE). Gaps between these use scenarios are figured out and measures to be taken are searched [1].Besides the well-known harsh environmental AE requirements, mounting induced effects on components loadings need to be considered. These mounting conditions superimpose stresses driven by the component-board induced CTE mismatch and are in particular critical for leadless components like QFNs, LGAs; WLPs, characteristic of CE use. For evaluation of this loading scenario, a combined measuring-simulation technique has been developed. It uses an optical multi-sensor metrology system for the thermo-mechanical deformation measurement of electronic components and systems for different size and resolution ranges. An application to critical components in an electronic control unit (ECU) is depicted.The combined experimental-numerical method is applied to test-setups, to figure out effects from board mounting on component reliability and characteristic limits due to mounting. Test-boards with systems in QFNs are analyzed. It is shown, that system effects can have major impact on components stress and solder fatigue life.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134032675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654313
K. Pun, Jason Rotanson, Navdeep S. Dhaka, Chee-wah Cheung, A. Chan
This paper demonstrates the latest ultra-fine pitch scalability of off-chip IC assembly on an 18 $mu {mathrm{ m}}$ pitch chip-on-film (COF) package fabricated by novel fully additive process (FAP) with Ni-free surface finish plating, immersion Au/electroless Pd/immersion Au (IGEPIG). The COF assembled with Au-Au diffusion bonding method is evaluated in terms of electrical and mechanical performance. Comparison is made with various finishes including Electrolytic Ni/Au and electroless Ni/electroless Pd/immersion Au (ENEPIG). Excellent alignment with sufficient contact area is achieved even on such narrow traces. The substrate fabricated by FAP possess desirable trace profile suitable for fine pitch bonding. With different finishing, it is seen that surface roughness is the main contributing factor that interrupt diffusion and creep process in forming void on the joint interface while the elastic plastic properties of the material construction and tri-layer thickness affect the deformation of the interconnect structure. Correlations between the surface finish and the Au-Au solid state diffusion bonding on the COF is established. In terms of long term reliability, all finishes show stable contact resistance below 30 $text{m}omega $ with no open joint on the daisy chain connectivity after high temperature humidity storage at $85^{circ }text{C}$/85% RH (1000 hours) and air-to-air thermal shock test at $125^{circ }text{C}$/-$55^{circ }text{C}$ (1000 cycles).
本文展示了在18 $mu {mathrm{ m}}$螺距片上芯片(COF)封装上最新的超细间距可扩展性，该封装采用新颖的全增材工艺(FAP)，无镍表面电镀，浸入式Au/化学镀Pd/浸入式Au (IGEPIG)。对用Au-Au扩散键合法组装的COF进行了电学性能和力学性能评价。比较了电解Ni/Au和化学Ni/化学Pd/浸金(ENEPIG)等各种表面处理方法。即使在如此狭窄的迹线上，也可以实现具有足够接触面积的出色对准。采用FAP工艺制备的基板具有良好的迹线轮廓，适合于细间距键合。在不同的整理工艺条件下，表面粗糙度是影响接头界面孔洞形成过程中扩散和蠕变过程中断的主要因素，而材料结构的弹塑性性能和三层厚度影响连接结构的变形。建立了COF表面光洁度与Au-Au固体扩散键合之间的关系。就长期可靠性而言，在$85^{circ }text{C}$ /85高温湿度储存后，所有饰面都显示出稳定的接触电阻低于30 $text{m}omega $，雏菊链连通性上没有开放接头% RH (1000 hours) and air-to-air thermal shock test at $125^{circ }text{C}$/-$55^{circ }text{C}$ (1000 cycles).
{"title":"Demonstration of Ni-free Surface Finishing with IGEPIG for Solid-State Diffusion Bonding on Ultra-fine Pitch Chip-on-Film (COF)","authors":"K. Pun, Jason Rotanson, Navdeep S. Dhaka, Chee-wah Cheung, A. Chan","doi":"10.1109/EPTC.2018.8654313","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654313","url":null,"abstract":"This paper demonstrates the latest ultra-fine pitch scalability of off-chip IC assembly on an 18 $mu {mathrm{ m}}$ pitch chip-on-film (COF) package fabricated by novel fully additive process (FAP) with Ni-free surface finish plating, immersion Au/electroless Pd/immersion Au (IGEPIG). The COF assembled with Au-Au diffusion bonding method is evaluated in terms of electrical and mechanical performance. Comparison is made with various finishes including Electrolytic Ni/Au and electroless Ni/electroless Pd/immersion Au (ENEPIG). Excellent alignment with sufficient contact area is achieved even on such narrow traces. The substrate fabricated by FAP possess desirable trace profile suitable for fine pitch bonding. With different finishing, it is seen that surface roughness is the main contributing factor that interrupt diffusion and creep process in forming void on the joint interface while the elastic plastic properties of the material construction and tri-layer thickness affect the deformation of the interconnect structure. Correlations between the surface finish and the Au-Au solid state diffusion bonding on the COF is established. In terms of long term reliability, all finishes show stable contact resistance below 30 $text{m}omega $ with no open joint on the daisy chain connectivity after high temperature humidity storage at $85^{circ }text{C}$/85% RH (1000 hours) and air-to-air thermal shock test at $125^{circ }text{C}$/-$55^{circ }text{C}$ (1000 cycles).","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115160705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-12-01DOI: 10.1109/EPTC.2018.8654340
Eric Jian Rong Phua, Ming Liu, J. Lim, Bokun Cho, C. Gan
Epoxy is ubiquitous in the electronics industry for its application as a package resin. However, harsher environments and more stringent conditions arising from emerging applications have driven epoxy to its servicing limit [1] –[5]. These applications have to rely heavily on fillers to push the performance limit further. Alternative high performance electronic packaging materials, including bismaleimide (BMI) [6, 7] and cyanate esters (CE) [8] –[10], have also been investigated. In this paper, we will discuss a variant of phthalonitrile (PN) [11] –[14], which as a resin itself is able to withstand a temperature of $300^{circ}mathrm{C}$ in normal atmosphere. Besides comparable properties especially in terms of mechanical strength, PN also exhibits strong thermal stability. High quality adherence of filler-matrix is not just observed in scanning electron microscopy (SEM) images but also reflected in the bond shear strength. The underlying mechanism of the performance of PN as an alternative packaging material was studied using Gaussian09™. It is shown that the interaction of triazine and phthalocyanine with silicon and aluminum atoms on silica and alumina respectively, is the factor behind the bond shear behavior observed.
{"title":"Phthalonitrile-Based Electronic Packages for High Temperature Applications","authors":"Eric Jian Rong Phua, Ming Liu, J. Lim, Bokun Cho, C. Gan","doi":"10.1109/EPTC.2018.8654340","DOIUrl":"https://doi.org/10.1109/EPTC.2018.8654340","url":null,"abstract":"Epoxy is ubiquitous in the electronics industry for its application as a package resin. However, harsher environments and more stringent conditions arising from emerging applications have driven epoxy to its servicing limit [1] –[5]. These applications have to rely heavily on fillers to push the performance limit further. Alternative high performance electronic packaging materials, including bismaleimide (BMI) [6, 7] and cyanate esters (CE) [8] –[10], have also been investigated. In this paper, we will discuss a variant of phthalonitrile (PN) [11] –[14], which as a resin itself is able to withstand a temperature of $300^{circ}mathrm{C}$ in normal atmosphere. Besides comparable properties especially in terms of mechanical strength, PN also exhibits strong thermal stability. High quality adherence of filler-matrix is not just observed in scanning electron microscopy (SEM) images but also reflected in the bond shear strength. The underlying mechanism of the performance of PN as an alternative packaging material was studied using Gaussian09™. It is shown that the interaction of triazine and phthalocyanine with silicon and aluminum atoms on silica and alumina respectively, is the factor behind the bond shear behavior observed.","PeriodicalId":360239,"journal":{"name":"2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132905765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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