Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450502
A. Abu-Issa, S. Quigley
This paper presents a smoothing technique for the output sequence of linear feedback shift registers (LFSR) to reduce power consumption in test-per-scan built-in self-test (BIST) applications. The proposed smoother is implemented by adding one multiplexer between the LFSR and scan-chain input of a single scan-chain. The size of the multiplexer is determined the desired smoothing degree. When the smoothed sequence of the LFSR is used to feed the test patterns in test-per-scan BIST, it reduces the number of transitions that occur at scan-chain input during scan shift operations by 25% to 50% depending on the smoothing degree, and hence reduces switching activity in the circuit-under-test (CUT) during test application. The proposed technique can be extended to multiple scan-chains BIST, also to test-per-clock applications. Various properties of the proposed technique and the methodology of the design are presented in this paper. Experimental results for the ISCAS'89 benchmark circuits show that the proposed design can reduce the switching activity up to 55% with a negligible effect on the fault coverage and test application time.
{"title":"Multi-degree smoother for low power consumption in single and multiple scan-chains BIST","authors":"A. Abu-Issa, S. Quigley","doi":"10.1109/ISQED.2010.5450502","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450502","url":null,"abstract":"This paper presents a smoothing technique for the output sequence of linear feedback shift registers (LFSR) to reduce power consumption in test-per-scan built-in self-test (BIST) applications. The proposed smoother is implemented by adding one multiplexer between the LFSR and scan-chain input of a single scan-chain. The size of the multiplexer is determined the desired smoothing degree. When the smoothed sequence of the LFSR is used to feed the test patterns in test-per-scan BIST, it reduces the number of transitions that occur at scan-chain input during scan shift operations by 25% to 50% depending on the smoothing degree, and hence reduces switching activity in the circuit-under-test (CUT) during test application. The proposed technique can be extended to multiple scan-chains BIST, also to test-per-clock applications. Various properties of the proposed technique and the methodology of the design are presented in this paper. Experimental results for the ISCAS'89 benchmark circuits show that the proposed design can reduce the switching activity up to 55% with a negligible effect on the fault coverage and test application time.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128703492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450461
Izumi Nitta, Yuji Kanazawa, D. Fukuda, Toshiyuki Shibuya, N. Idani, Masaru Ito, O. Yamasaki, Norihiro Harada, T. Hiramoto
Chemical Mechanical Polishing (CMP)-aware design has become important for reliability and yield. Recent work on predictive models for wafer surface planarity of Cu CMP has proven that the variation of wafer surface planarity is impacted by the metal perimeter in addition to the pattern density. Dummy fill insertion has been widely adopted to improve the CMP planarity in industrial design flows. However, conventional dummy fill insertion has been derived mainly to optimize the pattern density uniformity, which may worsen the CMP planarity because of missing impacts due to metal perimeter. In this paper, we propose; 1) a design of experiment (DOE) based method of evaluating the quality of fill insertion by using a CMP simulator which considers the impacts due to both pattern density and metal perimeter, and 2) a condition-based dummy fill insertion using the results of the proposed DOE method. Compared to the conventional pattern density driven rule-based fill insertion, the proposed method reduces the post-CMP Cu surface height variation by 24.3%. The metric of the metal perimeter may be applied to the model-based fill insertion methods, which will improve the planarity in the practical fill insertion flow.
{"title":"“Condition-based” dummy fill insertion method based on ECP and CMP predictive models","authors":"Izumi Nitta, Yuji Kanazawa, D. Fukuda, Toshiyuki Shibuya, N. Idani, Masaru Ito, O. Yamasaki, Norihiro Harada, T. Hiramoto","doi":"10.1109/ISQED.2010.5450461","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450461","url":null,"abstract":"Chemical Mechanical Polishing (CMP)-aware design has become important for reliability and yield. Recent work on predictive models for wafer surface planarity of Cu CMP has proven that the variation of wafer surface planarity is impacted by the metal perimeter in addition to the pattern density. Dummy fill insertion has been widely adopted to improve the CMP planarity in industrial design flows. However, conventional dummy fill insertion has been derived mainly to optimize the pattern density uniformity, which may worsen the CMP planarity because of missing impacts due to metal perimeter. In this paper, we propose; 1) a design of experiment (DOE) based method of evaluating the quality of fill insertion by using a CMP simulator which considers the impacts due to both pattern density and metal perimeter, and 2) a condition-based dummy fill insertion using the results of the proposed DOE method. Compared to the conventional pattern density driven rule-based fill insertion, the proposed method reduces the post-CMP Cu surface height variation by 24.3%. The metric of the metal perimeter may be applied to the model-based fill insertion methods, which will improve the planarity in the practical fill insertion flow.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127625213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450455
M. Kurimoto, Jun Matsushima, S. Ohbayashi, Yoshiaki Fukui
We propose a yield improvement methodology which repairs a faulty chip due to the logic defect by using a repairable scan flip-flop (R-SFF). Our methodology greatly improves an area penalty, which is a large issue for the logic repair technology in the actual products, by using a repair grouping and a redundant cell insertion algorithm, and by pushing the design rule for the repairable area of R-SFF. Besides, we reduce the number of wire connections around redundant cells compared with the conventional method, by improving the replacement method of the faulty cell by the redundant cell. The proposed methodology reduces total area penalty caused by the logic redundant repair to 3.6%, and improves the yield, that is the number of good chips on a wafer, by 4.7% when the defect density is 1.0[cm-2].
{"title":"A yield improvement methodology based on logic redundant repair with a repairable scan flip-flop designed by push rule","authors":"M. Kurimoto, Jun Matsushima, S. Ohbayashi, Yoshiaki Fukui","doi":"10.1109/ISQED.2010.5450455","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450455","url":null,"abstract":"We propose a yield improvement methodology which repairs a faulty chip due to the logic defect by using a repairable scan flip-flop (R-SFF). Our methodology greatly improves an area penalty, which is a large issue for the logic repair technology in the actual products, by using a repair grouping and a redundant cell insertion algorithm, and by pushing the design rule for the repairable area of R-SFF. Besides, we reduce the number of wire connections around redundant cells compared with the conventional method, by improving the replacement method of the faulty cell by the redundant cell. The proposed methodology reduces total area penalty caused by the logic redundant repair to 3.6%, and improves the yield, that is the number of good chips on a wafer, by 4.7% when the defect density is 1.0[cm-2].","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124677743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450414
Touqeer Azam, B. Cheng, D. Cumming
High variability in nano-scaled technologies can easily disturb the stability of a carefully designed standard 6T-SRAM cell, causing access failures during a read/write operation. We propose a 7T-SRAM cell to increase the read/write stability under large variations. The proposed design uses a low overhead read/write assist circuitry to increase the noise immunity. Use of an additional transistor and a floating ground allows read disturb free operation. While the write assist circuitry provides a floating ground during a write operation that weakens cell storage by turning off the supply voltage to ground path of the cross-coupled inverter pair. This allows a high speed/low power write operation. Monte Carlo simulations indicate a 200% increase in the read stability and a boost of 124% in write stability compared to a conventional 6T-SRAM design, when subjected to random dopant fluctuations, line edge roughness, and poly-granularity variations. HSPICE simulations of a 45nm 64×32 bit SRAM array designed using standard 6T and proposed 7T SRAM cells indicate a 31% improvement in write speed/write power, read power decreases by 60%, and a 44% reduction in the total average power consumption is achieved with the proposed design.
{"title":"Variability resilient low-power 7T-SRAM design for nano-scaled technologies","authors":"Touqeer Azam, B. Cheng, D. Cumming","doi":"10.1109/ISQED.2010.5450414","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450414","url":null,"abstract":"High variability in nano-scaled technologies can easily disturb the stability of a carefully designed standard 6T-SRAM cell, causing access failures during a read/write operation. We propose a 7T-SRAM cell to increase the read/write stability under large variations. The proposed design uses a low overhead read/write assist circuitry to increase the noise immunity. Use of an additional transistor and a floating ground allows read disturb free operation. While the write assist circuitry provides a floating ground during a write operation that weakens cell storage by turning off the supply voltage to ground path of the cross-coupled inverter pair. This allows a high speed/low power write operation. Monte Carlo simulations indicate a 200% increase in the read stability and a boost of 124% in write stability compared to a conventional 6T-SRAM design, when subjected to random dopant fluctuations, line edge roughness, and poly-granularity variations. HSPICE simulations of a 45nm 64×32 bit SRAM array designed using standard 6T and proposed 7T SRAM cells indicate a 31% improvement in write speed/write power, read power decreases by 60%, and a 44% reduction in the total average power consumption is achieved with the proposed design.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116714578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450535
Basab Datta, W. Burleson
Remarkable increase in peak power-density values coupled with the hotspot migration caused by workload variance motivates the need for multiple thermal monitoring circuits distributed across the die. The effect of intra-die process-variations on deep sub-micron circuits is significant enough to undermine their robustness. Accordingly, there is change in the response of thermal sensors occupying different process-corners which causes a shift in their calibration-constants. To save on tester cost, modern microprocessors employ a single, 2-point hard calibration model (slope-intercept form). In a multi-sensor environment, a single calibration equation will be rendered ineffective due to sparse sensor distribution that will be afflicted by varying degrees of process-variation. Thus, our aim is to estimate the process-induced drift in the calibration-constants of the thermal sensors. To this end, we propose a novel, supply and temperature independent, process-sensor which offers a high sensitivity of 3.35%/5mV variation in Vth and a low power consumption of 4–25nW. The process-estimates obtained are plugged into an analytical model used to describe the process-dependence of a ring-oscillator based thermal sensor and generate the process-shifted calibration constants. HSPICE simulations in 45nm indicate that in the presence of process-variations having 3-σ variability of +/−15% in all process-parameters, the average measurement error of a ring-oscillator-based thermal sensor with process-corrected calibration constants is reduced by ≫3X for slope and ≫10X for intercept as compared to one with static constants.
{"title":"Calibration of on-chip thermal sensors using process monitoring circuits","authors":"Basab Datta, W. Burleson","doi":"10.1109/ISQED.2010.5450535","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450535","url":null,"abstract":"Remarkable increase in peak power-density values coupled with the hotspot migration caused by workload variance motivates the need for multiple thermal monitoring circuits distributed across the die. The effect of intra-die process-variations on deep sub-micron circuits is significant enough to undermine their robustness. Accordingly, there is change in the response of thermal sensors occupying different process-corners which causes a shift in their calibration-constants. To save on tester cost, modern microprocessors employ a single, 2-point hard calibration model (slope-intercept form). In a multi-sensor environment, a single calibration equation will be rendered ineffective due to sparse sensor distribution that will be afflicted by varying degrees of process-variation. Thus, our aim is to estimate the process-induced drift in the calibration-constants of the thermal sensors. To this end, we propose a novel, supply and temperature independent, process-sensor which offers a high sensitivity of 3.35%/5mV variation in Vth and a low power consumption of 4–25nW. The process-estimates obtained are plugged into an analytical model used to describe the process-dependence of a ring-oscillator based thermal sensor and generate the process-shifted calibration constants. HSPICE simulations in 45nm indicate that in the presence of process-variations having 3-σ variability of +/−15% in all process-parameters, the average measurement error of a ring-oscillator-based thermal sensor with process-corrected calibration constants is reduced by ≫3X for slope and ≫10X for intercept as compared to one with static constants.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126221313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450549
W. Xu, Tong Zhang
Because of its great scalability potential and support of multi-level per cell storage, phase change memory has become a topic of great current interest. However, recent studies show that structural relaxation effect makes the resistance of phase change material drift over the time, which can severely degrade multi-level phase change memory storage reliability. This paper studies the potential of using a time-aware memory sensing strategy to address this challenge. The basic idea is to keep track of memory content lifetime and, when memory is being read, accordingly adjust the memory sensing configuration to minimize the negative impact of time-dependent resistance drift on memory storage reliability. Because multi-level phase change memory may demand the use of powerful error correction code (ECC) whose decoding can request either hard-decision or soft-decision log-likelihood (LLR) memory sensing, we discuss both hard-decision and soft-decision time-aware memory sensing in details. Using BCH code and LDPC code as ECC for 4-level/cell and 8-level/cell phase change memory, we carry out simulations and the results show that, compared with time-independent static memory sensing, time-aware memory sensing can increase allowable memory content lifetime by several orders of magnitude.
{"title":"Using time-aware memory sensing to address resistance drift issue in multi-level phase change memory","authors":"W. Xu, Tong Zhang","doi":"10.1109/ISQED.2010.5450549","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450549","url":null,"abstract":"Because of its great scalability potential and support of multi-level per cell storage, phase change memory has become a topic of great current interest. However, recent studies show that structural relaxation effect makes the resistance of phase change material drift over the time, which can severely degrade multi-level phase change memory storage reliability. This paper studies the potential of using a time-aware memory sensing strategy to address this challenge. The basic idea is to keep track of memory content lifetime and, when memory is being read, accordingly adjust the memory sensing configuration to minimize the negative impact of time-dependent resistance drift on memory storage reliability. Because multi-level phase change memory may demand the use of powerful error correction code (ECC) whose decoding can request either hard-decision or soft-decision log-likelihood (LLR) memory sensing, we discuss both hard-decision and soft-decision time-aware memory sensing in details. Using BCH code and LDPC code as ECC for 4-level/cell and 8-level/cell phase change memory, we carry out simulations and the results show that, compared with time-independent static memory sensing, time-aware memory sensing can increase allowable memory content lifetime by several orders of magnitude.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128459653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450500
Shirish Bahirat, S. Pasricha
Multiple use-case chip multiprocessor (CMP) applications require adaptive on-chip communication fabrics to cope with changing use-case performance needs. Networks-on-chip (NoC) have recently gained popularity as scalable and adaptive on-chip communication fabrics, but suffer from prohibitive power dissipation. In this paper we propose UCPHOTON, a novel hybrid photonic NoC communication architecture optimized to cope with the variable bandwidth and latency constraints of multiple use-case applications implemented on CMPs. Our detailed experimental results indicate that UC-PHOTON can effectively adapt to meet diverse use-case traffic requirements and optimize energy-delay product and power dissipation, with scaling CMP core count and multiple use-case complexity. For the five multiple use-case applications explored in this work, UC-PHOTON shows up to 46× reduction in power dissipation and up to 170× reduction in energy-delay product compared to traditional electrical NoC fabrics, highlighting the benefits of using the novel communication fabric.
{"title":"UC-PHOTON: A novel hybrid photonic network-on-chip for multiple use-case applications","authors":"Shirish Bahirat, S. Pasricha","doi":"10.1109/ISQED.2010.5450500","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450500","url":null,"abstract":"Multiple use-case chip multiprocessor (CMP) applications require adaptive on-chip communication fabrics to cope with changing use-case performance needs. Networks-on-chip (NoC) have recently gained popularity as scalable and adaptive on-chip communication fabrics, but suffer from prohibitive power dissipation. In this paper we propose UCPHOTON, a novel hybrid photonic NoC communication architecture optimized to cope with the variable bandwidth and latency constraints of multiple use-case applications implemented on CMPs. Our detailed experimental results indicate that UC-PHOTON can effectively adapt to meet diverse use-case traffic requirements and optimize energy-delay product and power dissipation, with scaling CMP core count and multiple use-case complexity. For the five multiple use-case applications explored in this work, UC-PHOTON shows up to 46× reduction in power dissipation and up to 170× reduction in energy-delay product compared to traditional electrical NoC fabrics, highlighting the benefits of using the novel communication fabric.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134033754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450512
Wenxu Sheng, Sheqin Dong, Yuliang Wu, S. Goto
Modern hierarchical SOC design flows need to deal with fixed-outline floorplanning under the interconnect constraints, in this paper, we address the problem of bus driven floorplanning in a fixed-outline area. Given a set of blocks, the bus specification, and the height and width of the chip area, a floorplan solution including bus routes and satisfying the outline constraint will be generated with the total floorplan area and total bus area minimized. The approach proposed in this paper is based on a deterministic algorithm Less Flexibility First (LFF), which runs in a fixed-outline area and packs hard blocks one after another with no drawbacks. In our approach, we put no limitation to the shape of the buses, and the processes block-packing and bus-packing are proceeding simultaneously. Experiment results show that under the constraint of fixed-outline, we can also obtain a good solution, with less dead space percentage and shorter run time, besides, for large test cases, our algorithm still works well.
{"title":"Fixed outline multi-bend bus driven floorplanning","authors":"Wenxu Sheng, Sheqin Dong, Yuliang Wu, S. Goto","doi":"10.1109/ISQED.2010.5450512","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450512","url":null,"abstract":"Modern hierarchical SOC design flows need to deal with fixed-outline floorplanning under the interconnect constraints, in this paper, we address the problem of bus driven floorplanning in a fixed-outline area. Given a set of blocks, the bus specification, and the height and width of the chip area, a floorplan solution including bus routes and satisfying the outline constraint will be generated with the total floorplan area and total bus area minimized. The approach proposed in this paper is based on a deterministic algorithm Less Flexibility First (LFF), which runs in a fixed-outline area and packs hard blocks one after another with no drawbacks. In our approach, we put no limitation to the shape of the buses, and the processes block-packing and bus-packing are proceeding simultaneously. Experiment results show that under the constraint of fixed-outline, we can also obtain a good solution, with less dead space percentage and shorter run time, besides, for large test cases, our algorithm still works well.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134304372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450515
S K Nithin, G. Shanmugam, S. Chandrasekar
Dynamic voltage (IR) drop, unlike the static voltage drop depends on the switching activity of the design, and hence it is vector dependent. In this paper we have highlighted the pitfalls in the common design closure methodology that addresses static IR drop well, but often fails to bound the impact of dynamic voltage drops robustly. Factors that can affect the accuracy of dynamic IR analysis and the related metrics for design closure are discussed. A structured approach to planning the power distribution and grid for power managed designs is then presented, with an emphasis to cover realistic application scenarios, and how it can be done early in the design cycle. Care-about and solutions to avoid and fix the Dynamic voltage drop issues are also presented. Results are from industrial designs in 45nm process are presented related to the said topics.
{"title":"Dynamic voltage (IR) drop analysis and design closure: Issues and challenges","authors":"S K Nithin, G. Shanmugam, S. Chandrasekar","doi":"10.1109/ISQED.2010.5450515","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450515","url":null,"abstract":"Dynamic voltage (IR) drop, unlike the static voltage drop depends on the switching activity of the design, and hence it is vector dependent. In this paper we have highlighted the pitfalls in the common design closure methodology that addresses static IR drop well, but often fails to bound the impact of dynamic voltage drops robustly. Factors that can affect the accuracy of dynamic IR analysis and the related metrics for design closure are discussed. A structured approach to planning the power distribution and grid for power managed designs is then presented, with an emphasis to cover realistic application scenarios, and how it can be done early in the design cycle. Care-about and solutions to avoid and fix the Dynamic voltage drop issues are also presented. Results are from industrial designs in 45nm process are presented related to the said topics.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132602964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450484
Yongpan Liu, Yinan Sun, Yihao Zhu, Huazhong Yang
Increasing circuit delay range due to process variations, temperature and voltage fluctuations and input characterization makes the traditional worst-case fault-avoidance design methodology no longer sustainable. As an alternative, the average-case fault-detection design methodology is generating interest. Among existing solutions, function speculation design with error recovery mechanisms is quite promising due to its high performance and low area overhead. Previous work had focused on two-stage function speculation and thus lacked a systematic way to address the challenge of the multistage function speculation approach. For the first time, this paper proposes a multistage function speculation structure and applies it in a novel adder. We deduced the analytical performance and area models for the design and validated them in our experiments. Based on those models, a general methodology is presented to guide design optimization. Both analytical proofs and experimental results show that the proposed adder's delay and area has a logarithmic and linear relationship with its bit number,respectively. Compared with the DesignWare IP, the proposed adder provides the same performance with 6–16% area reductions under different bit number configurations.
{"title":"Design methodology of variable latency adders with multistage function speculation","authors":"Yongpan Liu, Yinan Sun, Yihao Zhu, Huazhong Yang","doi":"10.1109/ISQED.2010.5450484","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450484","url":null,"abstract":"Increasing circuit delay range due to process variations, temperature and voltage fluctuations and input characterization makes the traditional worst-case fault-avoidance design methodology no longer sustainable. As an alternative, the average-case fault-detection design methodology is generating interest. Among existing solutions, function speculation design with error recovery mechanisms is quite promising due to its high performance and low area overhead. Previous work had focused on two-stage function speculation and thus lacked a systematic way to address the challenge of the multistage function speculation approach. For the first time, this paper proposes a multistage function speculation structure and applies it in a novel adder. We deduced the analytical performance and area models for the design and validated them in our experiments. Based on those models, a general methodology is presented to guide design optimization. Both analytical proofs and experimental results show that the proposed adder's delay and area has a logarithmic and linear relationship with its bit number,respectively. Compared with the DesignWare IP, the proposed adder provides the same performance with 6–16% area reductions under different bit number configurations.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129351447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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