Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450439
Chia-Yi Lin, Hung-Ming Chen
This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many long scan chain switching activities. Based on two-dimensional scan shift control, we can achieve low test power with simple and small overhead structure. The proposed scheme skips many unnecessary don't care (X) patterns to reduce the test data volume and test time. The experimental results of the proposed scheme illustrate the significant improvement in shift power reduction, test volume and test time reduction. Compared with traditional single scan chain design, the large benchmark b17 of ITC'99 has over 50% reduction in test data volume and over 40% reduction in test time with little area overhead and very few extra pins, and the power reduction is over 97%.
{"title":"A novel two-dimensional scan-control scheme for test-cost reduction","authors":"Chia-Yi Lin, Hung-Ming Chen","doi":"10.1109/ISQED.2010.5450439","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450439","url":null,"abstract":"This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many long scan chain switching activities. Based on two-dimensional scan shift control, we can achieve low test power with simple and small overhead structure. The proposed scheme skips many unnecessary don't care (X) patterns to reduce the test data volume and test time. The experimental results of the proposed scheme illustrate the significant improvement in shift power reduction, test volume and test time reduction. Compared with traditional single scan chain design, the large benchmark b17 of ITC'99 has over 50% reduction in test data volume and over 40% reduction in test time with little area overhead and very few extra pins, and the power reduction is over 97%.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132380777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450529
J. Ferguson, S. Koranne, D. Abercrombie
Intellectual property (IP) blocks often contain known design rule checking errors that have been “waived” by the foundry, meaning they acknowledge the error as a design rule violation, but do not consider it to be a critical yield-limiting defect. Because this waiver information is not conveyed in any consistent manner with the IP, waived IP design rule violations that reappear when the IP is integrated into a full-chip design must typically be investigated as though they are new violations. This paper will review various historic methods used to identify waived errors at the chip level, then propose a new automated method for identifying and eliminating waived errors, allowing chip designers to achieve accurate design rule checking results while minimizing debug time.
{"title":"An innovative method to automate the waiver of IP-level DRC violations","authors":"J. Ferguson, S. Koranne, D. Abercrombie","doi":"10.1109/ISQED.2010.5450529","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450529","url":null,"abstract":"Intellectual property (IP) blocks often contain known design rule checking errors that have been “waived” by the foundry, meaning they acknowledge the error as a design rule violation, but do not consider it to be a critical yield-limiting defect. Because this waiver information is not conveyed in any consistent manner with the IP, waived IP design rule violations that reappear when the IP is integrated into a full-chip design must typically be investigated as though they are new violations. This paper will review various historic methods used to identify waived errors at the chip level, then propose a new automated method for identifying and eliminating waived errors, allowing chip designers to achieve accurate design rule checking results while minimizing debug time.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122210492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450538
Jinhui Wang, Wu-chen Wu, Na Gong, L. Hou
Using both the modified supply voltage and body voltage, an optimized keeper technique is presented in this paper to tradeoff the performance of domino OR gates. The simulation results show that the novel technique can highly improve power/speed efficiency and robustness to noise. In addition, because of employment of body biased voltage, the optimized keeper technique enables to minimize effect of the strong process parameter variation.
{"title":"Domino gate with modified voltage keeper","authors":"Jinhui Wang, Wu-chen Wu, Na Gong, L. Hou","doi":"10.1109/ISQED.2010.5450538","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450538","url":null,"abstract":"Using both the modified supply voltage and body voltage, an optimized keeper technique is presented in this paper to tradeoff the performance of domino OR gates. The simulation results show that the novel technique can highly improve power/speed efficiency and robustness to noise. In addition, because of employment of body biased voltage, the optimized keeper technique enables to minimize effect of the strong process parameter variation.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115406174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450531
M. Meijer, J. P. D. Gyvez
Worst-case design uses extreme process corner conditions which rarely occur. This costs additional power due to area over-dimensioning during synthesis. We present a new design strategy for digital CMOS IP that makes use of forward body biasing. Our approach renders consistently a better performance-per-area ratio by constraining circuit over-dimensioning without sacrificing circuit performance. Dynamic power is reduced depending upon the ratio of flip-flops to logic-gates, and data activity. On a set of benchmark circuits in 65nm LP-CMOS, we observed performance-per-area improvements up to 81%, area and leakage reductions up to 38%, and total power savings of up to 26% without performance penalties.
{"title":"Body bias driven design synthesis for optimum performance per area","authors":"M. Meijer, J. P. D. Gyvez","doi":"10.1109/ISQED.2010.5450531","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450531","url":null,"abstract":"Worst-case design uses extreme process corner conditions which rarely occur. This costs additional power due to area over-dimensioning during synthesis. We present a new design strategy for digital CMOS IP that makes use of forward body biasing. Our approach renders consistently a better performance-per-area ratio by constraining circuit over-dimensioning without sacrificing circuit performance. Dynamic power is reduced depending upon the ratio of flip-flops to logic-gates, and data activity. On a set of benchmark circuits in 65nm LP-CMOS, we observed performance-per-area improvements up to 81%, area and leakage reductions up to 38%, and total power savings of up to 26% without performance penalties.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"28 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114127414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450447
Yiran Chen, Wei Tian, Hai Helen Li, Xiaobin Wang, Wenzhong Zhu
This work systematically explores the relationship between the resistive switching properties of Pr0.7Ca0.3MnO3 (PCMO) thin film element and its geometry dimensions in deep submicron (DSM) technologies. A series of PCMO-based resistive switch devices (RSDs) with different geometry sizes were fabricated. Our E-test results show that by reducing the PCMO layer thickness from the normal value of about 200nm to 30nm, a low switching voltage (within ±2.5V) can be achieved. The reduction of PCMO layer thickness does not incur visible impact on device reliability: no significant degradation of two resistance states was observed after 1500 programming cycles. Based on the extrapolation from the measured electrical parameters of PCMO-based devices, we analyzed the design requirements of PCMO-based resistive memory with different cell structures in sub-100nm technologies. Our simulations show that one-transistor-one-RSD (1T1R) cell structure can be successfully scaled down to 22nm technology node. However, the scaling of one-non-ohmicdevice-one-RSD (1N1R) cell structure is significantly limited by the low driving ability of current non-ohmic device technology.
{"title":"Scalability of PCMO-based resistive switch device in DSM technologies","authors":"Yiran Chen, Wei Tian, Hai Helen Li, Xiaobin Wang, Wenzhong Zhu","doi":"10.1109/ISQED.2010.5450447","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450447","url":null,"abstract":"This work systematically explores the relationship between the resistive switching properties of Pr0.7Ca0.3MnO3 (PCMO) thin film element and its geometry dimensions in deep submicron (DSM) technologies. A series of PCMO-based resistive switch devices (RSDs) with different geometry sizes were fabricated. Our E-test results show that by reducing the PCMO layer thickness from the normal value of about 200nm to 30nm, a low switching voltage (within ±2.5V) can be achieved. The reduction of PCMO layer thickness does not incur visible impact on device reliability: no significant degradation of two resistance states was observed after 1500 programming cycles. Based on the extrapolation from the measured electrical parameters of PCMO-based devices, we analyzed the design requirements of PCMO-based resistive memory with different cell structures in sub-100nm technologies. Our simulations show that one-transistor-one-RSD (1T1R) cell structure can be successfully scaled down to 22nm technology node. However, the scaling of one-non-ohmicdevice-one-RSD (1N1R) cell structure is significantly limited by the low driving ability of current non-ohmic device technology.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"106 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120932374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450401
Kwangok Jeong, A. Kahng, Seokhyeong Kang
Timing exceptions in IC implementation processes, especially timing verification, help reduce pessimism that arises from unnecessary timing constraints by masking non-functional critical paths. Ideally, timing exceptions should always be helpful for quality of results (QOR) metrics such as area or number of timing violations, and for design turnaround time (TAT) metrics such as tool runtime and number of design iterations.We expect this positive impact since timing exceptions reduce the number of constraints that the design optimization must satisfy.
{"title":"Toward effective utilization of timing exceptions in design optimization","authors":"Kwangok Jeong, A. Kahng, Seokhyeong Kang","doi":"10.1109/ISQED.2010.5450401","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450401","url":null,"abstract":"Timing exceptions in IC implementation processes, especially timing verification, help reduce pessimism that arises from unnecessary timing constraints by masking non-functional critical paths. Ideally, timing exceptions should always be helpful for quality of results (QOR) metrics such as area or number of timing violations, and for design turnaround time (TAT) metrics such as tool runtime and number of design iterations.We expect this positive impact since timing exceptions reduce the number of constraints that the design optimization must satisfy.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116311681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450513
Rajeev K. Nain, Shantesh Pinge, M. Chrzanowska-Jeske
Through signal vias (TSVs) in 3D ICs suffer from thermo-mechanical stress, and may fail or attain plasticity resulting in significant yield loss. We present a novel set of strategies for yield improvement in the presence of defects in through signal vias in heterogeneous 3D system-on-chip. Monte-Carlo simulation results show that our strategy can improve the yield of 3D ICs significantly. Furthermore, we estimate the parametric yield and present a quantitative analysis of the impact of our approach on chip area, power, performance and chip revenue that can improve profitability. Our results suggest that the proposed strategies can be very useful in yield-aware 3D design.
{"title":"Yield improvement of 3D ICs in the presence of defects in through signal vias","authors":"Rajeev K. Nain, Shantesh Pinge, M. Chrzanowska-Jeske","doi":"10.1109/ISQED.2010.5450513","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450513","url":null,"abstract":"Through signal vias (TSVs) in 3D ICs suffer from thermo-mechanical stress, and may fail or attain plasticity resulting in significant yield loss. We present a novel set of strategies for yield improvement in the presence of defects in through signal vias in heterogeneous 3D system-on-chip. Monte-Carlo simulation results show that our strategy can improve the yield of 3D ICs significantly. Furthermore, we estimate the parametric yield and present a quantitative analysis of the impact of our approach on chip area, power, performance and chip revenue that can improve profitability. Our results suggest that the proposed strategies can be very useful in yield-aware 3D design.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128328192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450470
G. Thakral, S. Mohanty, D. Ghai, D. Pradhan
In this paper, a novel design flow is presented for simultaneous P3 (power minimization, performance maximization and process variation tolerance) optimization of nano-CMOS circuits. For demonstration of the effectiveness of the flow, a 45nm single-ended 7-transistor SRAM is used as example circuit. The SRAM cell is subjected to a dual-VTh assignment based on a novel statistical Design of Experiments-Integer Linear Programming (DOE-ILP) approach. Experimental results show 44.2% power reduction (including leakage) and 43.9% increase in the read static noise margin compared to the baseline design. The process variation analysis of the optimized cell is carried out considering the variability effect in 12 device parameters. A 8 × 8 array is constructed to show the feasibility of the proposed SRAM cell. To the best of the authors' knowledge, this is the first study which makes use of statistical Design of Experiments and Integer Linear Programming for optimization of conflicting targets of stability, power in the presence of process variations in an SRAM cell.
{"title":"P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP","authors":"G. Thakral, S. Mohanty, D. Ghai, D. Pradhan","doi":"10.1109/ISQED.2010.5450470","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450470","url":null,"abstract":"In this paper, a novel design flow is presented for simultaneous P3 (power minimization, performance maximization and process variation tolerance) optimization of nano-CMOS circuits. For demonstration of the effectiveness of the flow, a 45nm single-ended 7-transistor SRAM is used as example circuit. The SRAM cell is subjected to a dual-VTh assignment based on a novel statistical Design of Experiments-Integer Linear Programming (DOE-ILP) approach. Experimental results show 44.2% power reduction (including leakage) and 43.9% increase in the read static noise margin compared to the baseline design. The process variation analysis of the optimized cell is carried out considering the variability effect in 12 device parameters. A 8 × 8 array is constructed to show the feasibility of the proposed SRAM cell. To the best of the authors' knowledge, this is the first study which makes use of statistical Design of Experiments and Integer Linear Programming for optimization of conflicting targets of stability, power in the presence of process variations in an SRAM cell.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125425943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450543
M. Gao, Zuochang Ye, Yao Peng, Yan Wang, Zhiping Yu
Gate delay models taking process variation into account are an essential part of ascendant statistical static timing analysis (SSTA). The statistical gate delay models in being, most of which take the forms of low order polynomials, are suffering from either enormous characterization cost or poor accuracy. We propose in this paper a statistical comprehensive gate delay model including both the effects of process variation and operating conditions, i.e. input slope and output load. With the help of effective dimension reduction, we can use only a couple of random variables to present the effect of process variation, which enables a simple modeling methodology as well as a cheap characterization process. This model can be changed into the polynomial forms required in some block based SSTA or directly used in Monte Carlo based SSTA. The error of the model is shown well below 5% compared with golden Monte Carlo data.
{"title":"A comprehensive model for gate delay under process variation and different driving and loading conditions","authors":"M. Gao, Zuochang Ye, Yao Peng, Yan Wang, Zhiping Yu","doi":"10.1109/ISQED.2010.5450543","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450543","url":null,"abstract":"Gate delay models taking process variation into account are an essential part of ascendant statistical static timing analysis (SSTA). The statistical gate delay models in being, most of which take the forms of low order polynomials, are suffering from either enormous characterization cost or poor accuracy. We propose in this paper a statistical comprehensive gate delay model including both the effects of process variation and operating conditions, i.e. input slope and output load. With the help of effective dimension reduction, we can use only a couple of random variables to present the effect of process variation, which enables a simple modeling methodology as well as a cheap characterization process. This model can be changed into the polynomial forms required in some block based SSTA or directly used in Monte Carlo based SSTA. The error of the model is shown well below 5% compared with golden Monte Carlo data.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123111616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-22DOI: 10.1109/ISQED.2010.5450552
Jeremy R. Tolbert, Pratik Kabali, Simeranjit Brar, S. Mukhopadhyay
Remote wireless monitoring of physiological signals has emerged as a key enabler for biotelemetry and can significantly improve the delivery of healthcare. Improving the energy-efficiency and battery-lifetime of the monitoring units without sacrificing the acquired signal quality is a key challenge in large-scale deployment of bio-electronic systems for remote wireless monitoring. In this paper, we present a design methodology for low power wireless monitoring of Electroencephalography (EEG) data. The proposed design performs a real-time accuracy energy trade-off by controlling the volume of transmitted data based on the information content in the EEG signal. We consider the effect of different system parameters in order to design an optimal system. Our analysis shows that the proposed system design approach can provide significant savings in transmitter power with minimal impact on the monitored EEG signal accuracy. We analyze the impact of noise of the wireless channel and show that an adaptive compression system has better performance for BER ≪ 10−4.
{"title":"A low power system with adaptive data compression for wireless monitoring of physiological signals and its application to wireless electroencephalography","authors":"Jeremy R. Tolbert, Pratik Kabali, Simeranjit Brar, S. Mukhopadhyay","doi":"10.1109/ISQED.2010.5450552","DOIUrl":"https://doi.org/10.1109/ISQED.2010.5450552","url":null,"abstract":"Remote wireless monitoring of physiological signals has emerged as a key enabler for biotelemetry and can significantly improve the delivery of healthcare. Improving the energy-efficiency and battery-lifetime of the monitoring units without sacrificing the acquired signal quality is a key challenge in large-scale deployment of bio-electronic systems for remote wireless monitoring. In this paper, we present a design methodology for low power wireless monitoring of Electroencephalography (EEG) data. The proposed design performs a real-time accuracy energy trade-off by controlling the volume of transmitted data based on the information content in the EEG signal. We consider the effect of different system parameters in order to design an optimal system. Our analysis shows that the proposed system design approach can provide significant savings in transmitter power with minimal impact on the monitored EEG signal accuracy. We analyze the impact of noise of the wireless channel and show that an adaptive compression system has better performance for BER ≪ 10−4.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126860725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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