Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268381
A. Makarov, S. Tyaginov, B. Kaczer, M. Jech, A. Chasin, A. Grill, G. Hellings, M. Vexler, D. Linten, T. Grasser
We perform a comprehensive analysis of hot-carrier degradation (HCD) in FinFETs. To accomplish this goal we employ our physics-based HCD model and validate it against experimental data acquired in n-FinFETs with a channel length of 28 nm. We use this verified model to study the distribution of the trap density across the fin/stack interface. The methodology is applied to analyze the effect of transistor architectural parameters, namely fin length, width, and height, on HCD. Our results show that at the same conditions HCD becomes more severe in shorter devices and in transistors with wider fins, while the impact of the fin height on the damage is weak. Finally we demonstrate that a proper HCD description can be achieved only with a physics-based model.
{"title":"Hot-carrier degradation in FinFETs: Modeling, peculiarities, and impact of device topology","authors":"A. Makarov, S. Tyaginov, B. Kaczer, M. Jech, A. Chasin, A. Grill, G. Hellings, M. Vexler, D. Linten, T. Grasser","doi":"10.1109/IEDM.2017.8268381","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268381","url":null,"abstract":"We perform a comprehensive analysis of hot-carrier degradation (HCD) in FinFETs. To accomplish this goal we employ our physics-based HCD model and validate it against experimental data acquired in n-FinFETs with a channel length of 28 nm. We use this verified model to study the distribution of the trap density across the fin/stack interface. The methodology is applied to analyze the effect of transistor architectural parameters, namely fin length, width, and height, on HCD. Our results show that at the same conditions HCD becomes more severe in shorter devices and in transistors with wider fins, while the impact of the fin height on the damage is weak. Finally we demonstrate that a proper HCD description can be achieved only with a physics-based model.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129863861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268476
S. Narasimha, B. Jagannathan, A. Ogino, D. Jaeger, B. Greene, C. Sheraw, K. Zhao, B. Haran, U. Kwon, A. Mahalingam, B. Kannan, B. Morganfeld, J. Dechene, C. Radens, A. Tessier, A. Hassan, H. Narisetty, I. Ahsan, M. Aminpur, C. An, M. Aquilino, A. Arya, R. Augur, N. Baliga, R. Bhelkar, G. Biery, A. Blauberg, N. Borjemscaia, A. Bryant, L. Cao, V. Chauhan, M. Chen, L. Cheng, J. Choo, C. Christiansen, T. Chu, B. Cohen, R. Coleman, D. Conklin, S. Crown, A. da Silva, D. Dechene, G. Derderian, S. Deshpande, G. Dilliway, K. Donegan, M. Eller, Y. Fan, Q. Fang, A. Gassaria, R. Gauthier, S. Ghosh, G. Gifford, T. Gordon, M. Gribelyuk, G. Han, J.H. Han, K. Han, M. Hasan, J. Higman, J. Holt, L. Hu, L. Huang, C. Huang, T. Hung, Y. Jin, J. Johnson, S. Johnson, V. Joshi, M. Joshi, P. Justison, S. Kalaga, T. Kim, W. Kim, R. Krishnan, B. Krishnan, K. Anil, M. Kumar, J. Lee, R. Lee, J. Lemon, S. L. Liew, P. Lindo, M. Lingalugari, M. Lipinski, P. Liu, J. Liu, S. Lucarini, W. Ma, E. Maciejewski, S. Madisetti, A. Malinowski, J.
We present a fully integrated 7nm CMOS platform featuring a 3rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization. This technology reflects an improvement of 2.8X routed logic density and >40% performance over the 14nm reference technology described in [1-3]. A full range of Vts is enabled on-chip through a unique multi-workfunction process. This enables both excellent low voltage SRAM response and highly scaled memory area simultaneously. The HD 6-T bitcell size is 0.0269um2. This 7nm technology is fully enabled by immersion lithography and advanced optical patterning techniques (like SAQP and SADP). However, the technology platform is also designed to leverage EUV insertion for specific multi-patterned (MP) levels for cycle time benefit and manufacturing efficiency. A complete set of foundation and complex IP is available in this advanced CMOS platform to enable both High Performance Compute (HPC) and mobile applications.
{"title":"A 7nm CMOS technology platform for mobile and high performance compute application","authors":"S. Narasimha, B. Jagannathan, A. Ogino, D. Jaeger, B. Greene, C. Sheraw, K. Zhao, B. Haran, U. Kwon, A. Mahalingam, B. Kannan, B. Morganfeld, J. Dechene, C. Radens, A. Tessier, A. Hassan, H. Narisetty, I. Ahsan, M. Aminpur, C. An, M. Aquilino, A. Arya, R. Augur, N. Baliga, R. Bhelkar, G. Biery, A. Blauberg, N. Borjemscaia, A. Bryant, L. Cao, V. Chauhan, M. Chen, L. Cheng, J. Choo, C. Christiansen, T. Chu, B. Cohen, R. Coleman, D. Conklin, S. Crown, A. da Silva, D. Dechene, G. Derderian, S. Deshpande, G. Dilliway, K. Donegan, M. Eller, Y. Fan, Q. Fang, A. Gassaria, R. Gauthier, S. Ghosh, G. Gifford, T. Gordon, M. Gribelyuk, G. Han, J.H. Han, K. Han, M. Hasan, J. Higman, J. Holt, L. Hu, L. Huang, C. Huang, T. Hung, Y. Jin, J. Johnson, S. Johnson, V. Joshi, M. Joshi, P. Justison, S. Kalaga, T. Kim, W. Kim, R. Krishnan, B. Krishnan, K. Anil, M. Kumar, J. Lee, R. Lee, J. Lemon, S. L. Liew, P. Lindo, M. Lingalugari, M. Lipinski, P. Liu, J. Liu, S. Lucarini, W. Ma, E. Maciejewski, S. Madisetti, A. Malinowski, J.","doi":"10.1109/IEDM.2017.8268476","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268476","url":null,"abstract":"We present a fully integrated 7nm CMOS platform featuring a 3rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization. This technology reflects an improvement of 2.8X routed logic density and >40% performance over the 14nm reference technology described in [1-3]. A full range of Vts is enabled on-chip through a unique multi-workfunction process. This enables both excellent low voltage SRAM response and highly scaled memory area simultaneously. The HD 6-T bitcell size is 0.0269um2. This 7nm technology is fully enabled by immersion lithography and advanced optical patterning techniques (like SAQP and SADP). However, the technology platform is also designed to leverage EUV insertion for specific multi-patterned (MP) levels for cycle time benefit and manufacturing efficiency. A complete set of foundation and complex IP is available in this advanced CMOS platform to enable both High Performance Compute (HPC) and mobile applications.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124547111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268307
A. Ionescu
In this paper we will present and discuss some of the great research challenges and opportunities related to 21st century energy efficient computing and sensing devices and systems, in the context of the Internet of Things (IoT) revolution. In the future, major innovations will require holistic approaches encompassing silicon and cloud technologies and will be centered on big/abundant data and context. There is still an important role to be played by innovations in energy efficient technologies, devices, and system design, building on the success of silicon CMOS. The predicted future global amounts of stored, computed, communicated, and sensed information will certainly challenge the world capability to process and make sense of zettabytes of data, requiring orders of magnitude improvements in energy efficiency.
{"title":"Energy efficient computing and sensing in the Zettabyte era: From silicon to the cloud","authors":"A. Ionescu","doi":"10.1109/IEDM.2017.8268307","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268307","url":null,"abstract":"In this paper we will present and discuss some of the great research challenges and opportunities related to 21st century energy efficient computing and sensing devices and systems, in the context of the Internet of Things (IoT) revolution. In the future, major innovations will require holistic approaches encompassing silicon and cloud technologies and will be centered on big/abundant data and context. There is still an important role to be played by innovations in energy efficient technologies, devices, and system design, building on the success of silicon CMOS. The predicted future global amounts of stored, computed, communicated, and sensed information will certainly challenge the world capability to process and make sense of zettabytes of data, requiring orders of magnitude improvements in energy efficiency.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124576577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268404
Sara Pellegrini, Bruce Rae, A. Pingault, D. Golanski, S. Jouan, C. Lapeyre, B. Mamdy
We present the first mature SPAD device in advanced 40 nm technology. For the first time we also show dedicated microlens fabrication on top of SPADs integrated in the same technology node. A high fill factor >70% is reported together with a low DCR median of 50cps at room temperature and a high PDP of 5% at 840nm. By taking advantage of the small digital node, a larger amount of logic can be integrated inside the pixel, which is ready to be ported to a 3D stacked technology, where the logic is implemented in a fully digital dedicated layer [1].
{"title":"Industrialised SPAD in 40 nm technology","authors":"Sara Pellegrini, Bruce Rae, A. Pingault, D. Golanski, S. Jouan, C. Lapeyre, B. Mamdy","doi":"10.1109/IEDM.2017.8268404","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268404","url":null,"abstract":"We present the first mature SPAD device in advanced 40 nm technology. For the first time we also show dedicated microlens fabrication on top of SPADs integrated in the same technology node. A high fill factor >70% is reported together with a low DCR median of 50cps at room temperature and a high PDP of 5% at 840nm. By taking advantage of the small digital node, a larger amount of logic can be integrated inside the pixel, which is ready to be ported to a 3D stacked technology, where the logic is implemented in a fully digital dedicated layer [1].","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121251821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268354
Ayaz Ali, Khurram Shehzad, Hongwei Guo, Zhen Wang, Peng Wang, Akeel Qadir, Weida Hu, Tianling Ren, Bin Yu, Yang Xu
We report a high-performance graphene/ultra-thin silicon metal-semiconductor-metal (MSM) ultraviolet (UV) photodetector, which benefits from the mechanical flexibility and high-percentage visible light rejection of ultra-thin silicon. In the near- and mid-UV spectral region, the proposed UV photodetector exhibits high photo-responsivity (0.47 A/W @ 3 V), fast time response (1 ps), high specific detectivity (2.5 × 1010 Jones), and UV/Vis rejection ratio of about 100, comparable to the state-of-the-art GaN and SiC Schottky photodetectors. The photodetector is semi-transparent, and its performance is stable after 1,000 bending cycles. Furthermore, we demonstrated UV imaging by replacing CCD array with the proposed graphene/silicon image sensor in a custom-designed digital camera.
{"title":"High-performance, flexible graphene/ultra-thin silicon ultra-violet image sensor","authors":"Ayaz Ali, Khurram Shehzad, Hongwei Guo, Zhen Wang, Peng Wang, Akeel Qadir, Weida Hu, Tianling Ren, Bin Yu, Yang Xu","doi":"10.1109/IEDM.2017.8268354","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268354","url":null,"abstract":"We report a high-performance graphene/ultra-thin silicon metal-semiconductor-metal (MSM) ultraviolet (UV) photodetector, which benefits from the mechanical flexibility and high-percentage visible light rejection of ultra-thin silicon. In the near- and mid-UV spectral region, the proposed UV photodetector exhibits high photo-responsivity (0.47 A/W @ 3 V), fast time response (1 ps), high specific detectivity (2.5 × 1010 Jones), and UV/Vis rejection ratio of about 100, comparable to the state-of-the-art GaN and SiC Schottky photodetectors. The photodetector is semi-transparent, and its performance is stable after 1,000 bending cycles. Furthermore, we demonstrated UV imaging by replacing CCD array with the proposed graphene/silicon image sensor in a custom-designed digital camera.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114633294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268334
Chenguang Qiu, Zhiyong Zhang, Lianmao Peng
Owing to its ultra-thin body and high carrier mobility, semiconducting carbon nanotube (CNT) has been considered as an ideal channel material for future field-effect transistors (FETs) with sub 10 nm channel length. With well-designed device structure and when combined with graphene, we demonstrated high performance top-gated CNT FETs with gate length scaled down to 5nm. Scaling trend study reveals that sub-10 nm CNT CMOS FETs significantly outperform Si CMOS FETs with the same gate length but at much lower supply voltage Vds (0.4 V vs. 0.7 V), with an excellent sub-threshold slope swing (SS) of about 73mV/decade even with the gate length being scaled down to 5 nm. The 5 nm CNT FET begins to touch the quantum limit of a FET, and involves approximately only one electron when switching between on-state and off-state. These results show that CNT CMOS technology has the potential to go much further than that of Si towards quantum limit.
半导体碳纳米管(CNT)由于其超薄的结构和高载流子迁移率，被认为是未来场效应晶体管(fet)的理想通道材料，通道长度在10纳米以下。通过设计良好的器件结构，并与石墨烯结合，我们展示了高性能的顶门控碳纳米管场效应管，栅极长度缩小到5nm。缩放趋势研究表明，在栅极长度相同但电源电压Vds (0.4 V vs. 0.7 V)低得多的情况下，10 nm以下的碳纳米管CMOS fet的性能明显优于Si CMOS fet，即使栅极长度缩小到5 nm，其亚阈值斜率摆幅(SS)也约为73mV/ 10年。5nm碳纳米管FET开始触及FET的量子极限，并且在导通和关断状态之间切换时大约只涉及一个电子。这些结果表明，碳纳米管CMOS技术有可能比硅技术在量子极限方面走得更远。
{"title":"Scaling carbon nanotube CMOS FETs towards quantum limit","authors":"Chenguang Qiu, Zhiyong Zhang, Lianmao Peng","doi":"10.1109/IEDM.2017.8268334","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268334","url":null,"abstract":"Owing to its ultra-thin body and high carrier mobility, semiconducting carbon nanotube (CNT) has been considered as an ideal channel material for future field-effect transistors (FETs) with sub 10 nm channel length. With well-designed device structure and when combined with graphene, we demonstrated high performance top-gated CNT FETs with gate length scaled down to 5nm. Scaling trend study reveals that sub-10 nm CNT CMOS FETs significantly outperform Si CMOS FETs with the same gate length but at much lower supply voltage Vds (0.4 V vs. 0.7 V), with an excellent sub-threshold slope swing (SS) of about 73mV/decade even with the gate length being scaled down to 5 nm. The 5 nm CNT FET begins to touch the quantum limit of a FET, and involves approximately only one electron when switching between on-state and off-state. These results show that CNT CMOS technology has the potential to go much further than that of Si towards quantum limit.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114729854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268475
B. Sell, B. Bigwood, S. Cha, Z. Chen, P. Dhage, P. Fan, M. Giraud-Carrier, A. Kar, E. Karl, C. Ku, R. Kumar, T. Lajoie, H. Lee, G. Liu, S. Liu, Y. Ma, S. Mudanai, L. Nguyen, L. Paulson, K. Phoa, K. Pierce, A. Roy, R. Russell, J. Sandford, J. Stoeger, N. Stojanovic, A. Sultana, J. Waldemer, J. Wan, W. Xu, D. Young, J. Zhang, Y. Zhang, P. Bai
A FinFET technology named 22FFL has been developed that combines high-performance, ultra-low power logic and RF transistors as well as single-pattern backend flow for the first time. High performance transistors exhibit 57%/87% higher NMOS/PMOS drive current compared to the previously reported 22nm technology [1]. New ultra-low power logic devices are introduced that reduce bit cell leakage by 28x compared to a regular SRAM cell enabling a new 6T low-leakage SRAM with bit cell leakage of sub 1pA/cell. An RF device with optimized layout has been developed and shows excellent fT/fMAX of (230GHz/284GHz) and (238GHz/242GHz) for NMOS and PMOS respectively.
{"title":"22FFL: A high performance and ultra low power FinFET technology for mobile and RF applications","authors":"B. Sell, B. Bigwood, S. Cha, Z. Chen, P. Dhage, P. Fan, M. Giraud-Carrier, A. Kar, E. Karl, C. Ku, R. Kumar, T. Lajoie, H. Lee, G. Liu, S. Liu, Y. Ma, S. Mudanai, L. Nguyen, L. Paulson, K. Phoa, K. Pierce, A. Roy, R. Russell, J. Sandford, J. Stoeger, N. Stojanovic, A. Sultana, J. Waldemer, J. Wan, W. Xu, D. Young, J. Zhang, Y. Zhang, P. Bai","doi":"10.1109/IEDM.2017.8268475","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268475","url":null,"abstract":"A FinFET technology named 22FFL has been developed that combines high-performance, ultra-low power logic and RF transistors as well as single-pattern backend flow for the first time. High performance transistors exhibit 57%/87% higher NMOS/PMOS drive current compared to the previously reported 22nm technology [1]. New ultra-low power logic devices are introduced that reduce bit cell leakage by 28x compared to a regular SRAM cell enabling a new 6T low-leakage SRAM with bit cell leakage of sub 1pA/cell. An RF device with optimized layout has been developed and shows excellent fT/fMAX of (230GHz/284GHz) and (238GHz/242GHz) for NMOS and PMOS respectively.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124330434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268414
Yihao Chen, Siyuan Lu, Xue Feng
We present a strategy to design and fabricate a skin-like nanostructured biosensor system (SNBS) that is only 3.8μm thick with high glucose measuring sensitivity. The SNBS is fabricated on the silicon wafer with MEMS fabrication process and then “liquid capillary transferred” off the wafer. The SNBS totally conforms to the skin morphology and fully measures the minimal volume of the analytes distributed among the skin ridges and valleys. The nanostructured electrode facilitates high-efficiency electrochemical deposition of the mechanically robust nano-transducer layer. The SNBS owns significant glucose sensitivity (130.4μA/mM) and good linearity (R2 = 0.95) through large linear ranges. It has been successfully applied to non-invasive blood glucose (BG) monitoring in the in vivo clinical tests on human bodies. The measuring results are highly correlated to the glucometer and the venous blood testing results (>0.9). The SNBS can be used for the first time in clinical-grade fully non-invasive continuous glucose monitoring.
{"title":"Skin-like nanostrucutred biosensor system for noninvasive blood glucose monitoring","authors":"Yihao Chen, Siyuan Lu, Xue Feng","doi":"10.1109/IEDM.2017.8268414","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268414","url":null,"abstract":"We present a strategy to design and fabricate a skin-like nanostructured biosensor system (SNBS) that is only 3.8μm thick with high glucose measuring sensitivity. The SNBS is fabricated on the silicon wafer with MEMS fabrication process and then “liquid capillary transferred” off the wafer. The SNBS totally conforms to the skin morphology and fully measures the minimal volume of the analytes distributed among the skin ridges and valleys. The nanostructured electrode facilitates high-efficiency electrochemical deposition of the mechanically robust nano-transducer layer. The SNBS owns significant glucose sensitivity (130.4μA/mM) and good linearity (R2 = 0.95) through large linear ranges. It has been successfully applied to non-invasive blood glucose (BG) monitoring in the in vivo clinical tests on human bodies. The measuring results are highly correlated to the glucometer and the venous blood testing results (>0.9). The SNBS can be used for the first time in clinical-grade fully non-invasive continuous glucose monitoring.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124147954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268358
M. Noguchi, T. Iwamatsu, H. Amishiro, H. Watanabe, K. Kita, S. Yamakawa
We determined the intrinsic phonon-limited mobility in the SiC MOSFET, for the first time. Based on this finding, the carrier transport properties of 4H-SiC MOSFETs such as phonon, surface roughness and Coulomb scattering were evaluated by experimental procedures. This approach is different from the conventional methods, which have adjusted the parameters in the mobility models. It was realized due to the suppression of severe impact of Coulomb scattering on SiC MOS inversion layer by lowering the acceptor concentration of p-type well region in the order of 1014 cm−3. The phonon-limited mobility of the SiC MOSFET is revealed to be one fourth or less than conventionally presumed values. In addition, different from the conventional understanding, it was clarified that surface roughness scattering is not the most dominant mobility limiting factor even in high effective normal field for the SiC MOSFET. These results represent that conventional mobility models should be modified in high effective normal field, especially at high temperature.
{"title":"Determination of intrinsic phonon-limited mobility and carrier transport property extraction of 4H-SiC MOSFETs","authors":"M. Noguchi, T. Iwamatsu, H. Amishiro, H. Watanabe, K. Kita, S. Yamakawa","doi":"10.1109/IEDM.2017.8268358","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268358","url":null,"abstract":"We determined the intrinsic phonon-limited mobility in the SiC MOSFET, for the first time. Based on this finding, the carrier transport properties of 4H-SiC MOSFETs such as phonon, surface roughness and Coulomb scattering were evaluated by experimental procedures. This approach is different from the conventional methods, which have adjusted the parameters in the mobility models. It was realized due to the suppression of severe impact of Coulomb scattering on SiC MOS inversion layer by lowering the acceptor concentration of p-type well region in the order of 1014 cm−3. The phonon-limited mobility of the SiC MOSFET is revealed to be one fourth or less than conventionally presumed values. In addition, different from the conventional understanding, it was clarified that surface roughness scattering is not the most dominant mobility limiting factor even in high effective normal field for the SiC MOSFET. These results represent that conventional mobility models should be modified in high effective normal field, especially at high temperature.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127685417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268425
S. Dunkel, M. Trentzsch, R. Richter, P. Moll, C. Fuchs, O. Gehring, M. Majer, S. Wittek, B. Muller, T. Melde, H. Mulaosmanovic, S. Slesazeck, S. Müller, J. Ocker, M. Noack, D. Lohr, P. Polakowski, J. Müller, T. Mikolajick, J. Hontschel, B. Rice, J. Pellerin, S. Beyer
We show the implementation of a ferroelectric field effect transistor (FeFET) based eNVM solution into a leading edge 22nm FDSOI CMOS technology. Memory windows of 1.5 V are demonstrated in aggressively scaled FeFET cells with an area as small as 0.025 μm2 At this point program/erase endurance cycles up to 105 are supported. Complex pattern are written into 32 MBit arrays using ultrafast program/erase pulses in a 10 ns range at 4.2 V. High temperature retention up to 300 °C is achieved. It makes FeFET based eNVM a viable choice for overall low-cost and low-power IoT applications in 22nm and beyond technology nodes.
{"title":"A FeFET based super-low-power ultra-fast embedded NVM technology for 22nm FDSOI and beyond","authors":"S. Dunkel, M. Trentzsch, R. Richter, P. Moll, C. Fuchs, O. Gehring, M. Majer, S. Wittek, B. Muller, T. Melde, H. Mulaosmanovic, S. Slesazeck, S. Müller, J. Ocker, M. Noack, D. Lohr, P. Polakowski, J. Müller, T. Mikolajick, J. Hontschel, B. Rice, J. Pellerin, S. Beyer","doi":"10.1109/IEDM.2017.8268425","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268425","url":null,"abstract":"We show the implementation of a ferroelectric field effect transistor (FeFET) based eNVM solution into a leading edge 22nm FDSOI CMOS technology. Memory windows of 1.5 V are demonstrated in aggressively scaled FeFET cells with an area as small as 0.025 μm2 At this point program/erase endurance cycles up to 105 are supported. Complex pattern are written into 32 MBit arrays using ultrafast program/erase pulses in a 10 ns range at 4.2 V. High temperature retention up to 300 °C is achieved. It makes FeFET based eNVM a viable choice for overall low-cost and low-power IoT applications in 22nm and beyond technology nodes.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127884424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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