Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268488
C. Tsai, Yun-Hsiang Wang, M. Kwan, P.-C. Chen, F. Yao, S.-C. Liu, J.-L. Yu, C. Yeh, R. Su, W. Wang, W. Yang, K.Y. Wong, Y.-S. Lin, M. Lin, H.-Y Wu, C.-M. Chen, C. Yu, C.-B. Wu, M. Chang, J.-S. You, T.M. Huang, S.P. Wang, L. Tsai, Chan-Hong Chern, H. Tuan, A. Kalnitsky
This paper explores the next stage of GaN power devices with 2-level integration of peripheral low voltage active and passive devices. The 1st level consists of protection/control/driving circuits, which potentially improves the performance and overcomes the challenges to the power devices. The 2nd level integration has high-low side on-chip integration on a 100V technology platform. The challenge of channel modulation due to substrate bias sharing is effectively eliminated by the invented new scheme. The system efficiency of DC-DC buck converter using such scheme is enhanced with lower on-state resistance and good stability.
{"title":"Smart GaN platform: Performance & challenges","authors":"C. Tsai, Yun-Hsiang Wang, M. Kwan, P.-C. Chen, F. Yao, S.-C. Liu, J.-L. Yu, C. Yeh, R. Su, W. Wang, W. Yang, K.Y. Wong, Y.-S. Lin, M. Lin, H.-Y Wu, C.-M. Chen, C. Yu, C.-B. Wu, M. Chang, J.-S. You, T.M. Huang, S.P. Wang, L. Tsai, Chan-Hong Chern, H. Tuan, A. Kalnitsky","doi":"10.1109/IEDM.2017.8268488","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268488","url":null,"abstract":"This paper explores the next stage of GaN power devices with 2-level integration of peripheral low voltage active and passive devices. The 1st level consists of protection/control/driving circuits, which potentially improves the performance and overcomes the challenges to the power devices. The 2nd level integration has high-low side on-chip integration on a 100V technology platform. The challenge of channel modulation due to substrate bias sharing is effectively eliminated by the invented new scheme. The system efficiency of DC-DC buck converter using such scheme is enhanced with lower on-state resistance and good stability.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126595197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268308
Jack Sun
Wafer based 3D×3D system scaling revolutionizes machine learning (ML) and artificial intelligence (AI) as well as mobile computing. It may trigger a big bang in intelligent ubiquitous computing. 3D CMOS scaling continues with many challenges and opportunities for relentless innovation in materials, processes, devices, circuits, design, EDA, computing architectures, algorithms, and software. 3D stacking and heterogeneous system integration, e.g., CoWoS® and InFO, not only augments but also amplifies the benefits of 3D CMOS logic, 3D memory, integrated specialty technologies and 3D sensors for intelligent ubiquitous computing. The virtuous cycles of 3D×3D system scaling innovation may expand like a galaxy or universe. The aggregate transistor count in a 3D×3D sub-system may reach the equivalent of human brain in the 2020s to provide brain-like augmented intelligence.
{"title":"System scaling for intelligent ubiquitous computing","authors":"Jack Sun","doi":"10.1109/IEDM.2017.8268308","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268308","url":null,"abstract":"Wafer based 3D×3D system scaling revolutionizes machine learning (ML) and artificial intelligence (AI) as well as mobile computing. It may trigger a big bang in intelligent ubiquitous computing. 3D CMOS scaling continues with many challenges and opportunities for relentless innovation in materials, processes, devices, circuits, design, EDA, computing architectures, algorithms, and software. 3D stacking and heterogeneous system integration, e.g., CoWoS® and InFO, not only augments but also amplifies the benefits of 3D CMOS logic, 3D memory, integrated specialty technologies and 3D sensors for intelligent ubiquitous computing. The virtuous cycles of 3D×3D system scaling innovation may expand like a galaxy or universe. The aggregate transistor count in a 3D×3D sub-system may reach the equivalent of human brain in the 2020s to provide brain-like augmented intelligence.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116103009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268520
Y. Qu, Xi Lin, Junkang Li, R. Cheng, Xiao Yu, Z. Zheng, Jiwu Lu, Bing Chen, Yi Zhao
We demonstrate electrical characterizations within sub-1 ns to investigate the self-heating effect (SHE) in 14 nm FinFETs, for the first time. Thanks to the extremely fast I-V measurement speed (∼500 ps), the heat generation and dissipation process in the transistor channel are precisely captured. Furthermore, the unique correlation between channel temperature and drain current at different gate and drain biases is obtained. With this correlation, the transient and static channel temperatures could be extracted for devices with any working conditions and switching speeds. The impact of SHE on HCI degradation under real circuit stress is also investigated, showing that even under high frequency working conditions (GHz with random signals), SHE still has significant impact on HCI degradation in 14 nm FinFETs.
{"title":"Ultra fast (<1 ns) electrical characterization of self-heating effect and its impact on hot carrier injection in 14nm FinFETs","authors":"Y. Qu, Xi Lin, Junkang Li, R. Cheng, Xiao Yu, Z. Zheng, Jiwu Lu, Bing Chen, Yi Zhao","doi":"10.1109/IEDM.2017.8268520","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268520","url":null,"abstract":"We demonstrate electrical characterizations within sub-1 ns to investigate the self-heating effect (SHE) in 14 nm FinFETs, for the first time. Thanks to the extremely fast I-V measurement speed (∼500 ps), the heat generation and dissipation process in the transistor channel are precisely captured. Furthermore, the unique correlation between channel temperature and drain current at different gate and drain biases is obtained. With this correlation, the transient and static channel temperatures could be extracted for devices with any working conditions and switching speeds. The impact of SHE on HCI degradation under real circuit stress is also investigated, showing that even under high frequency working conditions (GHz with random signals), SHE still has significant impact on HCI degradation in 14 nm FinFETs.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121742141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM19572.2017.9110625
O. Olanrewaju, C. Mbohwa
World energy consumption is responsible for the growth of the economy. Having it in abundant will do more to the continuous global growth. Fundamental factors to how energy is consumed are population and gross domestic product (GDP). This study focusses on predicting the global energy consumption from 1995 to 2009 using the fundamental factors as inputs. Statistical and evolutionary algorithm in the form of regression analysis and artificial neural network (ANN) were compared in their prediction performance. Both techniques performed brilliantly as indicated by the coefficient of correlation and visual inspection, however, ANN performed better. Analyzing the factors through the connection weights of ANN reported population to be the significant factor contributing more to how energy is consumed globally. It is important to have policies that can influence population positively in order to have abundant supply of energy whenever there is demand for it.
{"title":"Predicting World Energy Consumption: Comparison of ANN and Regression Analysis","authors":"O. Olanrewaju, C. Mbohwa","doi":"10.1109/IEDM19572.2017.9110625","DOIUrl":"https://doi.org/10.1109/IEDM19572.2017.9110625","url":null,"abstract":"World energy consumption is responsible for the growth of the economy. Having it in abundant will do more to the continuous global growth. Fundamental factors to how energy is consumed are population and gross domestic product (GDP). This study focusses on predicting the global energy consumption from 1995 to 2009 using the fundamental factors as inputs. Statistical and evolutionary algorithm in the form of regression analysis and artificial neural network (ANN) were compared in their prediction performance. Both techniques performed brilliantly as indicated by the coefficient of correlation and visual inspection, however, ANN performed better. Analyzing the factors through the connection weights of ANN reported population to be the significant factor contributing more to how energy is consumed globally. It is important to have policies that can influence population positively in order to have abundant supply of energy whenever there is demand for it.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114627386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268490
T. Yonehara, Y. Kajiwara, D. Kato, K. Uesugi, T. Shimizu, Y. Nishida, H. Ono, A. Shindome, A. Mukai, A. Yoshioka, M. Kuraguchi
Threshold voltage shift of GaN MOSFET in positive bias temperature instability test was drastically suppressed by reducing certain impurity densities in SiO2 gate dielectric. An analysis to estimate the charge trap level showed electron traps in the gate dielectric caused the threshold voltage shift in GaN MOSFETs. Moreover, impurities, which formed the electron traps in SiO2, were controlled by heat treatment after SiO2 deposition, and the threshold voltage shift characteristic was improved by the reduction of the impurity densities.
{"title":"Improvement of positive bias temperature instability characteristic in GaN MOSFETs by control of impurity density in SiO2 gate dielectric","authors":"T. Yonehara, Y. Kajiwara, D. Kato, K. Uesugi, T. Shimizu, Y. Nishida, H. Ono, A. Shindome, A. Mukai, A. Yoshioka, M. Kuraguchi","doi":"10.1109/IEDM.2017.8268490","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268490","url":null,"abstract":"Threshold voltage shift of GaN MOSFET in positive bias temperature instability test was drastically suppressed by reducing certain impurity densities in SiO2 gate dielectric. An analysis to estimate the charge trap level showed electron traps in the gate dielectric caused the threshold voltage shift in GaN MOSFETs. Moreover, impurities, which formed the electron traps in SiO2, were controlled by heat treatment after SiO2 deposition, and the threshold voltage shift characteristic was improved by the reduction of the impurity densities.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"328 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115874565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268442
N. Okada, N. Uchida, S. Ogawa, K. Endo, T. Kanayama
The insertion of an amorphous WSin (n = 12) film composed of W-atom-encapsulated Sin cage clusters is demonstrated to reduce the SBH to 0.32 eV at W/n-Si and to 0.51 eV at W/Ge/p-Si junctions, while significantly extending the estimated TDDB lifetime to > 10 years at 100 °C under 5 MV/cm stress for Cu MOS capacitors. This film was formed with an excellent contact hole coverage by using WF6 and SiH4 gas sources in a hot-wall thermal reactor. These film properties enable the direct Cu contact at S/D in CMOS.
{"title":"Cluster-preforming-deposited amorphous WSin (n = 12) insertion film of low SBH and high diffusion barrier for direct Cu contact","authors":"N. Okada, N. Uchida, S. Ogawa, K. Endo, T. Kanayama","doi":"10.1109/IEDM.2017.8268442","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268442","url":null,"abstract":"The insertion of an amorphous WSin (n = 12) film composed of W-atom-encapsulated Sin cage clusters is demonstrated to reduce the SBH to 0.32 eV at W/n-Si and to 0.51 eV at W/Ge/p-Si junctions, while significantly extending the estimated TDDB lifetime to > 10 years at 100 °C under 5 MV/cm stress for Cu MOS capacitors. This film was formed with an excellent contact hole coverage by using WF6 and SiH4 gas sources in a hot-wall thermal reactor. These film properties enable the direct Cu contact at S/D in CMOS.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122131480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268320
L. England, I. Arsovski
Technology scaling is becoming more difficult and costly with each generation. As we scale below 7nm, there is uncertainty in the methodology that will be used for device formation and integration. Now, more than ever, the use of advanced packaging technologies is needed to help extend the lifetimes of our most advanced fab technologies. In this “More Than Moore” era, transistor density can be considered in terms of volume rather than area, and the proliferation of TSV integration is the key enabling technology.
{"title":"Advanced packaging saves the day! — How TSV technology will enable continued scaling","authors":"L. England, I. Arsovski","doi":"10.1109/IEDM.2017.8268320","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268320","url":null,"abstract":"Technology scaling is becoming more difficult and costly with each generation. As we scale below 7nm, there is uncertainty in the methodology that will be used for device formation and integration. Now, more than ever, the use of advanced packaging technologies is needed to help extend the lifetimes of our most advanced fab technologies. In this “More Than Moore” era, transistor density can be considered in terms of volume rather than area, and the proliferation of TSV integration is the key enabling technology.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114953960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268376
Yachuan Pang, Huaqiang Wu, B. Gao, Dong Wu, An Chen, H. Qian
Physical unclonable function (PUF) is an important hardware security primitive. This paper proposes a novel PUF design based on a double-layer RRAM array architecture and digital RRAM programming achieved by splitting resistance distribution after a continuous distribution was formed. The proposed PUF was implemented on a 16 Mb RRAM test chip and its randomness was verified with NIST test suite. The experimental results demonstrate strong reliability and significantly enhanced resistance against machine-learning attack of this novel PUF design.
{"title":"A novel PUF against machine learning attack: Implementation on a 16 Mb RRAM chip","authors":"Yachuan Pang, Huaqiang Wu, B. Gao, Dong Wu, An Chen, H. Qian","doi":"10.1109/IEDM.2017.8268376","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268376","url":null,"abstract":"Physical unclonable function (PUF) is an important hardware security primitive. This paper proposes a novel PUF design based on a double-layer RRAM array architecture and digital RRAM programming achieved by splitting resistance distribution after a continuous distribution was formed. The proposed PUF was implemented on a 16 Mb RRAM test chip and its randomness was verified with NIST test suite. The experimental results demonstrate strong reliability and significantly enhanced resistance against machine-learning attack of this novel PUF design.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122879565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268356
Yusuke Kobayashi, N. Ohse, T. Morimoto, Makoto Kato, T. Kojima, M. Miyazato, M. Takei, Hiroshi Kimura, S. Harada
Integration of SBD into SiC-MOSFET is promising to solve body-PiN-diode related problems known such as forward degradation and reverse recovery loss. Particularly in lower breakdown-voltage-class SBD-integrated MOSFET, cell pitch reduction has a greater impact on inactivating the body-PiN-diode. Here, we developed a novel device called an SBD-wall-integrated trench MOSFET (SWITCH-MOS), in which small cell pitch of 5p.m was realized by utilizing trench side walls both for SBD and MOS channel with buried p+ layer. The fabricated 1.2 kV SWITCH-MOS successfully suppressed the forward degradation under extremely high current density condition with low switching loss, low specific on-resistance, and low leakage current.
{"title":"Body PiN diode inactivation with low on-resistance achieved by a 1.2 kV-class 4H-SiC SWITCH-MOS","authors":"Yusuke Kobayashi, N. Ohse, T. Morimoto, Makoto Kato, T. Kojima, M. Miyazato, M. Takei, Hiroshi Kimura, S. Harada","doi":"10.1109/IEDM.2017.8268356","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268356","url":null,"abstract":"Integration of SBD into SiC-MOSFET is promising to solve body-PiN-diode related problems known such as forward degradation and reverse recovery loss. Particularly in lower breakdown-voltage-class SBD-integrated MOSFET, cell pitch reduction has a greater impact on inactivating the body-PiN-diode. Here, we developed a novel device called an SBD-wall-integrated trench MOSFET (SWITCH-MOS), in which small cell pitch of 5p.m was realized by utilizing trench side walls both for SBD and MOS channel with buried p+ layer. The fabricated 1.2 kV SWITCH-MOS successfully suppressed the forward degradation under extremely high current density condition with low switching loss, low specific on-resistance, and low leakage current.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126490842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268515
Guohan Hu, Matthias Georg Gottwald, Qing He, Joon-Min Park, G. Lauer, Janusz J. Nowak, S. Brown, B. Doris, D. Edelstein, E. Evarts, Pouya Hashemi, B. Khan, Young-Hwan Kim, C. Kothandaraman, P. MarchackNathan, E. O'Sullivan, M. Reuter, R. Robertazzi, Jonathan Z. Sun, T. Suwannasiri, P. Trouilloud, Y. Zhu, D. Worledge
We report the impact of four key parameters on switching efficiency of STT-MRAM devices with perpendicular magnetic anisotropy: device size, device resistance-area product (RA), blanket film Gilbert damping constant (a), and process temperature. Performance degradation observed in 400°C-processed devices was eliminated by optimizing the perpendicular magnetic tunnel junction (p-MTJ) materials. Furthermore, 400°C-compatible double MTJs were developed for the first time and showed 1.5x improvement in switching efficiency compared to single MTJs with identical free layers.
{"title":"Key parameters affecting STT-MRAM switching efficiency and improved device performance of 400°C-compatible p-MTJs","authors":"Guohan Hu, Matthias Georg Gottwald, Qing He, Joon-Min Park, G. Lauer, Janusz J. Nowak, S. Brown, B. Doris, D. Edelstein, E. Evarts, Pouya Hashemi, B. Khan, Young-Hwan Kim, C. Kothandaraman, P. MarchackNathan, E. O'Sullivan, M. Reuter, R. Robertazzi, Jonathan Z. Sun, T. Suwannasiri, P. Trouilloud, Y. Zhu, D. Worledge","doi":"10.1109/IEDM.2017.8268515","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268515","url":null,"abstract":"We report the impact of four key parameters on switching efficiency of STT-MRAM devices with perpendicular magnetic anisotropy: device size, device resistance-area product (RA), blanket film Gilbert damping constant (a), and process temperature. Performance degradation observed in 400°C-processed devices was eliminated by optimizing the perpendicular magnetic tunnel junction (p-MTJ) materials. Furthermore, 400°C-compatible double MTJs were developed for the first time and showed 1.5x improvement in switching efficiency compared to single MTJs with identical free layers.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129559503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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