Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268488
C. Tsai, Yun-Hsiang Wang, M. Kwan, P.-C. Chen, F. Yao, S.-C. Liu, J.-L. Yu, C. Yeh, R. Su, W. Wang, W. Yang, K.Y. Wong, Y.-S. Lin, M. Lin, H.-Y Wu, C.-M. Chen, C. Yu, C.-B. Wu, M. Chang, J.-S. You, T.M. Huang, S.P. Wang, L. Tsai, Chan-Hong Chern, H. Tuan, A. Kalnitsky
This paper explores the next stage of GaN power devices with 2-level integration of peripheral low voltage active and passive devices. The 1st level consists of protection/control/driving circuits, which potentially improves the performance and overcomes the challenges to the power devices. The 2nd level integration has high-low side on-chip integration on a 100V technology platform. The challenge of channel modulation due to substrate bias sharing is effectively eliminated by the invented new scheme. The system efficiency of DC-DC buck converter using such scheme is enhanced with lower on-state resistance and good stability.
{"title":"Smart GaN platform: Performance & challenges","authors":"C. Tsai, Yun-Hsiang Wang, M. Kwan, P.-C. Chen, F. Yao, S.-C. Liu, J.-L. Yu, C. Yeh, R. Su, W. Wang, W. Yang, K.Y. Wong, Y.-S. Lin, M. Lin, H.-Y Wu, C.-M. Chen, C. Yu, C.-B. Wu, M. Chang, J.-S. You, T.M. Huang, S.P. Wang, L. Tsai, Chan-Hong Chern, H. Tuan, A. Kalnitsky","doi":"10.1109/IEDM.2017.8268488","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268488","url":null,"abstract":"This paper explores the next stage of GaN power devices with 2-level integration of peripheral low voltage active and passive devices. The 1st level consists of protection/control/driving circuits, which potentially improves the performance and overcomes the challenges to the power devices. The 2nd level integration has high-low side on-chip integration on a 100V technology platform. The challenge of channel modulation due to substrate bias sharing is effectively eliminated by the invented new scheme. The system efficiency of DC-DC buck converter using such scheme is enhanced with lower on-state resistance and good stability.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126595197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268308
Jack Sun
Wafer based 3D×3D system scaling revolutionizes machine learning (ML) and artificial intelligence (AI) as well as mobile computing. It may trigger a big bang in intelligent ubiquitous computing. 3D CMOS scaling continues with many challenges and opportunities for relentless innovation in materials, processes, devices, circuits, design, EDA, computing architectures, algorithms, and software. 3D stacking and heterogeneous system integration, e.g., CoWoS® and InFO, not only augments but also amplifies the benefits of 3D CMOS logic, 3D memory, integrated specialty technologies and 3D sensors for intelligent ubiquitous computing. The virtuous cycles of 3D×3D system scaling innovation may expand like a galaxy or universe. The aggregate transistor count in a 3D×3D sub-system may reach the equivalent of human brain in the 2020s to provide brain-like augmented intelligence.
{"title":"System scaling for intelligent ubiquitous computing","authors":"Jack Sun","doi":"10.1109/IEDM.2017.8268308","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268308","url":null,"abstract":"Wafer based 3D×3D system scaling revolutionizes machine learning (ML) and artificial intelligence (AI) as well as mobile computing. It may trigger a big bang in intelligent ubiquitous computing. 3D CMOS scaling continues with many challenges and opportunities for relentless innovation in materials, processes, devices, circuits, design, EDA, computing architectures, algorithms, and software. 3D stacking and heterogeneous system integration, e.g., CoWoS® and InFO, not only augments but also amplifies the benefits of 3D CMOS logic, 3D memory, integrated specialty technologies and 3D sensors for intelligent ubiquitous computing. The virtuous cycles of 3D×3D system scaling innovation may expand like a galaxy or universe. The aggregate transistor count in a 3D×3D sub-system may reach the equivalent of human brain in the 2020s to provide brain-like augmented intelligence.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116103009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268520
Y. Qu, Xi Lin, Junkang Li, R. Cheng, Xiao Yu, Z. Zheng, Jiwu Lu, Bing Chen, Yi Zhao
We demonstrate electrical characterizations within sub-1 ns to investigate the self-heating effect (SHE) in 14 nm FinFETs, for the first time. Thanks to the extremely fast I-V measurement speed (∼500 ps), the heat generation and dissipation process in the transistor channel are precisely captured. Furthermore, the unique correlation between channel temperature and drain current at different gate and drain biases is obtained. With this correlation, the transient and static channel temperatures could be extracted for devices with any working conditions and switching speeds. The impact of SHE on HCI degradation under real circuit stress is also investigated, showing that even under high frequency working conditions (GHz with random signals), SHE still has significant impact on HCI degradation in 14 nm FinFETs.
{"title":"Ultra fast (<1 ns) electrical characterization of self-heating effect and its impact on hot carrier injection in 14nm FinFETs","authors":"Y. Qu, Xi Lin, Junkang Li, R. Cheng, Xiao Yu, Z. Zheng, Jiwu Lu, Bing Chen, Yi Zhao","doi":"10.1109/IEDM.2017.8268520","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268520","url":null,"abstract":"We demonstrate electrical characterizations within sub-1 ns to investigate the self-heating effect (SHE) in 14 nm FinFETs, for the first time. Thanks to the extremely fast I-V measurement speed (∼500 ps), the heat generation and dissipation process in the transistor channel are precisely captured. Furthermore, the unique correlation between channel temperature and drain current at different gate and drain biases is obtained. With this correlation, the transient and static channel temperatures could be extracted for devices with any working conditions and switching speeds. The impact of SHE on HCI degradation under real circuit stress is also investigated, showing that even under high frequency working conditions (GHz with random signals), SHE still has significant impact on HCI degradation in 14 nm FinFETs.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121742141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268390
B. Turkot, S. Carson, A. Lio
Extreme Ultra-Violet (EUV) lithography, with its exposure wavelength of 13.5nm, offers a compelling alternative to 193nm-immersion lithography, improving imaging resolution and reducing a key contribution to Edge Placement Error (EPE). Recently, significant progress has been made in the development of EUV exposure tools, with source power meeting the roadmap target for EUV insertion1 as well as demonstrating improvements in system availability and infrastructure such as mask blank defectivity, pellicle membrane manufacturing, and EUV photoresist materials. This paper reviews the current status and challenges of EUV lithography for High Volume Manufacturing (HVM).
{"title":"Continuing Moore's law with EUV lithography","authors":"B. Turkot, S. Carson, A. Lio","doi":"10.1109/IEDM.2017.8268390","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268390","url":null,"abstract":"Extreme Ultra-Violet (EUV) lithography, with its exposure wavelength of 13.5nm, offers a compelling alternative to 193nm-immersion lithography, improving imaging resolution and reducing a key contribution to Edge Placement Error (EPE). Recently, significant progress has been made in the development of EUV exposure tools, with source power meeting the roadmap target for EUV insertion1 as well as demonstrating improvements in system availability and infrastructure such as mask blank defectivity, pellicle membrane manufacturing, and EUV photoresist materials. This paper reviews the current status and challenges of EUV lithography for High Volume Manufacturing (HVM).","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132385657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268336
T. Agarwal, Á. Szabó, M. Bardon, B. Sorée, I. Radu, P. Raghavan, M. Luisier, W. Dehaene, M. Heyns
In this paper, monolayer transition metal dichalcogenide (MX2) FETs are benchmarked with Si FinFET using energy-delay as figure-of-merits and a physical compact model. The model is validated with the help of both atomistic simulations and experimental data for different materials, without the use of any fitting parameter. Single-gate (SG) and double-gate (DG) MX2 FETs are compared from ON current, device capacitance and energy-delay perspective. DG MX2 FETs perform 25–30% faster than SG MX2 FETs for the same energy consumption in case of dominating wire load. WS2 DG FET shows both better energy and speed among chosen MX2 materials. However, in comparison to FinFET, WS2 DG FETs are shown to be ∼ 35% slower, but more energy efficient. Therefore, to match FinFET's performance with MX2 FETs, monolithic 3D integrated MX2 SG and DG FETs are explored. It is shown that 3–5 stacked WS2 DG FETs are needed to meet N3 FinFET performance.
{"title":"Benchmarking of monolithic 3D integrated MX2 FETs with Si FinFETs","authors":"T. Agarwal, Á. Szabó, M. Bardon, B. Sorée, I. Radu, P. Raghavan, M. Luisier, W. Dehaene, M. Heyns","doi":"10.1109/IEDM.2017.8268336","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268336","url":null,"abstract":"In this paper, monolayer transition metal dichalcogenide (MX2) FETs are benchmarked with Si FinFET using energy-delay as figure-of-merits and a physical compact model. The model is validated with the help of both atomistic simulations and experimental data for different materials, without the use of any fitting parameter. Single-gate (SG) and double-gate (DG) MX2 FETs are compared from ON current, device capacitance and energy-delay perspective. DG MX2 FETs perform 25–30% faster than SG MX2 FETs for the same energy consumption in case of dominating wire load. WS2 DG FET shows both better energy and speed among chosen MX2 materials. However, in comparison to FinFET, WS2 DG FETs are shown to be ∼ 35% slower, but more energy efficient. Therefore, to match FinFET's performance with MX2 FETs, monolithic 3D integrated MX2 SG and DG FETs are explored. It is shown that 3–5 stacked WS2 DG FETs are needed to meet N3 FinFET performance.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132046978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268360
T. Kimoto, H. Niwa, N. Kaji, T. Kobayashi, Y. Zhao, S. Mori, M. Aketa
Recent progress in SiC device physics and development of power devices in the authors' group is reviewed. The impact ionization coefficients in the wide temperature range were determined, which enables accurate device simulation. 13 kV SiC pin diodes with a very low differential on-resistance of 1.4 mΩ.cm2 and 11 kV SiC epitaxial MPS diodes are presented. A mobility-limiting factor in SiC MOSFETs is discussed, and 3 kV reverse-blocking MOSFETs are demonstrated.
{"title":"Progress and future challenges of SiC power devices and process technology","authors":"T. Kimoto, H. Niwa, N. Kaji, T. Kobayashi, Y. Zhao, S. Mori, M. Aketa","doi":"10.1109/IEDM.2017.8268360","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268360","url":null,"abstract":"Recent progress in SiC device physics and development of power devices in the authors' group is reviewed. The impact ionization coefficients in the wide temperature range were determined, which enables accurate device simulation. 13 kV SiC pin diodes with a very low differential on-resistance of 1.4 mΩ.cm2 and 11 kV SiC epitaxial MPS diodes are presented. A mobility-limiting factor in SiC MOSFETs is discussed, and 3 kV reverse-blocking MOSFETs are demonstrated.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133452618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268394
H. Ota, K. Fukuda, T. Ikegami, J. Hattori, H. Asai, S. Migita, A. Toriumi
Stability and instability of the negative capacitance (NC) states in metal (M) / ferroelectric (F) /M /insulator (I) /semiconductor (S) structures are rigorously studied using a newly developed transient TCAD simulation, in which time-dependent Landau-Khalatnikov (LK) equation can be considered. Our transient analysis reveals that NC becomes unstable due to formation of the inversion layer and gives rise to hysteresis in the NC-state, which cannot be simulated by the steady simulation. We propose a novel FinFET, in which the F-layer is located at the gate contact holes and exhibit a design guideline to avoid the instability of the NC-state using experimentally obtained ferroelectric parameters for (Hf, Zr)O2.
{"title":"Perspective of negative capacitance FinFETs investigated by transient TCAD simulation","authors":"H. Ota, K. Fukuda, T. Ikegami, J. Hattori, H. Asai, S. Migita, A. Toriumi","doi":"10.1109/IEDM.2017.8268394","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268394","url":null,"abstract":"Stability and instability of the negative capacitance (NC) states in metal (M) / ferroelectric (F) /M /insulator (I) /semiconductor (S) structures are rigorously studied using a newly developed transient TCAD simulation, in which time-dependent Landau-Khalatnikov (LK) equation can be considered. Our transient analysis reveals that NC becomes unstable due to formation of the inversion layer and gives rise to hysteresis in the NC-state, which cannot be simulated by the steady simulation. We propose a novel FinFET, in which the F-layer is located at the gate contact holes and exhibit a design guideline to avoid the instability of the NC-state using experimentally obtained ferroelectric parameters for (Hf, Zr)O2.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131944568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268351
J. Zhao, Q. Li, Y. Huang, S. Li, W. Tang, S. Peng, S. Chen, W. Liu, X. Guo
A printable device structure design is introduced to fabricate low voltage organic field effect transistor (OFET) of steep subthreshold (80 mV/dec) using thick gate dielectric layers and high throughput printing/coating processes. The device design also bring benefit on excellent bias stress stability. The device is shown to able to be biased in the subthreshold regime with near zero gate voltage for low power and high sensitivity detection of both small H+ concentration (<0.1 pH) and weak fluorescence signal (< 10 μW cm−2) changes.
{"title":"Manufactured-on-demand steep subthreshold organic field effect transistor for low power and high sensitivity ion and fluorescence sensing","authors":"J. Zhao, Q. Li, Y. Huang, S. Li, W. Tang, S. Peng, S. Chen, W. Liu, X. Guo","doi":"10.1109/IEDM.2017.8268351","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268351","url":null,"abstract":"A printable device structure design is introduced to fabricate low voltage organic field effect transistor (OFET) of steep subthreshold (80 mV/dec) using thick gate dielectric layers and high throughput printing/coating processes. The device design also bring benefit on excellent bias stress stability. The device is shown to able to be biased in the subthreshold regime with near zero gate voltage for low power and high sensitivity detection of both small H+ concentration (<0.1 pH) and weak fluorescence signal (< 10 μW cm−2) changes.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116877356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268320
L. England, I. Arsovski
Technology scaling is becoming more difficult and costly with each generation. As we scale below 7nm, there is uncertainty in the methodology that will be used for device formation and integration. Now, more than ever, the use of advanced packaging technologies is needed to help extend the lifetimes of our most advanced fab technologies. In this “More Than Moore” era, transistor density can be considered in terms of volume rather than area, and the proliferation of TSV integration is the key enabling technology.
{"title":"Advanced packaging saves the day! — How TSV technology will enable continued scaling","authors":"L. England, I. Arsovski","doi":"10.1109/IEDM.2017.8268320","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268320","url":null,"abstract":"Technology scaling is becoming more difficult and costly with each generation. As we scale below 7nm, there is uncertainty in the methodology that will be used for device formation and integration. Now, more than ever, the use of advanced packaging technologies is needed to help extend the lifetimes of our most advanced fab technologies. In this “More Than Moore” era, transistor density can be considered in terms of volume rather than area, and the proliferation of TSV integration is the key enabling technology.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114953960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM19572.2017.9110625
O. Olanrewaju, C. Mbohwa
World energy consumption is responsible for the growth of the economy. Having it in abundant will do more to the continuous global growth. Fundamental factors to how energy is consumed are population and gross domestic product (GDP). This study focusses on predicting the global energy consumption from 1995 to 2009 using the fundamental factors as inputs. Statistical and evolutionary algorithm in the form of regression analysis and artificial neural network (ANN) were compared in their prediction performance. Both techniques performed brilliantly as indicated by the coefficient of correlation and visual inspection, however, ANN performed better. Analyzing the factors through the connection weights of ANN reported population to be the significant factor contributing more to how energy is consumed globally. It is important to have policies that can influence population positively in order to have abundant supply of energy whenever there is demand for it.
{"title":"Predicting World Energy Consumption: Comparison of ANN and Regression Analysis","authors":"O. Olanrewaju, C. Mbohwa","doi":"10.1109/IEDM19572.2017.9110625","DOIUrl":"https://doi.org/10.1109/IEDM19572.2017.9110625","url":null,"abstract":"World energy consumption is responsible for the growth of the economy. Having it in abundant will do more to the continuous global growth. Fundamental factors to how energy is consumed are population and gross domestic product (GDP). This study focusses on predicting the global energy consumption from 1995 to 2009 using the fundamental factors as inputs. Statistical and evolutionary algorithm in the form of regression analysis and artificial neural network (ANN) were compared in their prediction performance. Both techniques performed brilliantly as indicated by the coefficient of correlation and visual inspection, however, ANN performed better. Analyzing the factors through the connection weights of ANN reported population to be the significant factor contributing more to how energy is consumed globally. It is important to have policies that can influence population positively in order to have abundant supply of energy whenever there is demand for it.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114627386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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