Pub Date : 2017-12-02DOI: 10.1109/IEDM.2017.8268464
A. Casanova, Marie-Charline Blatché, F. Mathieu, L. Bettamin, H. Martin, D. Gonzalez-Dunia, L. Nicu, G. Larrieu
Our knowledge of the functioning of the central nervous system still remains scarce to date. A better understanding of its behavior, in either normal or diseased conditions, goes through an increased knowledge of basic mechanisms involved in neuronal function, including at the single cell resolution. In that scope, the miniaturization of electronic components and emergence of nano-biotechnology open new perspectives to follow neuronal activities at the single cell level. Here, we propose to co-integrate very high surface-to-volume ratio active (Fin-FETs) and passive devices (vertical nanowire-probes) on the same platform to monitor electrical activity of single mammalian neurons. Very high signal noise ratio has been demonstrated, especially in intracellular configuration (up to 80). The bio-platform was used to examine the effect of bio-chemical and electrical stimulations on neuronal activity.
{"title":"Integration of FinFETs and 3D nanoprobes devices on a common bio-platform for monitoring electrical activity of single neurons","authors":"A. Casanova, Marie-Charline Blatché, F. Mathieu, L. Bettamin, H. Martin, D. Gonzalez-Dunia, L. Nicu, G. Larrieu","doi":"10.1109/IEDM.2017.8268464","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268464","url":null,"abstract":"Our knowledge of the functioning of the central nervous system still remains scarce to date. A better understanding of its behavior, in either normal or diseased conditions, goes through an increased knowledge of basic mechanisms involved in neuronal function, including at the single cell resolution. In that scope, the miniaturization of electronic components and emergence of nano-biotechnology open new perspectives to follow neuronal activities at the single cell level. Here, we propose to co-integrate very high surface-to-volume ratio active (Fin-FETs) and passive devices (vertical nanowire-probes) on the same platform to monitor electrical activity of single mammalian neurons. Very high signal noise ratio has been demonstrated, especially in intracellular configuration (up to 80). The bio-platform was used to examine the effect of bio-chemical and electrical stimulations on neuronal activity.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116268588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-02DOI: 10.1109/IEDM.2017.8268502
J. Liang, R. Ramos, J. Dijon, H. Okuno, D. Kalita, D. Renaud, J. Lee, V. Georgiev, S. Berrada, T. Sadi, A. Asenov, B. Uhlig, K. Lilienthal, A. Dhavamani, F. Könemann, B. Gotsmann, G. Goncalves, B. Chen, K. Teo, R. Pandey, A. Todri-Sanial
We investigate, by combining physical and electrical measurements together with an atomistic-to-circuit modeling approach, the conductance of doped carbon nanotubes (CNTs) and their eligibility as possible candidate for next generation back-end-of-line (BEOL) interconnects. Ab-initio simulations predict a doping-related shift of the Fermi level, which reduces shell chirality variability and improves electrical conductance up to 90% by converting semiconducting shells to metallic. Circuit-level simulations predict up to 88% signal delay improvement with doped vs. pristine CNT. Electrical measurements of Pt-salt doped CNTs provide up to 50% of resistance reduction which is a milestone result for future CNT interconnect technology.
{"title":"A physics-based investigation of Pt-salt doped carbon nanotubes for local interconnects","authors":"J. Liang, R. Ramos, J. Dijon, H. Okuno, D. Kalita, D. Renaud, J. Lee, V. Georgiev, S. Berrada, T. Sadi, A. Asenov, B. Uhlig, K. Lilienthal, A. Dhavamani, F. Könemann, B. Gotsmann, G. Goncalves, B. Chen, K. Teo, R. Pandey, A. Todri-Sanial","doi":"10.1109/IEDM.2017.8268502","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268502","url":null,"abstract":"We investigate, by combining physical and electrical measurements together with an atomistic-to-circuit modeling approach, the conductance of doped carbon nanotubes (CNTs) and their eligibility as possible candidate for next generation back-end-of-line (BEOL) interconnects. Ab-initio simulations predict a doping-related shift of the Fermi level, which reduces shell chirality variability and improves electrical conductance up to 90% by converting semiconducting shells to metallic. Circuit-level simulations predict up to 88% signal delay improvement with doped vs. pristine CNT. Electrical measurements of Pt-salt doped CNTs provide up to 50% of resistance reduction which is a milestone result for future CNT interconnect technology.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115525660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-02DOI: 10.1109/IEDM.2017.8268473
S. Barraud, V. Lapras, B. Previtali, M. Samson, J. Lacord, S. Martinie, M. Jaud, S. Athanasiou, F. Triozon, O. Rozeau, J. Hartmann, C. Vizioz, C. Comboroure, F. Andrieu, J. Barbe, M. Vinet, T. Ernst
This paper presents recent progress on Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs. Key technological challenges will be discussed and recent research results presented. Width-dependent carrier mobility in Si NW/NS and FinFET will be analyzed, and intrinsic performance and design considerations of GAA structures will be discussed and compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options. The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power-performance optimization.
{"title":"Performance and design considerations for gate-all-around stacked-NanoWires FETs","authors":"S. Barraud, V. Lapras, B. Previtali, M. Samson, J. Lacord, S. Martinie, M. Jaud, S. Athanasiou, F. Triozon, O. Rozeau, J. Hartmann, C. Vizioz, C. Comboroure, F. Andrieu, J. Barbe, M. Vinet, T. Ernst","doi":"10.1109/IEDM.2017.8268473","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268473","url":null,"abstract":"This paper presents recent progress on Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs. Key technological challenges will be discussed and recent research results presented. Width-dependent carrier mobility in Si NW/NS and FinFET will be analyzed, and intrinsic performance and design considerations of GAA structures will be discussed and compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options. The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power-performance optimization.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"226 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130807021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268401
Y. Arai, T. Miyoshi, I. Kurachi
Silicon-On-Insulator (SOI) technology is a suitable choice to realize monolithic radiation imaging device as it involves a separate thick silicon layer in addition to a circuit layer. However, there are several issues to overcome for using radiation sensors and CMOS LSI circuits on a same die, i.e., the back-gate effect, coupling between sensors and circuits, and the total ionization dose (TID) effect. These issues have been solved by introducing a middle Si layer between the sensor and circuit layer (double SOI). The back-gate effect and the coupling are successfully suppressed and radiation hardness is increased by more than 100 kGy(Si) by introducing bias in the middle Si layer. In addition, a small pixel size is achieved by using the PMOS and NMOS active merge technique in SOI. This enables a much smaller layout size than that in the bulk CMOS process with the same feature size, while maintaining a high enough analog operation voltage. An example of a counting-type detector is also shown.
{"title":"SOI monolithic pixel technology for radiation image sensor","authors":"Y. Arai, T. Miyoshi, I. Kurachi","doi":"10.1109/IEDM.2017.8268401","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268401","url":null,"abstract":"Silicon-On-Insulator (SOI) technology is a suitable choice to realize monolithic radiation imaging device as it involves a separate thick silicon layer in addition to a circuit layer. However, there are several issues to overcome for using radiation sensors and CMOS LSI circuits on a same die, i.e., the back-gate effect, coupling between sensors and circuits, and the total ionization dose (TID) effect. These issues have been solved by introducing a middle Si layer between the sensor and circuit layer (double SOI). The back-gate effect and the coupling are successfully suppressed and radiation hardness is increased by more than 100 kGy(Si) by introducing bias in the middle Si layer. In addition, a small pixel size is achieved by using the PMOS and NMOS active merge technique in SOI. This enables a much smaller layout size than that in the bulk CMOS process with the same feature size, while maintaining a high enough analog operation voltage. An example of a counting-type detector is also shown.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121243958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268326
B. Gao, Huaqiang Wu, Wei Wu, Xiaohu Wang, Peng Yao, Yue Xi, Wenqiang Zhang, Ning Deng, Peng Huang, Xiaoyan Liu, Jinfeng Kang, Hong-Yu Chen, Shimeng Yu, H. Qian
Although bi-directional analog switching capability is crucial for neuromorphic computing application, it is still difficult to be realized in filamentary RRAM cells. This work investigates the physical mechanism of the abrupt switching to the analog switching transition using Kinetic Monte Carlo simulation method. A disorder-related model for oxygen vacancy distribution is proposed with an order parameter Oy to quantify the analog behaviors of different RRAM devices. The simulation results and model predictions are verified by experiments performed on 1kb RRAM array. It is suggested that disordered oxygen vacancy distribution is desired for analog switching. Optimization guideline for improving the analog performance of filamentary RRAM is provided.
{"title":"Modeling disorder effect of the oxygen vacancy distribution in filamentary analog RRAM for neuromorphic computing","authors":"B. Gao, Huaqiang Wu, Wei Wu, Xiaohu Wang, Peng Yao, Yue Xi, Wenqiang Zhang, Ning Deng, Peng Huang, Xiaoyan Liu, Jinfeng Kang, Hong-Yu Chen, Shimeng Yu, H. Qian","doi":"10.1109/IEDM.2017.8268326","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268326","url":null,"abstract":"Although bi-directional analog switching capability is crucial for neuromorphic computing application, it is still difficult to be realized in filamentary RRAM cells. This work investigates the physical mechanism of the abrupt switching to the analog switching transition using Kinetic Monte Carlo simulation method. A disorder-related model for oxygen vacancy distribution is proposed with an order parameter Oy to quantify the analog behaviors of different RRAM devices. The simulation results and model predictions are verified by experiments performed on 1kb RRAM array. It is suggested that disordered oxygen vacancy distribution is desired for analog switching. Optimization guideline for improving the analog performance of filamentary RRAM is provided.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124762024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268365
Reza M. Mohamadi, S. Kelley
Microscale analysis has facilitated significant progress towards the development of approaches that enable the capture of rare circulating tumor cells (CTCs) from the blood of cancer patients. This is a critical capability for noninvasive tumor profiling. These advances have allowed the capture and enumeration of CTCs with unique sensitivity. However, it has become clear that simply counting tumor cells cannot provide the information that could help to make significant clinical decisions. CTCs are heterogeneous and they can change as they enter the bloodstream. Therefore, profiling of CTCs at single cell level is critical to unraveling the complex and dynamic properties of these potential cancer markers.
{"title":"Microscale profiling of circulating tumor cells","authors":"Reza M. Mohamadi, S. Kelley","doi":"10.1109/IEDM.2017.8268365","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268365","url":null,"abstract":"Microscale analysis has facilitated significant progress towards the development of approaches that enable the capture of rare circulating tumor cells (CTCs) from the blood of cancer patients. This is a critical capability for noninvasive tumor profiling. These advances have allowed the capture and enumeration of CTCs with unique sensitivity. However, it has become clear that simply counting tumor cells cannot provide the information that could help to make significant clinical decisions. CTCs are heterogeneous and they can change as they enter the bloodstream. Therefore, profiling of CTCs at single cell level is critical to unraveling the complex and dynamic properties of these potential cancer markers.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122434389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268378
R. Huang, X. Jiang, S. Guo, P. Ren, P. Hao, Z. Yu, Z. Zhang, Y. Wang, R. Wang
Device variability and reliability are becoming increasingly important for nano-CMOS technology and circuits, due to the shrinking circuit design margin with the downscaling supply voltage (Vdd). Therefore, robust design should have the awareness of both variability and reliability. In FinFET technology, strong correlation between the variations of device electrical parameters is found, due to the larger impacts of line-edge roughness (LER) in FinFET structure. Accurate compact models and new design methodology for random variability in FinFETs were proposed for the variation-and correlation-aware design. For the reliability awareness, the impacts of BTI-induced temporal shift and the layout dependent aging effects should be taken into account for the optimization of end-of-life (EOL) performance/power/area (PPA). New-generation aging model and circuit reliability simulator for FinFETs were proposed and developed in industry-standard EDA tools. Future challenges are also pointed out, such as statistical BTI and RTN. The results are helpful for the robust and resilient design for 16/14nm and beyond.
{"title":"Variability-and reliability-aware design for 16/14nm and beyond technology","authors":"R. Huang, X. Jiang, S. Guo, P. Ren, P. Hao, Z. Yu, Z. Zhang, Y. Wang, R. Wang","doi":"10.1109/IEDM.2017.8268378","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268378","url":null,"abstract":"Device variability and reliability are becoming increasingly important for nano-CMOS technology and circuits, due to the shrinking circuit design margin with the downscaling supply voltage (Vdd). Therefore, robust design should have the awareness of both variability and reliability. In FinFET technology, strong correlation between the variations of device electrical parameters is found, due to the larger impacts of line-edge roughness (LER) in FinFET structure. Accurate compact models and new design methodology for random variability in FinFETs were proposed for the variation-and correlation-aware design. For the reliability awareness, the impacts of BTI-induced temporal shift and the layout dependent aging effects should be taken into account for the optimization of end-of-life (EOL) performance/power/area (PPA). New-generation aging model and circuit reliability simulator for FinFETs were proposed and developed in industry-standard EDA tools. Future challenges are also pointed out, such as statistical BTI and RTN. The results are helpful for the robust and resilient design for 16/14nm and beyond.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122625816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268359
D. Ji, C. Gupta, Silvia H. Chan, Anchal Agarwal, Wenwen Li, S. Keller, U. Mishra, S. Chowdhury
A normally off (Vth = 4.7 V) vertical GaN OG-FET with a 10 nm UID-GaN channel interlayer and a 50 nm in-situ Al2O3 gate dielectric has been successfully demonstrated and scaled for higher current operation. By using a novel double field-plated structure for mitigating peak electric field, a high off-state breakdown voltage over 1.4 kV was achieved with a low specific on-state resistance (RON, SP) of 2.2 mΩ.cm2. The MOCVD regrown 10 nm GaN channel interlayer enabled a channel resistance lower than 10 Qmm and an average channel electron mobility of 185 cm2/Vs. The fabricated large-area transistor with a total area of 400 μm × 500 μm offered a breakdown voltage of 900 V and an on-state resistance (Ron) of 4.1 Q. Results indicate the potential of vertical GaN OG-FETs for over kV range of power electronics applications.
{"title":"Demonstrating >1.4 kV OG-FET performance with a novel double field-plated geometry and the successful scaling of large-area devices","authors":"D. Ji, C. Gupta, Silvia H. Chan, Anchal Agarwal, Wenwen Li, S. Keller, U. Mishra, S. Chowdhury","doi":"10.1109/IEDM.2017.8268359","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268359","url":null,"abstract":"A normally off (V<inf>th</inf> = 4.7 V) vertical GaN OG-FET with a 10 nm UID-GaN channel interlayer and a 50 nm in-situ Al<inf>2</inf>O<inf>3</inf> gate dielectric has been successfully demonstrated and scaled for higher current operation. By using a novel double field-plated structure for mitigating peak electric field, a high off-state breakdown voltage over 1.4 kV was achieved with a low specific on-state resistance (RON, SP) of 2.2 mΩ.cm<sup>2</sup>. The MOCVD regrown 10 nm GaN channel interlayer enabled a channel resistance lower than 10 Qmm and an average channel electron mobility of 185 cm<sup>2</sup>/Vs. The fabricated large-area transistor with a total area of 400 μm × 500 μm offered a breakdown voltage of 900 V and an on-state resistance (R<inf>on</inf>) of 4.1 Q. Results indicate the potential of vertical GaN OG-FETs for over kV range of power electronics applications.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122945593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268428
F. Andrieu, R. Berthelon, R. Boumchedda, G. Tricaud, L. Brunet, P. Batude, B. Mathieu, E. Avelar, A. A. de Sousa, G. Cibrario, O. Rozeau, J. Lacord, O. Billoint, C. Fenouillet-Béranger, S. Guissi, D. Fried, P. Morin, J. Noel, B. Giraud, S. Thuries, F. Arnaud, M. Vinet
We have fabricated 3D-monolithic transistors on two tiers. We experimentally evidence the asymmetric double-gate (DG) behavior of a top-tier transistor, resulting in a better ON-state current (Ion) / OFF-state current (Ioff) tradeoff than in single-gate (SG) mode. Moreover, a 3D-shared contact between a top and bottom electrode is experimentally demonstrated; paving the way for a local back gate, possibly connected with the top gate by a 3D-shared contact. Assuming such a construct, we have performed extensive layout and spice simulations of standard cells and SRAMs. We evidence that the back-gate overlap on the source and drain must be minimized to mitigate the parasitic capacitances. The best layout configurations of a loaded 1-finger inverter yields a 24% frequency gain at a given static power and Vdd = 0.6V supply voltage, compared to SG, or to a static power divided by 5, compared to SG under Forward Body Bias (FBB). These performance boosts may be obtained without any area penalty and assuming a 20nm-thin BOX. Similarly, a 29% improvement of the read and write currents of 6T SRAMs is contemplated at Vdd = 0.8V. Such new functionality provided by 3D-monolithic even enables making 4T SRAMs that are fully functional at Vdd = 0.8V by improving their retention and, in turn, the maximum number of bitcells per column from 50 (SG) to 300 with a dynamic back-bias.
{"title":"Design technology co-optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation","authors":"F. Andrieu, R. Berthelon, R. Boumchedda, G. Tricaud, L. Brunet, P. Batude, B. Mathieu, E. Avelar, A. A. de Sousa, G. Cibrario, O. Rozeau, J. Lacord, O. Billoint, C. Fenouillet-Béranger, S. Guissi, D. Fried, P. Morin, J. Noel, B. Giraud, S. Thuries, F. Arnaud, M. Vinet","doi":"10.1109/IEDM.2017.8268428","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268428","url":null,"abstract":"We have fabricated 3D-monolithic transistors on two tiers. We experimentally evidence the asymmetric double-gate (DG) behavior of a top-tier transistor, resulting in a better ON-state current (Ion) / OFF-state current (Ioff) tradeoff than in single-gate (SG) mode. Moreover, a 3D-shared contact between a top and bottom electrode is experimentally demonstrated; paving the way for a local back gate, possibly connected with the top gate by a 3D-shared contact. Assuming such a construct, we have performed extensive layout and spice simulations of standard cells and SRAMs. We evidence that the back-gate overlap on the source and drain must be minimized to mitigate the parasitic capacitances. The best layout configurations of a loaded 1-finger inverter yields a 24% frequency gain at a given static power and Vdd = 0.6V supply voltage, compared to SG, or to a static power divided by 5, compared to SG under Forward Body Bias (FBB). These performance boosts may be obtained without any area penalty and assuming a 20nm-thin BOX. Similarly, a 29% improvement of the read and write currents of 6T SRAMs is contemplated at Vdd = 0.8V. Such new functionality provided by 3D-monolithic even enables making 4T SRAMs that are fully functional at Vdd = 0.8V by improving their retention and, in turn, the maximum number of bitcells per column from 50 (SG) to 300 with a dynamic back-bias.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114145217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268438
Jingyun Zhang, T. Ando, C. Yeung, Miaomiao Wang, O. Kwon, R. Galatage, R. Chao, N. Loubet, B. Moon, R. Bao, R. Vega, Juntao Li, Chen Zhang, Zuoguang Liu, M. Kang, Xin He Miao, Junli Wang, S. Kanakasabapathy, V. Basker, H. Jagannathan, T. Yamashita
In this paper, we report multi-threshold-voltage (multi-Vt) options for stacked Nanosheet gate-all-around (GAA) transistors. Vt can be modulated through workfunction metal (WFM) thickness as well as the inter-nanosheet spacing (Tsus), the combination of which may be leveraged to increase the number of undoped Vt offerings within a CMOS device menu relative to a FinFET CMOS device menu, which fundamentally does not have Tsus as a Vt tuning option. Hence we propose our multi-Vt scheme by taking advantage of the unique structure of stacked GAA transistor.
{"title":"High-k metal gate fundamental learning and multi-Vt options for stacked nanosheet gate-all-around transistor","authors":"Jingyun Zhang, T. Ando, C. Yeung, Miaomiao Wang, O. Kwon, R. Galatage, R. Chao, N. Loubet, B. Moon, R. Bao, R. Vega, Juntao Li, Chen Zhang, Zuoguang Liu, M. Kang, Xin He Miao, Junli Wang, S. Kanakasabapathy, V. Basker, H. Jagannathan, T. Yamashita","doi":"10.1109/IEDM.2017.8268438","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268438","url":null,"abstract":"In this paper, we report multi-threshold-voltage (multi-Vt) options for stacked Nanosheet gate-all-around (GAA) transistors. V<inf>t</inf> can be modulated through workfunction metal (WFM) thickness as well as the inter-nanosheet spacing (T<inf>sus</inf>), the combination of which may be leveraged to increase the number of undoped V<inf>t</inf> offerings within a CMOS device menu relative to a FinFET CMOS device menu, which fundamentally does not have T<inf>sus</inf> as a V<inf>t</inf> tuning option. Hence we propose our multi-V<inf>t</inf> scheme by taking advantage of the unique structure of stacked GAA transistor.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"27 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121896018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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