Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268463
C. Prinz
III-V nanowires have tunable dimensions, between 40 nm and 100 nm in diameter and between 1 and 15 μm in length. Due to their small diameter, they are ideal candidates to interact with cells without detrimental effects on the cell viability. Nanowires can be used as sensors: in our case, we have shown that arrays of vertical gallium phosphide nanowires are promising materials for biosensing in membranes, neural implant development as well as for cellular mechanosensing. Moreover, due to the exceptional control one can achieve during synthesis over their geometrical and optical properties, III-V nanowires are ideal materials to investigate the interactions of high aspect ratio nanoparticles with living cells and tissue.
{"title":"Interactions of nanowires with cells and tissue","authors":"C. Prinz","doi":"10.1109/IEDM.2017.8268463","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268463","url":null,"abstract":"III-V nanowires have tunable dimensions, between 40 nm and 100 nm in diameter and between 1 and 15 μm in length. Due to their small diameter, they are ideal candidates to interact with cells without detrimental effects on the cell viability. Nanowires can be used as sensors: in our case, we have shown that arrays of vertical gallium phosphide nanowires are promising materials for biosensing in membranes, neural implant development as well as for cellular mechanosensing. Moreover, due to the exceptional control one can achieve during synthesis over their geometrical and optical properties, III-V nanowires are ideal materials to investigate the interactions of high aspect ratio nanoparticles with living cells and tissue.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114904779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268440
Heng Wu, S. Seo, C. Niu, W. Wang, G. Tsutsui, O. Gluschenkov, Zuoguang Liu, A. Petrescu, A. Carr, Samuel S. Choi, S. Tsai, Chanro Park, I. Seshadri, Anuja Desilva, A. Arceo, George Yang, M. Sankarapandian, C. Prindle, K. Akarvardar, C. Durfee, Jie Yang, P. Adusumilli, Bruce Miao, J. Strane, W. Kleemeier, M. Raymond, K. Choi, F. Lie, T. Yamashita, A. Knorr, D. Gupta, D. Guo, R. Divakaruni, H. Bu, M. Khare
In this study, a manufacturable CMOS dual solid phase epitaxy (SPE) process with pc < 2.2×10−9 Q-cm2 on both NFET and PFET is demonstrated on the hardware with 7nm ground rule. Contact resistivity reduction strategies of both the conventional approach of high in-situ doped epi and the novel SPE processes are systematically studied on device and ring oscillator (RO) level. Clear improvement in the RO delay is accomplished by the novel dual SPE process on the CMOS flow. Stronger performance benefit is demonstrated with smaller contact sizes towards future CMOS technology nodes.
{"title":"Integrated dual SPE processes with low contact resistivity for future CMOS technologies","authors":"Heng Wu, S. Seo, C. Niu, W. Wang, G. Tsutsui, O. Gluschenkov, Zuoguang Liu, A. Petrescu, A. Carr, Samuel S. Choi, S. Tsai, Chanro Park, I. Seshadri, Anuja Desilva, A. Arceo, George Yang, M. Sankarapandian, C. Prindle, K. Akarvardar, C. Durfee, Jie Yang, P. Adusumilli, Bruce Miao, J. Strane, W. Kleemeier, M. Raymond, K. Choi, F. Lie, T. Yamashita, A. Knorr, D. Gupta, D. Guo, R. Divakaruni, H. Bu, M. Khare","doi":"10.1109/IEDM.2017.8268440","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268440","url":null,"abstract":"In this study, a manufacturable CMOS dual solid phase epitaxy (SPE) process with pc < 2.2×10−9 Q-cm2 on both NFET and PFET is demonstrated on the hardware with 7nm ground rule. Contact resistivity reduction strategies of both the conventional approach of high in-situ doped epi and the novel SPE processes are systematically studied on device and ring oscillator (RO) level. Clear improvement in the RO delay is accomplished by the novel dual SPE process on the CMOS flow. Stronger performance benefit is demonstrated with smaller contact sizes towards future CMOS technology nodes.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116909182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268306
Lisa T. Su, S. Naffziger, M. Papermaster
Datacenter and high-performance computing capabilities have continued their exponential improvements in performance over the prior decade, driven by the proliferation of devices and data through the internet of things (IoT), and new applications in the enterprise and cloud. This trend will continue over the next decade as the demand for compute performance continues to grow with exabytes of data being created daily and new use models incorporating machine learning and artificial intelligence become more prevalent. As Moore's Law has slowed in recent years, numerous techniques including system, architectural and software innovation have been used to extend the high-performance processor performance improvements. We examine these techniques and demonstrate that although some of these will continue, new innovations are needed especially at the system level to continue the performance trend over the next decade. We believe that multi-chip technologies and system level innovations are key to unlocking the performance gains in computing over the next decade.
{"title":"Multi-chip technologies to unleash computing performance gains over the next decade","authors":"Lisa T. Su, S. Naffziger, M. Papermaster","doi":"10.1109/IEDM.2017.8268306","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268306","url":null,"abstract":"Datacenter and high-performance computing capabilities have continued their exponential improvements in performance over the prior decade, driven by the proliferation of devices and data through the internet of things (IoT), and new applications in the enterprise and cloud. This trend will continue over the next decade as the demand for compute performance continues to grow with exabytes of data being created daily and new use models incorporating machine learning and artificial intelligence become more prevalent. As Moore's Law has slowed in recent years, numerous techniques including system, architectural and software innovation have been used to extend the high-performance processor performance improvements. We examine these techniques and demonstrate that although some of these will continue, new innovations are needed especially at the system level to continue the performance trend over the next decade. We believe that multi-chip technologies and system level innovations are key to unlocking the performance gains in computing over the next decade.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116183458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268387
D. Edelstein
This year marks the 20th anniversary of IBM's announcement of its impending plans to insert CMOS/Cu BEOL technology into production, and its having shipped the first functional CPU prototypes. The subsequent manufacturing ramp in mid-1998 provided the first commercial IC chips with Cu BEOL. This invited paper covers the timeline of this technology, with its key defining elements, subsequent innovations, and likely future directions. The original, basic features of this technology have endured to this day, though with many evolutionary improvements. But now, in its 10th generation of manufacturing, and 12th in research, we are finally seeing changes beyond evolutionary. The replacement of Cu metal for the finest wiring levels may occur over the next 1–3 nodes.
{"title":"20 Years of Cu BEOL in manufacturing, and its future prospects","authors":"D. Edelstein","doi":"10.1109/IEDM.2017.8268387","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268387","url":null,"abstract":"This year marks the 20th anniversary of IBM's announcement of its impending plans to insert CMOS/Cu BEOL technology into production, and its having shipped the first functional CPU prototypes. The subsequent manufacturing ramp in mid-1998 provided the first commercial IC chips with Cu BEOL. This invited paper covers the timeline of this technology, with its key defining elements, subsequent innovations, and likely future directions. The original, basic features of this technology have endured to this day, though with many evolutionary improvements. But now, in its 10th generation of manufacturing, and 12th in research, we are finally seeing changes beyond evolutionary. The replacement of Cu metal for the finest wiring levels may occur over the next 1–3 nodes.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"66 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116283346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268468
Wei-Hao Chen, W. Lin, Li-Ya Lai, Shuangchen Li, Chien-Hua Hsu, Huan-Ting Lin, Heng-Yuan Lee, Jian-Wei Su, Yuan Xie, S. Sheu, Meng-Fan Chang
Recent ReRAM devices enable the development of computing-in-memory (CIM) for beyond von Neumann structure. However, wide distribution in ReRAM resistance (R) causes low yield for CIM operations. This work proposes a dual-mode computing (DMc) ReRAM macro structure with a dual-function voltage-mode self-write termination (DV-SWT) scheme to achieve both memory and fundamental CIM functions (AND, OR and XOR operations) with high yield. The DV-SWT increases the read margin for CIM operations by suppressing the R-variations caused by macro-level IR-drop and process variations. A 16Mb DMc-ReRAM full-function macro was fabricated using 1T1R HfO ReRAM devices and 0.15um CMOS process. The measured delay of the CIM operations is less than 14ns, which is 86+x faster than previous ReRAM-based CIM works. This work also represents the first CIM ReRAM macro with ReRAM device and CIM-peripheral circuits fully integrated on the same die.
{"title":"A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme","authors":"Wei-Hao Chen, W. Lin, Li-Ya Lai, Shuangchen Li, Chien-Hua Hsu, Huan-Ting Lin, Heng-Yuan Lee, Jian-Wei Su, Yuan Xie, S. Sheu, Meng-Fan Chang","doi":"10.1109/IEDM.2017.8268468","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268468","url":null,"abstract":"Recent ReRAM devices enable the development of computing-in-memory (CIM) for beyond von Neumann structure. However, wide distribution in ReRAM resistance (R) causes low yield for CIM operations. This work proposes a dual-mode computing (DMc) ReRAM macro structure with a dual-function voltage-mode self-write termination (DV-SWT) scheme to achieve both memory and fundamental CIM functions (AND, OR and XOR operations) with high yield. The DV-SWT increases the read margin for CIM operations by suppressing the R-variations caused by macro-level IR-drop and process variations. A 16Mb DMc-ReRAM full-function macro was fabricated using 1T1R HfO ReRAM devices and 0.15um CMOS process. The measured delay of the CIM operations is less than 14ns, which is 86+x faster than previous ReRAM-based CIM works. This work also represents the first CIM ReRAM macro with ReRAM device and CIM-peripheral circuits fully integrated on the same die.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125875620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268329
D. Resnati, A. Mannara, G. Nicosia, G. M. Paolucci, P. Tessariol, A. L. Lacaita, Alessandro S. Spinelli, C. M. Compagnoni
In this work, we present the first statistical analysis of the temperature activation of the string current in vertical-channel NAND Flash arrays. To this aim, a 3-Dimensional (3-D) TCAD model for current transport through the thin polysilicon channel of NAND strings is developed and calibrated against experimental data over a wide temperature range. This calibration allows to highlight the main features of current transport through the polysilicon grain boundaries as a function of the string current level and temperature, for different grain sizes. The model is then used to address the statistical dispersion of the temperature activation of the string current during read and of the temperature-induced shift of cell threshold-voltage (Vt) coming from the variability in the configuration of the polysilicon grains. Results reveal that this variability represents a nonnegligible source of statistical broadening for the cell Vt distribution when changing the array temperature.
{"title":"Temperature activation of the string current and its variability in 3-D NAND flash arrays","authors":"D. Resnati, A. Mannara, G. Nicosia, G. M. Paolucci, P. Tessariol, A. L. Lacaita, Alessandro S. Spinelli, C. M. Compagnoni","doi":"10.1109/IEDM.2017.8268329","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268329","url":null,"abstract":"In this work, we present the first statistical analysis of the temperature activation of the string current in vertical-channel NAND Flash arrays. To this aim, a 3-Dimensional (3-D) TCAD model for current transport through the thin polysilicon channel of NAND strings is developed and calibrated against experimental data over a wide temperature range. This calibration allows to highlight the main features of current transport through the polysilicon grain boundaries as a function of the string current level and temperature, for different grain sizes. The model is then used to address the statistical dispersion of the temperature activation of the string current during read and of the temperature-induced shift of cell threshold-voltage (Vt) coming from the variability in the configuration of the polysilicon grains. Results reveal that this variability represents a nonnegligible source of statistical broadening for the cell Vt distribution when changing the array temperature.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124863900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268483
A. Mallik, A. Vandooren, L. Witters, A. Walke, J. Franco, Y. Sherazi, P. Weckx, D. Yakimets, M. Bardon, B. Parvais, P. Debacker, B. W. Ku, S. Lim, A. Mocuta, D. Mocuta, J. Ryckaert, N. Collaert, P. Raghavan
The continued physical feature size scaling of CMOS transistors is experiencing asperities due to several factors (physical, technological, and economical), and it is expected to reach its boundary in the coming years. Sequential-3D (S3D) integration has been perceived as a promising alternative to continue the benefits offered by semiconductor scaling. This paper addresses the different variants of S3D integration and potential challenges to achieve a realizable solution. We analyze and quantify the benefits observed due to sequential scaling at a die level.
{"title":"The impact of sequential-3D integration on semiconductor scaling roadmap","authors":"A. Mallik, A. Vandooren, L. Witters, A. Walke, J. Franco, Y. Sherazi, P. Weckx, D. Yakimets, M. Bardon, B. Parvais, P. Debacker, B. W. Ku, S. Lim, A. Mocuta, D. Mocuta, J. Ryckaert, N. Collaert, P. Raghavan","doi":"10.1109/IEDM.2017.8268483","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268483","url":null,"abstract":"The continued physical feature size scaling of CMOS transistors is experiencing asperities due to several factors (physical, technological, and economical), and it is expected to reach its boundary in the coming years. Sequential-3D (S3D) integration has been perceived as a promising alternative to continue the benefits offered by semiconductor scaling. This paper addresses the different variants of S3D integration and potential challenges to achieve a realizable solution. We analyze and quantify the benefits observed due to sequential scaling at a die level.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130051390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268489
M. Hua, Jin Wei, Qilong Bao, Jiabei He, Zhaofu Zhang, Zheyang Zheng, Jiacheng Lei, K. J. Chen
With substantially limited holes generation, the E-mode n-channel LPCVD-SiNx/GaN MIS-FET delivers small NBTI (with Vds = 0 V and a negative Vgs = −30 V) even without a hole-barrier. In high reverse-bias (i.e. high drain bias off-state with Vgs < Vth and large Vds) stress, larger negative gate-bias is found to accelerate positive shift in Vth, suggesting a hole-induced gate dielectric degradation mechanism. It is also revealed that the hole-induced dielectric breakdown can be greatly contained when Vgs is limited to a few volts below Vth.
{"title":"Reverse-bias stability and reliability of hole-barrier-free E-mode LPCVD-SiNx/GaN MIS-FETs","authors":"M. Hua, Jin Wei, Qilong Bao, Jiabei He, Zhaofu Zhang, Zheyang Zheng, Jiacheng Lei, K. J. Chen","doi":"10.1109/IEDM.2017.8268489","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268489","url":null,"abstract":"With substantially limited holes generation, the E-mode n-channel LPCVD-SiNx/GaN MIS-FET delivers small NBTI (with V<inf>ds</inf> = 0 V and a negative V<inf>gs</inf> = −30 V) even without a hole-barrier. In high reverse-bias (i.e. high drain bias off-state with V<inf>gs</inf> < V<inf>th</inf> and large V<inf>ds</inf>) stress, larger negative gate-bias is found to accelerate positive shift in V<inf>th</inf>, suggesting a hole-induced gate dielectric degradation mechanism. It is also revealed that the hole-induced dielectric breakdown can be greatly contained when V<inf>gs</inf> is limited to a few volts below V<inf>th</inf>.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130147666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268486
E. Beyne, Soon-Wook Kim, Lan Peng, N. Heylen, J. De Messemaeker, O. O. Okudur, A. Phommahaxay, Tae-Gon Kim, M. Stucchi, D. Velenis, Andy Miller, G. Beyer
This paper presents a novel approach to face-to-face wafer-to-wafer (W2W) bonding using SiCN-to-SiCN dielectric bonding, in combination with direct Cu-Cu bonding using Cu pads of unequal size and surface topography for the top and bottom wafers. The use of SiCN dielectrics allows to obtain a high W2W bonding energy (> 2 J/m2) at low annealing temperature (250 °C). Excellent Cu-Cu bonding is obtained after annealing at 350 °C. A novel CMP process, resulting in a slightly protruding Cu top pad and a slightly recessed Cu bottom pad, is introduced. The difference in pad sizes, allows for the necessary W2W overlay bonding tolerances. Excellent resistivity and yield results are obtained across bonded 300 mm Si wafers for scaled 360 nm top pads bonded to 720 nm bottom pads at 1.44 μm pitch (25% bottom Cu density). Feasibility of smaller pitches has been demonstrated by successfully bonding 180 nm top pads to 540 nm bottom pads at 0.72 μm pitch.
{"title":"Scalable, sub 2μm pitch, Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology","authors":"E. Beyne, Soon-Wook Kim, Lan Peng, N. Heylen, J. De Messemaeker, O. O. Okudur, A. Phommahaxay, Tae-Gon Kim, M. Stucchi, D. Velenis, Andy Miller, G. Beyer","doi":"10.1109/IEDM.2017.8268486","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268486","url":null,"abstract":"This paper presents a novel approach to face-to-face wafer-to-wafer (W2W) bonding using SiCN-to-SiCN dielectric bonding, in combination with direct Cu-Cu bonding using Cu pads of unequal size and surface topography for the top and bottom wafers. The use of SiCN dielectrics allows to obtain a high W2W bonding energy (> 2 J/m2) at low annealing temperature (250 °C). Excellent Cu-Cu bonding is obtained after annealing at 350 °C. A novel CMP process, resulting in a slightly protruding Cu top pad and a slightly recessed Cu bottom pad, is introduced. The difference in pad sizes, allows for the necessary W2W overlay bonding tolerances. Excellent resistivity and yield results are obtained across bonded 300 mm Si wafers for scaled 360 nm top pads bonded to 720 nm bottom pads at 1.44 μm pitch (25% bottom Cu density). Feasibility of smaller pitches has been demonstrated by successfully bonding 180 nm top pads to 540 nm bottom pads at 0.72 μm pitch.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122339866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268391
N. Breil, D. Shemesh, J. Fernandez, R. Hung, N. Bekiaris, J. Tseng, M. Naik, J. H. Park, J. Bakke, A. Kumar, K. Nafisi, A. Litman, A. Karnieli, V. Kuchik, A. Wachs, N. Khasgiwale, M. Chudzik
Inline detection of embedded voids within Middle-Of-Line (MOL) cobalt metal lines is a major industry gap at 7nm technology node and below, for both developing the new metallization solutions, as well as for monitoring during ramp and production. We present a new non-destructive electron beam cobalt void detection method, leveraging an improved scanning electron microscope (SEM) imaging technique, which enable an accurate detection of voids embedded inside MOL metal trenches. After explaining the potential process mechanisms causing void formation, we introduce the e-beam technique, and demonstrate by simulation and experiments the correlation between the electron signal and the volume and depth of the voids. We conclude this paper by discussing how a defect inspection strategy using a massive metrology approach can lead to a faster and more efficient development of the Cobalt metallization.
{"title":"Electron beam detection of cobalt trench embedded voids enabling improved process control for Middle-Of-Line at the 7nm node and beyond","authors":"N. Breil, D. Shemesh, J. Fernandez, R. Hung, N. Bekiaris, J. Tseng, M. Naik, J. H. Park, J. Bakke, A. Kumar, K. Nafisi, A. Litman, A. Karnieli, V. Kuchik, A. Wachs, N. Khasgiwale, M. Chudzik","doi":"10.1109/IEDM.2017.8268391","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268391","url":null,"abstract":"Inline detection of embedded voids within Middle-Of-Line (MOL) cobalt metal lines is a major industry gap at 7nm technology node and below, for both developing the new metallization solutions, as well as for monitoring during ramp and production. We present a new non-destructive electron beam cobalt void detection method, leveraging an improved scanning electron microscope (SEM) imaging technique, which enable an accurate detection of voids embedded inside MOL metal trenches. After explaining the potential process mechanisms causing void formation, we introduce the e-beam technique, and demonstrate by simulation and experiments the correlation between the electron signal and the volume and depth of the voids. We conclude this paper by discussing how a defect inspection strategy using a massive metrology approach can lead to a faster and more efficient development of the Cobalt metallization.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130867992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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