Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268487
T. Tiwei, H. Oprins, V. Cherman, G. van der Plas, I. De Wolf, E. Beyne, M. Baelmans
A novel 3D-shaped polymer multi-jet impingement cooler based on low cost fabrication techniques is introduced for high performance applications. This paper presents the modeling study, design, fabrication, experimental characterization and benchmarking of this cooling concept, showing a very good thermal performance with low required pumping power.
{"title":"High efficiency direct liquid jet impingement cooling of high power devices using a 3D-shaped polymer cooler","authors":"T. Tiwei, H. Oprins, V. Cherman, G. van der Plas, I. De Wolf, E. Beyne, M. Baelmans","doi":"10.1109/IEDM.2017.8268487","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268487","url":null,"abstract":"A novel 3D-shaped polymer multi-jet impingement cooler based on low cost fabrication techniques is introduced for high performance applications. This paper presents the modeling study, design, fabrication, experimental characterization and benchmarking of this cooling concept, showing a very good thermal performance with low required pumping power.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128085660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268384
L. Selmi, E. Caruso, S. Carapezzi, M. Visciarelli, E. Gnani, N. Zagni, P. Pavan, P. Palestri, D. Esseni, A. Gnudi, S. Reggiani, F. Puglisi, G. Verzellesi
We review a few state of the art solutions and recent developments to model short channel III-V compound semiconductor n-MOSFETs based on full quantum transport, semiclassical multi-valley / multi-subband transport and TCAD models. The pros and cons of each, and the insights they can deliver, are illustrated with examples from recent technology developments and literature. Areas where improvements and implementations at TCAD level are most necessary are highlighted as well.
{"title":"Modelling nanoscale n-MOSFETs with III-V compound semiconductor channels: From advanced models for band structures, electrostatics and transport to TCAD","authors":"L. Selmi, E. Caruso, S. Carapezzi, M. Visciarelli, E. Gnani, N. Zagni, P. Pavan, P. Palestri, D. Esseni, A. Gnudi, S. Reggiani, F. Puglisi, G. Verzellesi","doi":"10.1109/IEDM.2017.8268384","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268384","url":null,"abstract":"We review a few state of the art solutions and recent developments to model short channel III-V compound semiconductor n-MOSFETs based on full quantum transport, semiclassical multi-valley / multi-subband transport and TCAD models. The pros and cons of each, and the insights they can deliver, are illustrated with examples from recent technology developments and literature. Areas where improvements and implementations at TCAD level are most necessary are highlighted as well.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132047611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268421
S. Tsuda, T. Saito, H. Nagase, Y. Kawashima, A. Yoshitomi, S. Okanishi, T. Hayashi, T. Maruyama, M. Inoue, S. Muranaka, S. Kato, T. Hagiwara, H. Saito, T. Yamaguchi, M. Kadoshima, T. Mihara, H. Yanagita, K. Sonoda, T. Yamashita, Y. Yamaguchi
Reliability and scalability of split-gate metal-oxide nitride oxide silicon (SG-MONOS) are discussed for 16/14nm-node embedded Flash in FinFET-era. FinFET SG-MONOS array is successfully operated with wide enough program/erase window. The Vth distribution of FinFET SG-MONOS array is kept tighter than planar even after retention. It is also demonstrated that Fin structure enables scaling of the control gate and the memory gate, which leads to the improvement of retention characteristics due to reduction of the mismatch of trapped carrier distribution during program/erase operation.
{"title":"Reliability and scalability of FinFET split-gate MONOS array with tight Vth distribution for 16/14nm-node embedded flash","authors":"S. Tsuda, T. Saito, H. Nagase, Y. Kawashima, A. Yoshitomi, S. Okanishi, T. Hayashi, T. Maruyama, M. Inoue, S. Muranaka, S. Kato, T. Hagiwara, H. Saito, T. Yamaguchi, M. Kadoshima, T. Mihara, H. Yanagita, K. Sonoda, T. Yamashita, Y. Yamaguchi","doi":"10.1109/IEDM.2017.8268421","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268421","url":null,"abstract":"Reliability and scalability of split-gate metal-oxide nitride oxide silicon (SG-MONOS) are discussed for 16/14nm-node embedded Flash in FinFET-era. FinFET SG-MONOS array is successfully operated with wide enough program/erase window. The Vth distribution of FinFET SG-MONOS array is kept tighter than planar even after retention. It is also demonstrated that Fin structure enables scaling of the control gate and the memory gate, which leads to the improvement of retention characteristics due to reduction of the mismatch of trapped carrier distribution during program/erase operation.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132231995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268323
S. Clima, B. Govoreanu, K. Opsomer, A. Velea, N. S. Avasarala, W. Devulder, I. Shlyakhov, G. Donadio, T. Witters, S. Kundu, L. Goux, V. Afanasiev, G. Kar, G. Pourtois
We investigate the electronic structure and defects of GexSe1−x materials at the atomic level, using full-layer-thickness (5nm) amorphous models. In Ge-rich GexSe1−x, the nature of the mobility gap defects is mostly related to miscoordinated Ge. The population/localization of mobility-gap states changes solely under the effect of electric field. Strong covalent bonds introduced by N doping in the material increase its thermal conductivity and crystallization temperature beyond 600C. C/N dopants are found to add/remove mobility-gap states in the doped systems. Our investigation sets guidelines for material design in view of improved electro-thermal device performance.
{"title":"Atomistic investigation of the electronic structure, thermal properties and conduction defects in Ge-rich GexSe1−x materials for selector applications","authors":"S. Clima, B. Govoreanu, K. Opsomer, A. Velea, N. S. Avasarala, W. Devulder, I. Shlyakhov, G. Donadio, T. Witters, S. Kundu, L. Goux, V. Afanasiev, G. Kar, G. Pourtois","doi":"10.1109/IEDM.2017.8268323","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268323","url":null,"abstract":"We investigate the electronic structure and defects of GexSe1−x materials at the atomic level, using full-layer-thickness (5nm) amorphous models. In Ge-rich GexSe1−x, the nature of the mobility gap defects is mostly related to miscoordinated Ge. The population/localization of mobility-gap states changes solely under the effect of electric field. Strong covalent bonds introduced by N doping in the material increase its thermal conductivity and crystallization temperature beyond 600C. C/N dopants are found to add/remove mobility-gap states in the doped systems. Our investigation sets guidelines for material design in view of improved electro-thermal device performance.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132313395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268498
M. Pala, O. Badami, D. Esseni
This paper presents the theory, implementation and application of a new quantum transport, NEGF based modelling approach employing a full-band Empirical Pseudopotential (EP) Hamiltonian. The use of a hybrid real-space/plane-waves basis results in a remarkable reduction of the computational burden compared to a full plane waves basis, which allowed us to obtain complete, self-consistent simulations for both FETs and Tunnel FETs in Si or in Ge, and with geometrical features in line with forthcoming CMOS technologies.
{"title":"NEGF based transport modelling with a full-band, pseudopotential Hamiltonian: Theory, implementation and full device simulations","authors":"M. Pala, O. Badami, D. Esseni","doi":"10.1109/IEDM.2017.8268498","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268498","url":null,"abstract":"This paper presents the theory, implementation and application of a new quantum transport, NEGF based modelling approach employing a full-band Empirical Pseudopotential (EP) Hamiltonian. The use of a hybrid real-space/plane-waves basis results in a remarkable reduction of the computational burden compared to a full plane waves basis, which allowed us to obtain complete, self-consistent simulations for both FETs and Tunnel FETs in Si or in Ge, and with geometrical features in line with forthcoming CMOS technologies.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131031568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268479
Jiahao Kang, W. Cao, Arnab K. Pal, S. Pandey, Steve Kramer, R. Hill, G. Sandhu, K. Banerjee
Gate-induced drain leakage (GIDL) is one of the main leakage mechanisms in field-effect transistors (FETs), especially access transistors that are widely employed in a variety of memory technologies. In this work, GIDL in emerging two-dimensional (2D) FETs is evaluated for the first time, by employing a novel dissipative quantum transport methodology based on Büttiker probes with band-to-band tunneling capability. It is shown that 2D semiconductors with relatively large bandgaps and favorable effective masses compared to that of silicon can greatly reduce GIDL, which is a compelling reason for using such materials in future memory technologies. Materials and device design considerations are discussed for minimizing the GIDL current. This work also provides guidelines for performance/scalability analysis of low-leakage applications of 2D FETs.
{"title":"Computational study of gate-induced drain leakage in 2D-semiconductor field-effect transistors","authors":"Jiahao Kang, W. Cao, Arnab K. Pal, S. Pandey, Steve Kramer, R. Hill, G. Sandhu, K. Banerjee","doi":"10.1109/IEDM.2017.8268479","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268479","url":null,"abstract":"Gate-induced drain leakage (GIDL) is one of the main leakage mechanisms in field-effect transistors (FETs), especially access transistors that are widely employed in a variety of memory technologies. In this work, GIDL in emerging two-dimensional (2D) FETs is evaluated for the first time, by employing a novel dissipative quantum transport methodology based on Büttiker probes with band-to-band tunneling capability. It is shown that 2D semiconductors with relatively large bandgaps and favorable effective masses compared to that of silicon can greatly reduce GIDL, which is a compelling reason for using such materials in future memory technologies. Materials and device design considerations are discussed for minimizing the GIDL current. This work also provides guidelines for performance/scalability analysis of low-leakage applications of 2D FETs.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132949849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268521
Saurabh Kumar, M. Cho, L. Everson, Hoonki Kim, Qianying Tang, Paul R. Mazanec, P. Meinerzhagen, Andres F. Malavasi, D. Lake, Carlos Tokunaga, M. Khellah, J. Tschanz, S. Borkar, V. De, C. Kim
This paper describes a 14nm test chip employing a novel NAND/NOR readout chain for characterizing soft error rate (SER) in combinational logic gates. The proposed test structure uses high density standard logic gates as detection circuit for sensing Single Event Transients (SETs) that are then forwarded to a skewed NAND-NOR readout chain which funnels all SET pulses while expanding the pulse width to ensure they reach the final triple modular redundant (TMR) counter. The proposed circuit is compact, has a scalable architecture based on a unit cell layout, and incurs minimal area overhead. Different gate configurations (device size, threshold voltage, fan-out and chain length) were implemented in the 14nm test-chip and irradiated under a neutron beam to collect a massive amount of statistical data. Radiation data captures, for the first time, the impact of various circuit parameters on combinational logic SER in 14nm tri-gate technology.
{"title":"An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits","authors":"Saurabh Kumar, M. Cho, L. Everson, Hoonki Kim, Qianying Tang, Paul R. Mazanec, P. Meinerzhagen, Andres F. Malavasi, D. Lake, Carlos Tokunaga, M. Khellah, J. Tschanz, S. Borkar, V. De, C. Kim","doi":"10.1109/IEDM.2017.8268521","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268521","url":null,"abstract":"This paper describes a 14nm test chip employing a novel NAND/NOR readout chain for characterizing soft error rate (SER) in combinational logic gates. The proposed test structure uses high density standard logic gates as detection circuit for sensing Single Event Transients (SETs) that are then forwarded to a skewed NAND-NOR readout chain which funnels all SET pulses while expanding the pulse width to ensure they reach the final triple modular redundant (TMR) counter. The proposed circuit is compact, has a scalable architecture based on a unit cell layout, and incurs minimal area overhead. Different gate configurations (device size, threshold voltage, fan-out and chain length) were implemented in the 14nm test-chip and irradiated under a neutron beam to collect a massive amount of statistical data. Radiation data captures, for the first time, the impact of various circuit parameters on combinational logic SER in 14nm tri-gate technology.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132586270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268497
M. Notomi, K. Nozaki, A. Shinya, M. Takiguchi
We review our recent achievements in various energy-efficient nanophotonic devices based on photonic crystals. Strong light confinement of photonic crystals enables large enhancement of light-matter interactions and ultrasmall capacitance for OE/EO conversion devices. Owing to these two features, we have demonstrated that the energy consumption of photonic devices can be reduced down to fJ/bit or less. This achievement may suggest energy-efficient optical link in a processor chip, and even opportunity for ultrasmall latency optoelectronic computations.
{"title":"Femto-joule-per-bit integrated nanophotonics and challenge for optical computation","authors":"M. Notomi, K. Nozaki, A. Shinya, M. Takiguchi","doi":"10.1109/IEDM.2017.8268497","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268497","url":null,"abstract":"We review our recent achievements in various energy-efficient nanophotonic devices based on photonic crystals. Strong light confinement of photonic crystals enables large enhancement of light-matter interactions and ultrasmall capacitance for OE/EO conversion devices. Owing to these two features, we have demonstrated that the energy consumption of photonic devices can be reduced down to fJ/bit or less. This achievement may suggest energy-efficient optical link in a processor chip, and even opportunity for ultrasmall latency optoelectronic computations.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128904157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268509
C. Lee, S. Mochizuki, R. Southwick, J. Li, Xin He Miao, R. Bao, T. Ando, R. Galatage, S. Siddiqui, C. Labelle, A. Knorr, J. Stathis, D. Guo, V. Narayanan, B. Haran, H. Jagannathan
Strained Si1−x Gex channel pFinFETs and planar pFETs are fabricated on a strain relaxed buffer virtual substrate to comparatively study the electrical impact of strain and Ge content in the Si1−xGex channel. By comparing the transistor electrical properties of Si1−xGex pFETs on SRB with Si1−xGex pFETs on Si substrate, we successfully decouple the influence of strain and Ge content in the Si1−x Gex channel on device performance such as gate stack quality, reliability, and carrier transport. Based on these understandings, dual channel Si/Si1−xGex FinFETs on the SRB with the optimized surface orientation is proposed to further improve the device performance.
{"title":"A comparative study of strain and Ge content in Si1−xGex channel using planar FETs, FinFETs, and strained relaxed buffer layer FinFETs","authors":"C. Lee, S. Mochizuki, R. Southwick, J. Li, Xin He Miao, R. Bao, T. Ando, R. Galatage, S. Siddiqui, C. Labelle, A. Knorr, J. Stathis, D. Guo, V. Narayanan, B. Haran, H. Jagannathan","doi":"10.1109/IEDM.2017.8268509","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268509","url":null,"abstract":"Strained Si<inf>1−x</inf> Ge<inf>x</inf> channel pFinFETs and planar pFETs are fabricated on a strain relaxed buffer virtual substrate to comparatively study the electrical impact of strain and Ge content in the Si<inf>1−x</inf>Ge<inf>x</inf> channel. By comparing the transistor electrical properties of Si<inf>1−x</inf>Ge<inf>x</inf> pFETs on SRB with Si<inf>1−x</inf>Ge<inf>x</inf> pFETs on Si substrate, we successfully decouple the influence of strain and Ge content in the Si<inf>1−x</inf> Ge<inf>x</inf> channel on device performance such as gate stack quality, reliability, and carrier transport. Based on these understandings, dual channel Si/Si<inf>1−x</inf>Ge<inf>x</inf> FinFETs on the SRB with the optimized surface orientation is proposed to further improve the device performance.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127723527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268369
V. Milo, Daniele Ielmini, Elisabetta Chicca
Attractor networks can realistically describe neurophysiological processes while providing useful computational modules for pattern recognition, signal restoration, and feature extraction. To implement attractor networks in small-area integrated circuits, the development of a hybrid technology including CMOS transistors and resistive switching memory (RRAM) is essential. This work presents a summary of recent results toward implementing RRAM-based attractor networks. Based on realistic models of HfO2 RRAM devices, we design and simulate recurrent networks showing the capability to train, recall and sustain attractors. The results support the feasibility of RRAM-based bio-realistic attractor networks.
{"title":"Attractor networks and associative memories with STDP learning in RRAM synapses","authors":"V. Milo, Daniele Ielmini, Elisabetta Chicca","doi":"10.1109/IEDM.2017.8268369","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268369","url":null,"abstract":"Attractor networks can realistically describe neurophysiological processes while providing useful computational modules for pattern recognition, signal restoration, and feature extraction. To implement attractor networks in small-area integrated circuits, the development of a hybrid technology including CMOS transistors and resistive switching memory (RRAM) is essential. This work presents a summary of recent results toward implementing RRAM-based attractor networks. Based on realistic models of HfO2 RRAM devices, we design and simulate recurrent networks showing the capability to train, recall and sustain attractors. The results support the feasibility of RRAM-based bio-realistic attractor networks.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115633263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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