Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268345
N. Parihar, R. Southwick, M. Wang, J. Stathis, S. Mahapatra
NBTI in Replacement Metal Gate (RMG) High-K Metal Gate (HKMG) SiGe p-FinFETs is modeled. Time kinetics for DC and AC stress and recovery, temperature (T) dependence of voltage acceleration factor (VAF), and impact of Ge% and N% are quantified. Benchmarking is done with Si p-FinFETs, and process (Ge%, N%) dependence is explained by TCAD and band structure calculations.
{"title":"Modeling of NBTI time kinetics and T dependence of VAF in SiGe p-FinFETs","authors":"N. Parihar, R. Southwick, M. Wang, J. Stathis, S. Mahapatra","doi":"10.1109/IEDM.2017.8268345","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268345","url":null,"abstract":"NBTI in Replacement Metal Gate (RMG) High-K Metal Gate (HKMG) SiGe p-FinFETs is modeled. Time kinetics for DC and AC stress and recovery, temperature (T) dependence of voltage acceleration factor (VAF), and impact of Ge% and N% are quantified. Benchmarking is done with Si p-FinFETs, and process (Ge%, N%) dependence is explained by TCAD and band structure calculations.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130241693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268460
M. D. Hodge, R. Vetury, S. Gibb, M. Winters, P. Patel, M. Mclain, Ya Shen, D. Kim, Joe Jech, K. Fallon, R. Houlden, D. Aichele, J. Shealy
5.24GHz bulk acoustic wave filters, utilizing undoped single crystal aluminum nitride, are reported. The filters had an absolute 4dB bandwidth of 151 MHz, a minimum insertion loss of 2.82 dB and rejection >38 dB. Resonators show k2eff of 6.32%, Qrnax of 1523, and FOM of 96.
{"title":"High rejection UNII 5.2GHz wideband bulk acoustic wave filters using undoped single crystal AlN-on-SiC resonators","authors":"M. D. Hodge, R. Vetury, S. Gibb, M. Winters, P. Patel, M. Mclain, Ya Shen, D. Kim, Joe Jech, K. Fallon, R. Houlden, D. Aichele, J. Shealy","doi":"10.1109/IEDM.2017.8268460","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268460","url":null,"abstract":"5.24GHz bulk acoustic wave filters, utilizing undoped single crystal aluminum nitride, are reported. The filters had an absolute 4dB bandwidth of 151 MHz, a minimum insertion loss of 2.82 dB and rejection >38 dB. Resonators show k<sup>2</sup><inf>eff</inf> of 6.32%, Q<inf>rnax</inf> of 1523, and FOM of 96.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130425308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268332
Xuejun Xie, Jiahao Kang, Y. Gong, P. Ajayan, K. Banerjee
Memristive devices with short-term plasticity (STP), gate tunability, site controllability, and light sensitivity have generated significant interest for wide range of applications, especially mimicking the neural network. However, there is still no memristive device that can accomplish all those goals in tandem at room temperature. To fill that void, in this work, lT-phase quantum dot superlattice is created on 2H-phase monolayer single crystal molybdenum disulfide (MoS2) back-gated field-effect transistor by focused electron beam irradiation. The quantum dots work as charge traps that induce memristive resistance. The memristive resistance can be controlled by applying gate bias and shows STP to light stimulation. Thus, this work demonstrates the first room temperature light sensitive memristive transistor that can serve as artificial retina device for artificial intelligence, and memristive receiver for optical-electrical neuromorphic interface.
{"title":"Room temperature 2D memristive transistor with optical short-term plasticity","authors":"Xuejun Xie, Jiahao Kang, Y. Gong, P. Ajayan, K. Banerjee","doi":"10.1109/IEDM.2017.8268332","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268332","url":null,"abstract":"Memristive devices with short-term plasticity (STP), gate tunability, site controllability, and light sensitivity have generated significant interest for wide range of applications, especially mimicking the neural network. However, there is still no memristive device that can accomplish all those goals in tandem at room temperature. To fill that void, in this work, lT-phase quantum dot superlattice is created on 2H-phase monolayer single crystal molybdenum disulfide (MoS2) back-gated field-effect transistor by focused electron beam irradiation. The quantum dots work as charge traps that induce memristive resistance. The memristive resistance can be controlled by applying gate bias and shows STP to light stimulation. Thus, this work demonstrates the first room temperature light sensitive memristive transistor that can serve as artificial retina device for artificial intelligence, and memristive receiver for optical-electrical neuromorphic interface.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127935947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268314
C. Ho, Shu-Cheng Chang, Chao-Yi Huang, Yu-cheng Chuang, S. Lim, Ming-Huei Hsieh, Shu-Cheng Chang, H. Liao
For the first time, this work demonstrated a 90nm 512Kb SPI HfO2-RRAM product vehicle successfully with reducing read / write power by 18X / 2X, boosting read / write speed by 5X / 10X, and scaling feature size by 2X, compared to presented 512Kb SPI EEPROM; while sustaining high reliability on million cycle endurance, even better post-cycle retention (85°C retention 100years for post 100K cycles), and 150°C high temperature operation, by optimized mismatching, read-integrity, relaxation, and noise as discussed in this work. Technology also offers alternative solution for greener, highly-reliable, and scaled NOR Flash applications. A new plasma dicing technology was implemented to further increase gross die per wafer.
{"title":"Integrated HfO2-RRAM to achieve highly reliable, greener, faster, cost-effective, and scaled devices","authors":"C. Ho, Shu-Cheng Chang, Chao-Yi Huang, Yu-cheng Chuang, S. Lim, Ming-Huei Hsieh, Shu-Cheng Chang, H. Liao","doi":"10.1109/IEDM.2017.8268314","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268314","url":null,"abstract":"For the first time, this work demonstrated a 90nm 512Kb SPI HfO2-RRAM product vehicle successfully with reducing read / write power by 18X / 2X, boosting read / write speed by 5X / 10X, and scaling feature size by 2X, compared to presented 512Kb SPI EEPROM; while sustaining high reliability on million cycle endurance, even better post-cycle retention (85°C retention 100years for post 100K cycles), and 150°C high temperature operation, by optimized mismatching, read-integrity, relaxation, and noise as discussed in this work. Technology also offers alternative solution for greener, highly-reliable, and scaled NOR Flash applications. A new plasma dicing technology was implemented to further increase gross die per wafer.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"29 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131669292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268377
Cheng Wang, Zhi Hu, G. Zhang, J. Holloway, R. Han
The high integration capability of silicon technologies, as well as the small wavelength of terahertz (THz) signals, make it possible to build a high-density, very-large-scale active THz array on a single chip. This is, however, very challenging in practice, due to the low device efficiency and large footprint of conventional circuit designs. To address these problems, we introduce a set of compact while versatile circuits, which utilize the multi-mode behaviors from structures with tight device-electromagnetic integration. These circuits have enabled large-scale (1) homogeneous arrays for high-power, collimated radiation, and (2) heterogeneous arrays for fast broadband spectral scanning. In particular, 0.1-mW power generation (20-mW effective isotropically-radiated power) at 1 THz, simultaneous transmit/receive capability, and high-parallelism molecular spectroscopy are demonstrated. New opportunities that these works bring about are also discussed.
{"title":"Large-scale terahertz active arrays in silicon using highly-versatile electromagnetic structures","authors":"Cheng Wang, Zhi Hu, G. Zhang, J. Holloway, R. Han","doi":"10.1109/IEDM.2017.8268377","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268377","url":null,"abstract":"The high integration capability of silicon technologies, as well as the small wavelength of terahertz (THz) signals, make it possible to build a high-density, very-large-scale active THz array on a single chip. This is, however, very challenging in practice, due to the low device efficiency and large footprint of conventional circuit designs. To address these problems, we introduce a set of compact while versatile circuits, which utilize the multi-mode behaviors from structures with tight device-electromagnetic integration. These circuits have enabled large-scale (1) homogeneous arrays for high-power, collimated radiation, and (2) heterogeneous arrays for fast broadband spectral scanning. In particular, 0.1-mW power generation (20-mW effective isotropically-radiated power) at 1 THz, simultaneous transmit/receive capability, and high-parallelism molecular spectroscopy are demonstrated. New opportunities that these works bring about are also discussed.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129217447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268443
V. Hu, P. Chiu, A. Sachid, C. Hu
The scaling potential of negative capacitance FinFET and FDSOI (NC-FinFET and NC-FDSOI) are studied for technology nodes down to 2nm. According to ITRS 2.0, FinFET scaling ends at 6/5nm node due to the scaling limits of fin width (6 nm Wfm) and FDSOI scaling ends at 11/10 nm due to scaling limit of the channel thickness (3 nm Tch). We present TCAD simulation evidence that using these Wfin and Tch, and negative capacitance enables FinFET and FDSOI scaling to 2 nm node. NC-FinFET and NC-FDSOI at 2 nm node show Ioff < 100nA/μm and 10%∼29% higher Ion compared with 2nm FinFET(97μA/μm Ioff) and FDSOI(46μA/μm Ioff). NC-FDSOI exhibits similarly strong back-gate bias effects on Ioff and Ion compared with FDSOI.
{"title":"Negative capacitance enables FinFET and FDSOI scaling to 2 nm node","authors":"V. Hu, P. Chiu, A. Sachid, C. Hu","doi":"10.1109/IEDM.2017.8268443","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268443","url":null,"abstract":"The scaling potential of negative capacitance FinFET and FDSOI (NC-FinFET and NC-FDSOI) are studied for technology nodes down to 2nm. According to ITRS 2.0, FinFET scaling ends at 6/5nm node due to the scaling limits of fin width (6 nm Wfm) and FDSOI scaling ends at 11/10 nm due to scaling limit of the channel thickness (3 nm Tch). We present TCAD simulation evidence that using these Wfin and Tch, and negative capacitance enables FinFET and FDSOI scaling to 2 nm node. NC-FinFET and NC-FDSOI at 2 nm node show Ioff < 100nA/μm and 10%∼29% higher Ion compared with 2nm FinFET(97μA/μm Ioff) and FDSOI(46μA/μm Ioff). NC-FDSOI exhibits similarly strong back-gate bias effects on Ioff and Ion compared with FDSOI.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126844243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268431
D. Prasad, S. Sinha, B. Cline, S. Moore, A. Naeemi
Faithful a priori estimation of system performance has long been the foundation for early device, circuit, and micro-architectural evaluation. For over two decades, Rent's power-law has been a popular modelling methodology for predicting interconnect characteristics of a system. However, with dimensional scaling, interconnects have become increasingly important, and the existing models do not provide accurate interconnect estimates; at worst, current Rent's-based models heavily under-estimate interconnect delay and power. At the same time, microprocessor designs are also evolving to cope with the rapidly changing technology landscape, which together can drastically influence the overall performance characteristics of the designs. For the first time, this paper argues the validity of Rent's method in the era of rapid technology and microprocessor-design advancements. A new approach to Rent's model is proposed which addresses the inability of the current Rent's approach to accurately capture the standard cell level characteristics and microprocessor characteristics that are inherent to the way we design microprocessors today. The proposed models are validated against a rich database of state-of-the-art commercial microprocessors at 14/16nm, 10nm and 7nm process nodes, and the results illustrate the importance of design-specific technology prediction.
{"title":"A novel performance model for state-of-the-art processors by modernization of Rent's rule","authors":"D. Prasad, S. Sinha, B. Cline, S. Moore, A. Naeemi","doi":"10.1109/IEDM.2017.8268431","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268431","url":null,"abstract":"Faithful a priori estimation of system performance has long been the foundation for early device, circuit, and micro-architectural evaluation. For over two decades, Rent's power-law has been a popular modelling methodology for predicting interconnect characteristics of a system. However, with dimensional scaling, interconnects have become increasingly important, and the existing models do not provide accurate interconnect estimates; at worst, current Rent's-based models heavily under-estimate interconnect delay and power. At the same time, microprocessor designs are also evolving to cope with the rapidly changing technology landscape, which together can drastically influence the overall performance characteristics of the designs. For the first time, this paper argues the validity of Rent's method in the era of rapid technology and microprocessor-design advancements. A new approach to Rent's model is proposed which addresses the inability of the current Rent's approach to accurately capture the standard cell level characteristics and microprocessor characteristics that are inherent to the way we design microprocessors today. The proposed models are validated against a rich database of state-of-the-art commercial microprocessors at 14/16nm, 10nm and 7nm process nodes, and the results illustrate the importance of design-specific technology prediction.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126513735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/iedm.2017.8268400
T. Nishihara, M. Matsumura, T. Imoto, K. Okumura, Y. Sakano, Y. Yorikado, Y. Tashiro, H. Wakabayashi, Y. Oike, Y. Nitta
This is the first reported non-electron-multiplying CMOS Image Sensor (CIS) photon-detector for replacing Photo Multiplier Tubes (PMT). 15jum pitch active sensor pixels with complete charge transfer and readout noise of 0.5 e-RMS are arrayed and their digital outputs are summed to detect micro light pulses. Successful proof of radiation counting is demonstrated.
{"title":"An experimental CMOS photon detector with 0.5e-RMS temporal noise and 15μm pitch active sensor pixels","authors":"T. Nishihara, M. Matsumura, T. Imoto, K. Okumura, Y. Sakano, Y. Yorikado, Y. Tashiro, H. Wakabayashi, Y. Oike, Y. Nitta","doi":"10.1109/iedm.2017.8268400","DOIUrl":"https://doi.org/10.1109/iedm.2017.8268400","url":null,"abstract":"This is the first reported non-electron-multiplying CMOS Image Sensor (CIS) photon-detector for replacing Photo Multiplier Tubes (PMT). 15jum pitch active sensor pixels with complete charge transfer and readout noise of 0.5 e-RMS are arrayed and their digital outputs are summed to detect micro light pulses. Successful proof of radiation counting is demonstrated.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121302998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268325
N. Shukla, R. Ghosh, B. Grisafe, S. Datta
We establish an active electrode (AE) selection criterion for volatile and non-volatile switching in metallic conducting bridge (CB) RAM, relevant to cross-point selector and memory applications. Using first principle calculations, we show that: (a) volatile versus non-volatile switching is determined by the energy difference A between the cluster configuration of the AE atoms in the high-resistance (HRS) state, and the filament configuration of the AE atoms in the low-resistance (LRS) state; volatile switching is achieved when A is large, whereas the system will exhibit non-volatile behavior when A ∼ 0; (b) the maximum LRS (ON-state) current, Imax that can be delivered while sustaining volatile (selector) operation is proportional to the magnitude of A for the AE. Using molecular dynamical (MD) + NEGF transport simulations, supported by experiments, we confirm the volatile (selector) switching characteristics of Ag/HfÖ2/Pt, and the non-volatile (memory) switching characteristics of Co/HfO2/Pt, as predicted by our criterion; the corresponding temporal characteristics are also evaluated. Finally, we calculate the expected switching characteristics for various active electrodes (AEs), showing excellent agreement with experimental results. Our findings enable the design of CBRAM-based selectors and memory with the required switching properties.
{"title":"Fundamental mechanism behind volatile and non-volatile switching in metallic conducting bridge RAM","authors":"N. Shukla, R. Ghosh, B. Grisafe, S. Datta","doi":"10.1109/IEDM.2017.8268325","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268325","url":null,"abstract":"We establish an active electrode (AE) selection criterion for volatile and non-volatile switching in metallic conducting bridge (CB) RAM, relevant to cross-point selector and memory applications. Using first principle calculations, we show that: (a) volatile versus non-volatile switching is determined by the energy difference A between the cluster configuration of the AE atoms in the high-resistance (HRS) state, and the filament configuration of the AE atoms in the low-resistance (LRS) state; volatile switching is achieved when A is large, whereas the system will exhibit non-volatile behavior when A ∼ 0; (b) the maximum LRS (ON-state) current, Imax that can be delivered while sustaining volatile (selector) operation is proportional to the magnitude of A for the AE. Using molecular dynamical (MD) + NEGF transport simulations, supported by experiments, we confirm the volatile (selector) switching characteristics of Ag/HfÖ2/Pt, and the non-volatile (memory) switching characteristics of Co/HfO2/Pt, as predicted by our criterion; the corresponding temporal characteristics are also evaluated. Finally, we calculate the expected switching characteristics for various active electrodes (AEs), showing excellent agreement with experimental results. Our findings enable the design of CBRAM-based selectors and memory with the required switching properties.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121630591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268466
Xin Zhu, Xiaowei Wang, Z. Cao, Zhi Ye, Chaoming Gu, Chuanghong Jin, Yang Liu
Nanopore devices integrated with ITO gate electrodes are fabricated, producing pore diameters <10nm and lengths ∼30nm. Translocation signals of λ-DNA reveal detailed signatures of various DNA folding states. The gate bias VG modulates the translocation events. As VG rises from −0.5V to 0.5V, the count of folded-once events increases by ∼5.5X relative to that of unfolded ones, indicating capability of electrically modulating the effective pore cross-section.
{"title":"Nanopores incorporating ITO electrodes for electrical gating of DNA at different folding states","authors":"Xin Zhu, Xiaowei Wang, Z. Cao, Zhi Ye, Chaoming Gu, Chuanghong Jin, Yang Liu","doi":"10.1109/IEDM.2017.8268466","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268466","url":null,"abstract":"Nanopore devices integrated with ITO gate electrodes are fabricated, producing pore diameters <10nm and lengths ∼30nm. Translocation signals of λ-DNA reveal detailed signatures of various DNA folding states. The gate bias V<inf>G</inf> modulates the translocation events. As V<inf>G</inf> rises from −0.5V to 0.5V, the count of folded-once events increases by ∼5.5X relative to that of unfolded ones, indicating capability of electrically modulating the effective pore cross-section.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122951185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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