Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268467
G. Pedretti, S. Bianchi, V. Milo, A. Calderoni, N. Ramaswamy, D. Ielmini
Brain-inspired computing is currently gaining momentum as a viable technology for artificial intelligence enabling recognition, language processing and online unsupervised learning. Brain-inspired circuit design is currently hindered by 2 fundamental limits: (i) understanding the event-driven spike processing in the human brain, and (ii) developing predictive models to design and optimize cognitive circuits. Here we present a comprehensive model for spiking neural networks based on spike-timing dependent plasticity (STDP) in resistive switching memory (RRAM) synapses. Both a Monte Carlo (MC) model and an analytical model are presented to describe experimental data from a state-of-the-art neuromorphic hardware. The model can predict the learning efficiency and time as a function of the input noise and pattern size, thus paving the way for model-based design of cognitive brain-like circuits.
{"title":"Modeling-based design of brain-inspired spiking neural networks with RRAM learning synapses","authors":"G. Pedretti, S. Bianchi, V. Milo, A. Calderoni, N. Ramaswamy, D. Ielmini","doi":"10.1109/IEDM.2017.8268467","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268467","url":null,"abstract":"Brain-inspired computing is currently gaining momentum as a viable technology for artificial intelligence enabling recognition, language processing and online unsupervised learning. Brain-inspired circuit design is currently hindered by 2 fundamental limits: (i) understanding the event-driven spike processing in the human brain, and (ii) developing predictive models to design and optimize cognitive circuits. Here we present a comprehensive model for spiking neural networks based on spike-timing dependent plasticity (STDP) in resistive switching memory (RRAM) synapses. Both a Monte Carlo (MC) model and an analytical model are presented to describe experimental data from a state-of-the-art neuromorphic hardware. The model can predict the learning efficiency and time as a function of the input noise and pattern size, thus paving the way for model-based design of cognitive brain-like circuits.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121809391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268393
Z. Krivokapic, U. Rana, R. Galatage, A. Razavieh, A. Aziz, J. Liu, J. Shi, H. Kim, R. Sporer, C. Serrao, A. Busquet, P. Polakowski, J. Müller, W. Kleemeier, A. Jacob, D. Brown, A. Knorr, R. Carter, S. Banna
Doped hafnia ferroelectric layers with thicknesses from 3 to 8nm are integrated into state-of-the-art 14nm FinFET technology without any further process modification. Ferroelectric devices show improved subthreshold slope (as low as 54mV/dec) and Idsat (up to 165% increase). C-V curves show slight ferroelectric hysteresis. For the first time, we show that ring oscillators with ferroelectric devices can operate at frequencies similar to regular dielectrics, while improved subthreshold slope reduces their active power. We also propose a model for ferroelectric MOSFETs that spans both negative (NCFET) and positive (PCFET) ferroelectric capacitance (CFE) devices. By carefully designed capacitance matching ferroelectric devices can provide significant power savings without sacrificing the speed.
{"title":"14nm Ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications","authors":"Z. Krivokapic, U. Rana, R. Galatage, A. Razavieh, A. Aziz, J. Liu, J. Shi, H. Kim, R. Sporer, C. Serrao, A. Busquet, P. Polakowski, J. Müller, W. Kleemeier, A. Jacob, D. Brown, A. Knorr, R. Carter, S. Banna","doi":"10.1109/IEDM.2017.8268393","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268393","url":null,"abstract":"Doped hafnia ferroelectric layers with thicknesses from 3 to 8nm are integrated into state-of-the-art 14nm FinFET technology without any further process modification. Ferroelectric devices show improved subthreshold slope (as low as 54mV/dec) and Idsat (up to 165% increase). C-V curves show slight ferroelectric hysteresis. For the first time, we show that ring oscillators with ferroelectric devices can operate at frequencies similar to regular dielectrics, while improved subthreshold slope reduces their active power. We also propose a model for ferroelectric MOSFETs that spans both negative (NCFET) and positive (PCFET) ferroelectric capacitance (CFE) devices. By carefully designed capacitance matching ferroelectric devices can provide significant power savings without sacrificing the speed.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124641077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268350
Suhui Lee, Di Geng, Ling Li, Ming Liu, Jin Jang
We report extremely stable and high performance etch-stopper (E/S) a-IGZO TFT on plastic substrate by using split active oxide semiconductor and source/drain electrodes. The a-IGZO TFTs exhibit high mobility over 70cm2/Vs and extremely stable under positive bias stress and mechanical stress. Therefore, this technology can be used for the manufacturing of high resolution flexible AMOLED displays.
{"title":"Highly robust oxide thin film transistors with split active semiconductor and source/drain electrodes","authors":"Suhui Lee, Di Geng, Ling Li, Ming Liu, Jin Jang","doi":"10.1109/IEDM.2017.8268350","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268350","url":null,"abstract":"We report extremely stable and high performance etch-stopper (E/S) a-IGZO TFT on plastic substrate by using split active oxide semiconductor and source/drain electrodes. The a-IGZO TFTs exhibit high mobility over 70cm2/Vs and extremely stable under positive bias stress and mechanical stress. Therefore, this technology can be used for the manufacturing of high resolution flexible AMOLED displays.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"385 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134194612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268309
S. Kim, Jong Chul Lee, T. J. Ha, Jong Ho Lee, Jae Yeon Lee, Yong Taek Park, K. Kim, W. Ju, Younghyun Ko, H. Hwang, B. Lee, J. Y. Moon, W. Park, B. Gyun, B. Lee, D. Yim, S. Hong
In this paper, the authors report for the first time the outstanding selector performance from an innovative oxide selector. SiO2, one of conventional and common materials in semiconductor industry, was chosen as a matrix oxide material. Metal atoms which are non-mobile and easy to handle were injected into the oxide films. Off-current and threshold voltage (Vth) could be controlled by using arsenic (As), which doping method and concentration were carefully investigated to achieve threshold switching behavior. Finally ReRAM (Resistance switching Random Access Memory) cell array consisted of one selector-one resistor (1S1R) was successfully demonstrated with the full integration of the newly developed selector.
{"title":"Breakthrough of selector technology for cross-point 25-nm ReRAM","authors":"S. Kim, Jong Chul Lee, T. J. Ha, Jong Ho Lee, Jae Yeon Lee, Yong Taek Park, K. Kim, W. Ju, Younghyun Ko, H. Hwang, B. Lee, J. Y. Moon, W. Park, B. Gyun, B. Lee, D. Yim, S. Hong","doi":"10.1109/IEDM.2017.8268309","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268309","url":null,"abstract":"In this paper, the authors report for the first time the outstanding selector performance from an innovative oxide selector. SiO2, one of conventional and common materials in semiconductor industry, was chosen as a matrix oxide material. Metal atoms which are non-mobile and easy to handle were injected into the oxide films. Off-current and threshold voltage (Vth) could be controlled by using arsenic (As), which doping method and concentration were carefully investigated to achieve threshold switching behavior. Finally ReRAM (Resistance switching Random Access Memory) cell array consisted of one selector-one resistor (1S1R) was successfully demonstrated with the full integration of the newly developed selector.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131030016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268322
T. Brunschwiler, G. Schlottig, A. Sridhar, P. Bezerra, P. Ruch, N. Ebejer, H. Oppermann, J. Kleff, W. Steller, M. Jatlaoui, F. Voiron, Z. Pavlović, P. McCloskey, D. Bremner, P. Parida, F. Krismer, J. Kolar, B. Michel
Novel heat removal and power delivery topologies are required to enable ‘extreme 3D integration’ with cube-sized compute nodes. Therefore, a technology roadmap is presented supporting memory-on-logic and logic-on-logic in the medium and long-term, by (i) dual-side cooling and integrated voltage regulators, and (ii) interlayer cooling and electrochemical power delivery.
{"title":"Towards cube-sized compute nodes: Advanced packaging concepts enabling extreme 3D integration","authors":"T. Brunschwiler, G. Schlottig, A. Sridhar, P. Bezerra, P. Ruch, N. Ebejer, H. Oppermann, J. Kleff, W. Steller, M. Jatlaoui, F. Voiron, Z. Pavlović, P. McCloskey, D. Bremner, P. Parida, F. Krismer, J. Kolar, B. Michel","doi":"10.1109/IEDM.2017.8268322","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268322","url":null,"abstract":"Novel heat removal and power delivery topologies are required to enable ‘extreme 3D integration’ with cube-sized compute nodes. Therefore, a technology roadmap is presented supporting memory-on-logic and logic-on-logic in the medium and long-term, by (i) dual-side cooling and integrated voltage regulators, and (ii) interlayer cooling and electrochemical power delivery.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134122067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268362
X. Duan, S. Pan, W. Pang
Using of bulk acoustic wave resonators for biosensing applications grows rapidly in recent years. In this review, we summarized the recent trend developing of these devices for biodetection from two aspects: 1) as biosensors to provide label-free measurement of biomarkers. 2) as bioacutuators to manipulate biomolecules and enhance biosensing performance.
{"title":"Development of high-frequency bulk acoustic wave (BAW) resonators as biosensors and bioactuators","authors":"X. Duan, S. Pan, W. Pang","doi":"10.1109/IEDM.2017.8268362","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268362","url":null,"abstract":"Using of bulk acoustic wave resonators for biosensing applications grows rapidly in recent years. In this review, we summarized the recent trend developing of these devices for biodetection from two aspects: 1) as biosensors to provide label-free measurement of biomarkers. 2) as bioacutuators to manipulate biomolecules and enhance biosensing performance.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132421592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268423
Rui Yang, Haitong Li, K. Smithe, T. R. Kim, Kye L. Okabe, E. Pop, Jonathan A. Fan, H. Wong
We demonstrate the first 1-transistor-1-resistor (1T1R) memory cell using the atomically thin molybdenum disulfide (MoS2) field-effect transistor (FET) and resistive random access memory (RRAM). This 1T1R demonstration realizes a key milestone for tight integration of memory with logic in a monolithic 3D integrated chip. The monolayer MoS2 is grown by chemical vapor deposition (CVD), suitable for wafer-scale fabrication. The MoS2 FETs have ON-state current of 190 μA/μm at Vd = 2.5 V, showing strong driving capability for RRAM. Metal-oxide RRAMs are fabricated at low process temperature, compatible with MoS2 FET fabrication. 1T1R measurements show higher resistances, and less resistance and voltage variation compared with measurements using only the RRAM. The multiple resistance states obtained for pulsed reset measurements show promise for in-memory computing and neuromorphic computing applications.
{"title":"2D molybdenum disulfide (MoS2) transistors driving RRAMs with 1T1R configuration","authors":"Rui Yang, Haitong Li, K. Smithe, T. R. Kim, Kye L. Okabe, E. Pop, Jonathan A. Fan, H. Wong","doi":"10.1109/IEDM.2017.8268423","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268423","url":null,"abstract":"We demonstrate the first 1-transistor-1-resistor (1T1R) memory cell using the atomically thin molybdenum disulfide (MoS2) field-effect transistor (FET) and resistive random access memory (RRAM). This 1T1R demonstration realizes a key milestone for tight integration of memory with logic in a monolithic 3D integrated chip. The monolayer MoS2 is grown by chemical vapor deposition (CVD), suitable for wafer-scale fabrication. The MoS2 FETs have ON-state current of 190 μA/μm at Vd = 2.5 V, showing strong driving capability for RRAM. Metal-oxide RRAMs are fabricated at low process temperature, compatible with MoS2 FET fabrication. 1T1R measurements show higher resistances, and less resistance and voltage variation compared with measurements using only the RRAM. The multiple resistance states obtained for pulsed reset measurements show promise for in-memory computing and neuromorphic computing applications.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114400391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268348
K. Triantopoulos, M. Cassé, L. Brunet, P. Batude, C. Fenouillet-Béranger, B. Mathieu, M. Vinet, G. Ghibaudo, G. Reimbold
We present for the first time an experimental study of thermal effects in 3D sequential integration, including Self-Heating Effect (SHE) and thermal coupling between the two levels of ultra-thin body FDSOI transistors. We extracted a large set of experimental data using different thermometry techniques, and different heater-sensor configurations allowed by this specific stacked integration. We described SHE in top and bottom transistor levels, as well as the influence of a transistor in ON state on a transistor stacked above or below. At the same time, we provide for the first time an experimental validation that the temperature increase given by gate resistance thermometry technique is equal to the temperature in the channel given by the subthreshold slope. Finally, this work can be also used to manage thermal effects for logic or analog applications, and help further optimization of 3D sequential integrated circuits through both technology and design solutions.
{"title":"Thermal effects in 3D sequential technology","authors":"K. Triantopoulos, M. Cassé, L. Brunet, P. Batude, C. Fenouillet-Béranger, B. Mathieu, M. Vinet, G. Ghibaudo, G. Reimbold","doi":"10.1109/IEDM.2017.8268348","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268348","url":null,"abstract":"We present for the first time an experimental study of thermal effects in 3D sequential integration, including Self-Heating Effect (SHE) and thermal coupling between the two levels of ultra-thin body FDSOI transistors. We extracted a large set of experimental data using different thermometry techniques, and different heater-sensor configurations allowed by this specific stacked integration. We described SHE in top and bottom transistor levels, as well as the influence of a transistor in ON state on a transistor stacked above or below. At the same time, we provide for the first time an experimental validation that the temperature increase given by gate resistance thermometry technique is equal to the temperature in the channel given by the subthreshold slope. Finally, this work can be also used to manage thermal effects for logic or analog applications, and help further optimization of 3D sequential integrated circuits through both technology and design solutions.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114902303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268470
K. Takeuchi
This paper presents the data-aware NAND flash memories for intelligent computing. By recognizing the “value” of data stored in NAND flash, sophisticated data management such as storing important data in the higher reliable memory cell or adaptively optimizing the read reference voltage depending on the stress of each memory cell are realized. As a result, intelligent computing such as image recognition with deep neural network [1], data compression [2], data center storage [3] and disaggregated hybrid storage [4,5] are achieved.
{"title":"Data-aware NAND flash memory for intelligent computing with deep neural network","authors":"K. Takeuchi","doi":"10.1109/IEDM.2017.8268470","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268470","url":null,"abstract":"This paper presents the data-aware NAND flash memories for intelligent computing. By recognizing the “value” of data stored in NAND flash, sophisticated data management such as storing important data in the higher reliable memory cell or adaptively optimizing the read reference voltage depending on the stress of each memory cell are realized. As a result, intelligent computing such as image recognition with deep neural network [1], data compression [2], data center storage [3] and disaggregated hybrid storage [4,5] are achieved.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"433 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116012918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/IEDM.2017.8268407
X. Zhao, C. Heidelberger, E. Fitzgerald, W. Lu, A. Vardi, J. D. del Alamo
We present the first sub-10 nm diameter vertical nanowire transistors of any kind in any semiconductor system. These devices are InGaAs MOSFETs fabricated by a top-down approach using reactive ion etching, alcohol-based digital etch and Ni alloyed contacts. A record Ion of 350 μA/μm at Ioff = 100 nA/μm and Vdd = 0.5 V is obtained in a 7 nm diameter device. The same device exhibits a peak transconductance (gm, pk) of 1.7 mS/μm and minimal subthreshold swing (S) of 90 mV/dec at Vds = 0.5 V, achieving the highest quality factor (defined as the ratio gm, pk/S) of 19 reported in vertical nanowire transistors. Excellent scaling behavior is observed with gm, pk and Ion increasing as the diameter is shrunk down to 7 nm.
{"title":"Sub-10 nm diameter InGaAs vertical nanowire MOSFETs","authors":"X. Zhao, C. Heidelberger, E. Fitzgerald, W. Lu, A. Vardi, J. D. del Alamo","doi":"10.1109/IEDM.2017.8268407","DOIUrl":"https://doi.org/10.1109/IEDM.2017.8268407","url":null,"abstract":"We present the first sub-10 nm diameter vertical nanowire transistors of any kind in any semiconductor system. These devices are InGaAs MOSFETs fabricated by a top-down approach using reactive ion etching, alcohol-based digital etch and Ni alloyed contacts. A record Ion of 350 μA/μm at Ioff = 100 nA/μm and Vdd = 0.5 V is obtained in a 7 nm diameter device. The same device exhibits a peak transconductance (gm, pk) of 1.7 mS/μm and minimal subthreshold swing (S) of 90 mV/dec at Vds = 0.5 V, achieving the highest quality factor (defined as the ratio gm, pk/S) of 19 reported in vertical nanowire transistors. Excellent scaling behavior is observed with gm, pk and Ion increasing as the diameter is shrunk down to 7 nm.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116713740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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