Electronic Materials Letters最新文献

High stretchability and flexibility are essential characteristics for wearable devices that attach to a living body to store data and analyze electrical signals. Memristors, the promising next generation of intelligent semiconductors, are expected to be lightweight and highly integrated by dramatically reducing device size due to its unique characteristics. The non-volatile nature of memristors is expected to be utilized in wearable devices that can store and analyze bioelectrical signals. To improve the resistive switching mechanism of the memristor, annealing process above 400 °C are widely utilized due to the certainty of the process. However, it is difficult to apply high-temperature annealing processes to flexible substrate like polyethylene terephthalate or polyethylene naphthalate. Here, we developed the low temperature Dual plasma-annealing treatment (DPA) process that combines a low-temperature annealing treatment process with an O₂ plasma process for glass/ITO/TiO₂/TiO_2−x/Ag thin film-based memristor devices, and to analyze the effect of this series DPA processes on memristor devices, we fabricated devices with different process temperatures. Also, we measured the enhancement in I–V curve, retention test and different of bandgap and ohmic conduction. The results showed that the resistive switching behavior of the device processed at 160 °C was best enhanced temperature and confirmed that the DPA process can replace the high temperature annealing treatment process and be applied to flexible substrates.

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Beom Gu Lee et al., TiO₂ memristors prepared based on sputtering-processeshave many advantages, such as the characteristic of resistive switchingmechanism, However, these devices require high-temperature annealing, whichposes challenges for their application on high-stretchable substrates. This workhas shown that the performance of the devices switching mechanism can beimproved by subjecting the devices to plasma treatment with low temperatureannealing process.

Memristor, a combination of memory and resistor, was first proposed as the fourth fundamental passive circuit element. While halide perovskites have emerged as promising materials for memristor devices, organic-inorganic hybrid perovskites face challenges such as hygroscopicity and thermal instability, limiting their long-term applicability. This paper focuses on inorganic halide perovskite quantum dots (IHPQDs), which offer enhanced environmental stability and unique properties, including high tolerance to native defects and ion migration capability. This paper provides a comprehensive review of recent advancements in IHPQDs, covering their crystal structures, synthesis techniques, and operational mechanisms in memristor devices. Unlike previous studies that predominantly explored bulk halide perovskites, we emphasize the role of IHPQDs in resistive switching memory and neuromorphic computing, highlighting their potential for multilevel resistance states and low-power operation. Additionally, this review addresses practical challenges, including thin-film uniformity, charge transport layer integration, and lead-free alternatives, which are critical for the commercialization of IHPQDs-based memristors. By proposing actionable strategies and future research directions, we aim to bridge the gap between fundamental research and real-world applications, positioning IHPQDs as key materials for next-generation electronic devices.

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This review paper systematically analyzes the recent advancements in semiconductor packaging technology, focusing on hybrid bonding technology. Hybrid bonding is a crucial technique for enhancing integration density and thermal management in high-performance semiconductor devices by directly bonding metal to an insulator. It is categorized into wafer-to-wafer (W2W), die-to-wafer (D2W), and die-to-die (D2D) methods.

This paper compares the characteristics, advantages, and limitations of each method while presenting technical approaches for performance improvements. Innovations such as new dielectric materials, surface and interface modifications, and optimizing the crystallinity and crystal orientation of metals can significantly enhance the reliability and performance of hybrid bonding. These strategies boost data transfer rates between memory and processors while reducing power consumption and improving overall system performance. This latest research on maximizing hybrid bonding performance is also discussed, emphasizing its potential in the next generation of memory technologies, including high bandwidth memory. This research lays a critical foundation for further advancements in high-performance 3D integrated circuit technology.

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Organoid culturing in microfluidic devices becomes an important technology for high throughput screening (HTS) of drugs, nutrients, and microbiome metabolites. Here, we present 3D organoid culturing devices to induce inflammation in human pluripotent stem cell (hPSC)-derived intestinal organoids (hIOs). Using high resolution 3D printing process, we established a method to fabricate microfluidic devices which have microchannels and 3D dome. The 3D dome geometry is suitable for the formation of Matrigel which serves as a cellular matrix. To validate the efficacy of the culturing devices, we induced inflammation in the hPSC-derived hIOs by the treatment of the combined proinflammatory cytokines such as interferon γ (IFNγ) and tumor necrosis factor α (TNFα). The inflamed hIOs have thinner epithelium with the upregulation of inflammatory cytokines. The induction of inflammatory models inside the 3D devices paves a way towards a microfluidic platform to investigate HTS.

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ZnSnO-based thin-film transistor (TFT) is considered to be the most competitive candidate for next-generation displays and transparent electronics. However, ZnSnO TFTs usually work in depletion mode with a negative voltage. In this work, we designed a structure of ZnSnO/Al₂O₃ TFTs with ultrathin Al₂O₃ contact layers. As the thickness of tunnel layer increases, the threshold voltages of TFTs increase at first and then decrease. When the growth cycle of Al₂O₃ layer reaches 17 (with thickness of ∼ 2 nm), the TFT has a positive threshold voltage of 2.3 V, as well as the best performances with an on-to-off current ratio of ∼ 10⁶, a saturation mobility of 23.5 cm²V^− 1s^− 1, and a small subthreshold swing of 0.57 V/decade. In this study, for the first time we propose an ultrathin contact method to modify the threshold voltage of amorphous oxide semiconductor (AOS) TFTs to get the enhancement mode without sacrificing mobility. It is expected that the method may open the door for practical applications of ZnSnO-based AOS TFTs.

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This study demonstrates the performance of a hydroxyethyl cellulose (HEC) charge trap layer for p-type organic thin-film transistor memory. The HEC charge trap transistor memory (HEC-TM) shows conventional charge trapping characteristics; that is, positive and negative threshold voltage (V_th) shifts after the application of a positive and negative bias, respectively. As the time and amplitude of the gate bias increases, V_th shift increases gradually and saturates. Because the electron trap is relatively more dominant than the hole trap in the hydroxyl group of HEC, a larger shift in V_th and longer memory retention appears when a positive voltage is applied rather than a negative voltage. HEC-TM is immersed and the HEC charge trap layer (HEC-CTL) is dissolved sufficiently with deionized water to validate its water degradability. HEC-TM is expected to be utilized as a biodegradable short-term transistor memory device.

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Amorphous metal powders, known for their high saturation magnetization, low coercivity (H_c), and reduced eddy current loss, hold great promise for high-performance magnetic devices. However, elevated core losses at higher frequencies—primarily due to eddy currents—impair their efficiency, leading to significant heat dissipation. This study addresses this challenge by investigating the application of low-softening temperature (T_s) glass frits as an insulating coating to enhance the electrical and magnetic properties of Fe_92.3Si_3.5B_3.0C_0.7P_0.5 (wt%) amorphous alloy powders. The practical implications of this research are significant, as it offers a potential solution to the problem of core losses at higher frequencies. The coated powders exhibited superior performance, with the lowest core loss measured at less than 321 mW/cm³ (B_m = 0.2 T at 1 MHz) and a high powder resistivity of up to 1.81 × 10⁹ Ω∙cm while maintaining appropriate permeability. Calculation and experimental results demonstrated that adjusting the coating thickness and ensuring a uniform layer minimized inter-particle and intra-particle eddy current losses. This optimization led to a significant reduction in core loss, enhancing the material’s high-frequency performance. The study emphasizes the critical role of low T_s glass frits in balancing resistivity, magnetic properties, and core loss reduction, offering a practical pathway for developing efficient amorphous alloy powders for advanced magnetic applications, including compact inductors and energy-efficient devices in eco-friendly technologies.

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An Fe-based amorphous alloy (Fe, Co)_68.7(C, Si, B, P)_24.5(Mo, Al)_6.8 was prepared as amorphous ribbons (~ 25 μm thick) and amorphous rods (Ф3 mm), which were crushed and sieved to form powders with different shapes and particles smaller than 53 μm: amorphous flake powders made from crushed ribbons and amorphous irregular powders made from crushed rods. Both powders were consolidated via spark plasma sintering into dense ring cores with a relative density exceeding 90%; this high density is attributed to the Newtonian flow within the temperature range of the amorphous powder’s supercooled liquid region. Excellent soft magnetic properties originating from the amorphous nature and high density of the ring cores were confirmed. Additionally, due to electrical isolation between the powder particles, the eddy current loss of the amorphous ring cores made from the SiO₂-coated amorphous flake powder was significantly reduced to 4.86 W/kg (at Bm = 100 mT, 1 kHz).

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Copper sulfide (CuS_x) is an electrocatalyst which selectively converts CO₂ into HCOOH under harsh conditions. Here, we investigate the formation and kinetics of CuS_x nanostructures on various multi-metal substrates to understand their catalytic properties in sulfur-containing environments. Using a combination of morphological, structural, and electrochemical analyses, we elucidate the time-dependent growth behavior of CuS_x nanostructures with progressive void formation over time. Notably, we discover that CuS_x formation is accelerated on substrates with galvanic corrosion-promoting metals such as Ag and Au, leading to enhanced selectivity for HCOOH during CO₂ reduction. In contrast, coating Cu with corrosion-inhibiting metals like Sn, Ni, or In reduce HCOOH selectivity, highlighting the critical role of galvanic corrosion in the CuS_x formation mechanism and its kinetics. This study experimentally identifies the impact of galvanic corrosion on CuS_x formation mechanisms and offers insights for optimizing electrocatalytic systems.

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