Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487757
Chao-Hsin Lu, Hua Wang, CH Peng, A. Goel, Sang-Hee Son, Paul C. P. Liang, A. Niknejad, HC Hwang, G. Chien
Recently, digitizing RF circuits has attracted extensive attention by exploiting high speed transistors offered in nano-scale CMOS processes. The digitally-assisted or digital-intensive RF transceivers not only benefit from technology scaling in terms of power efficiency and die area, but also improve functional flexibility. The polar architecture is well recognized for digital RF transmitters [1,2,4,5], while the bandwidth expansion resulting from Cartesian-to-polar transformation makes it difficult to comply with high-speed wireless standards. Open-loop phase interpolation topology was employed in an outphasing transmitter [3], where 12dBm output power was demonstrated with 40MHz 802.11n signal. In this work, an all-digital RF transmitter with direct quadrature architecture is presented to address the need for broadband wireless connectivity.
{"title":"A 24.7dBm all-digital RF transmitter for multimode broadband applications in 40nm CMOS","authors":"Chao-Hsin Lu, Hua Wang, CH Peng, A. Goel, Sang-Hee Son, Paul C. P. Liang, A. Niknejad, HC Hwang, G. Chien","doi":"10.1109/ISSCC.2013.6487757","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487757","url":null,"abstract":"Recently, digitizing RF circuits has attracted extensive attention by exploiting high speed transistors offered in nano-scale CMOS processes. The digitally-assisted or digital-intensive RF transceivers not only benefit from technology scaling in terms of power efficiency and die area, but also improve functional flexibility. The polar architecture is well recognized for digital RF transmitters [1,2,4,5], while the bandwidth expansion resulting from Cartesian-to-polar transformation makes it difficult to comply with high-speed wireless standards. Open-loop phase interpolation topology was employed in an outphasing transmitter [3], where 12dBm output power was demonstrated with 40MHz 802.11n signal. In this work, an all-digital RF transmitter with direct quadrature architecture is presented to address the need for broadband wireless connectivity.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"40 1","pages":"332-333"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79660736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487662
T. Takemoto, H. Yamashita, T. Yazaki, N. Chujo, Yong Lee, Y. Matsuoka
Growing data traffic requires low-power 25Gb/s-class optical interconnects for board-to-board transmission inside ICT systems [1-4]. The main power consumption of an optical link strongly depends on the sensitivity of the TIA; thus, development of a high-sensitivity TIA is a key to creating a low-power optical link., There are two challenges concerning the design of such a TIA: (1) improving the sensitivity of TIA without sacrificing bandwidth and (2) suppressing ISI due to insertion loss. To address these two issues, a 4×25Gb/s CMOS optical receiver (RX), which includes a four-channel TIA and a PD array operating at 1.3μm wavelength, is developed. The key components of the TIA are an automatic-decision-threshold control (ATC) with an offset canceller and low-voltage output driver (Drv) with peaking value of 7.7dB at 12.5GHz, achieved by separating equalizer (EQ) function and output buffer (BUF). The TIA attains a sensitivity of -9.7dBm (86μApp) optical modulation amplitude (OMA) and an eye opening of 65% at 25Gb/s. Operation at 28Gb/s with sensitivity of -8.2dBm (121μApp) OMA is also confirmed.
{"title":"A 4× 25-to-28Gb/s 4.9mW/Gb/s −9.7dBm high-sensitivity optical receiver based on 65nm CMOS for board-to-board interconnects","authors":"T. Takemoto, H. Yamashita, T. Yazaki, N. Chujo, Yong Lee, Y. Matsuoka","doi":"10.1109/ISSCC.2013.6487662","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487662","url":null,"abstract":"Growing data traffic requires low-power 25Gb/s-class optical interconnects for board-to-board transmission inside ICT systems [1-4]. The main power consumption of an optical link strongly depends on the sensitivity of the TIA; thus, development of a high-sensitivity TIA is a key to creating a low-power optical link., There are two challenges concerning the design of such a TIA: (1) improving the sensitivity of TIA without sacrificing bandwidth and (2) suppressing ISI due to insertion loss. To address these two issues, a 4×25Gb/s CMOS optical receiver (RX), which includes a four-channel TIA and a PD array operating at 1.3μm wavelength, is developed. The key components of the TIA are an automatic-decision-threshold control (ATC) with an offset canceller and low-voltage output driver (Drv) with peaking value of 7.7dB at 12.5GHz, achieved by separating equalizer (EQ) function and output buffer (BUF). The TIA attains a sensitivity of -9.7dBm (86μApp) optical modulation amplitude (OMA) and an eye opening of 65% at 25Gb/s. Operation at 28Gb/s with sensitivity of -8.2dBm (121μApp) OMA is also confirmed.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"47 1","pages":"118-119"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84290865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently reported continuous-time (CT) ΔΣ modulators with opamp bandwidth compensation and high-order single-opamp integrators have achieved FoM values well below 100fJ/conv-step [1-3]. With loop-filter power greatly reduced, power dissipation in multibit quantizers becomes especially significant. For example, the quantizer in [2] accounts for 2.8mW of 8.5mW total power dissipation. Also, the input capacitance of multibit quantizers and the output parasitics of excess loop delay (ELD) compensation DACs result in increased power demand for summing circuits. To minimize power dissipation, two recent works use 1b quantizers with FIR DACs and replace ELD compensation DACs with a DAC followed by analog filter [3] or with feedback to the pre-amplifier [4]. ELD compensation may also be realized using digital logic following the quantizer [5]. This paper presents a low-power solution based on a highly digital multibit quantizer with embedded feedback to compensate for finite opamp bandwidth along with ELD. The quantizer consumes less than 10% of the total power and simplifies the analog circuits into a single DAC plus a feedforward loop filter with relaxed opamp requirements. Digital correction at the modulator output suggested by early work [6] is employed to shape DAC mismatch with the inherent noise transfer function (NTF) and to further relax circuit constraints. These digitally assisted techniques enable a CT ΔΣ modulator to achieve an FoM below 28fJ/conv-step.
{"title":"A 28fJ/conv-step CT ΔΣ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer","authors":"Yun-Shiang Shu, Jui-Yuan Tsai, Ping-Yu Chen, Tien-Yu Lo, Pao-Cheng Chiu","doi":"10.1109/ISSCC.2013.6487729","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487729","url":null,"abstract":"Recently reported continuous-time (CT) ΔΣ modulators with opamp bandwidth compensation and high-order single-opamp integrators have achieved FoM values well below 100fJ/conv-step [1-3]. With loop-filter power greatly reduced, power dissipation in multibit quantizers becomes especially significant. For example, the quantizer in [2] accounts for 2.8mW of 8.5mW total power dissipation. Also, the input capacitance of multibit quantizers and the output parasitics of excess loop delay (ELD) compensation DACs result in increased power demand for summing circuits. To minimize power dissipation, two recent works use 1b quantizers with FIR DACs and replace ELD compensation DACs with a DAC followed by analog filter [3] or with feedback to the pre-amplifier [4]. ELD compensation may also be realized using digital logic following the quantizer [5]. This paper presents a low-power solution based on a highly digital multibit quantizer with embedded feedback to compensate for finite opamp bandwidth along with ELD. The quantizer consumes less than 10% of the total power and simplifies the analog circuits into a single DAC plus a feedforward loop filter with relaxed opamp requirements. Digital correction at the modulator output suggested by early work [6] is employed to shape DAC mismatch with the inherent noise transfer function (NTF) and to further relax circuit constraints. These digitally assisted techniques enable a CT ΔΣ modulator to achieve an FoM below 28fJ/conv-step.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"65 1","pages":"268-269"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83568071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487788
M. Mansuri, J. Jaussi, J. Kennedy, Tzu-Chien Hsueh, S. Shekhar, G. Balamurugan, F. O’Mahony, Clark Roberts, R. Mooney, B. Casper
High-performance computing (HPC) systems demand aggressive scaling of memory and I/O to achieve multiple terabits/sec of bandwidth. Minimizing I/O cost, area and power are crucial to achieving a practically realizable system with such large bandwidth. To meet these needs, we developed a low-power dense 64-lane I/O system with per-port aggregate bandwidth up to 1Tb/s and 2.6pJ/bit power efficiency. We developed a high-density connector and cable, attached to the top side of the package that enables this high interconnect density. A lane-failover mechanism provides design robustness for fault-tolerance. To further optimize power efficiency, the lane data rate scales from 2 to 16Gb/s with non-linear power efficiency of 0.8 to 2.6pJ/bit, providing scalable aggregate bandwidth of 0.128 to 1Tb/s. Highly power scalable circuits such as CMOS clocking and reconfigurable current-mode (CM) or voltage-mode (VM) TX driver enable the 8× bandwidth and 3× power efficiency scalability with aggressive supply voltage scaling (0.6 to 1.08V).
{"title":"A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS","authors":"M. Mansuri, J. Jaussi, J. Kennedy, Tzu-Chien Hsueh, S. Shekhar, G. Balamurugan, F. O’Mahony, Clark Roberts, R. Mooney, B. Casper","doi":"10.1109/ISSCC.2013.6487788","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487788","url":null,"abstract":"High-performance computing (HPC) systems demand aggressive scaling of memory and I/O to achieve multiple terabits/sec of bandwidth. Minimizing I/O cost, area and power are crucial to achieving a practically realizable system with such large bandwidth. To meet these needs, we developed a low-power dense 64-lane I/O system with per-port aggregate bandwidth up to 1Tb/s and 2.6pJ/bit power efficiency. We developed a high-density connector and cable, attached to the top side of the package that enables this high interconnect density. A lane-failover mechanism provides design robustness for fault-tolerance. To further optimize power efficiency, the lane data rate scales from 2 to 16Gb/s with non-linear power efficiency of 0.8 to 2.6pJ/bit, providing scalable aggregate bandwidth of 0.128 to 1Tb/s. Highly power scalable circuits such as CMOS clocking and reconfigurable current-mode (CM) or voltage-mode (VM) TX driver enable the 8× bandwidth and 3× power efficiency scalability with aggressive supply voltage scaling (0.6 to 1.08V).","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"26 1","pages":"402-403"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85054404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487695
M. Qazi, A. Amerasekera, A. Chandrakasan
Nonvolatile processing-continuously operating a digital circuit and retaining state through frequent power interruptions-creates new applications for portable electronics operating from harvested energy [1] and high-performance systems managing power by operating “normally off” [2]. To enable these scenarios, energy processing must happen in parallel with information processing. This work makes the following contributions: 1) the design of a nonvolatile D flip-flop (NVDFF) with embedded ferroelectric capacitors (fecaps) that senses data robustly and avoids race conditions; 2) the integration of the NVDFF into the ASIC design flow with a power management unit (PMU) and a simple one-bit interface to brown-out detection circuitry; and 3) a characterization of the NVDFF statistical signal margin and the energy cost of retaining data.
{"title":"A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems","authors":"M. Qazi, A. Amerasekera, A. Chandrakasan","doi":"10.1109/ISSCC.2013.6487695","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487695","url":null,"abstract":"Nonvolatile processing-continuously operating a digital circuit and retaining state through frequent power interruptions-creates new applications for portable electronics operating from harvested energy [1] and high-performance systems managing power by operating “normally off” [2]. To enable these scenarios, energy processing must happen in parallel with information processing. This work makes the following contributions: 1) the design of a nonvolatile D flip-flop (NVDFF) with embedded ferroelectric capacitors (fecaps) that senses data robustly and avoids race conditions; 2) the integration of the NVDFF into the ASIC design flow with a power management unit (PMU) and a simple one-bit interface to brown-out detection circuitry; and 3) a characterization of the NVDFF statistical signal margin and the energy cost of retaining data.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"15 1","pages":"192-193"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72862560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487723
Taekwang Jang, Nan Xing, Frank Liu, Jungeun Shin, Hyungreal Ryu, Jihyun F. Kim, Taeik Kim, Jaejin Park, Hojin Park
Recent innovations in semiconductor processes have accelerated the transition from analog circuits to their digital counterparts, with digital PLLs (DPLLs) being an example of this trend [1]. All-digital or fully synthesizable approaches, which exploit the merits of advanced processes, suffer from poor noise performance and high power consumption [2]. On the other hand, hybrid approaches, which employ analog components such as digital-to-analog converters (DACs), digital-to-time converters, phase interpolators (PIs) and regulators, have the typical difficulties associated with analog circuits, such as low output resistance, small voltage headroom and large variation. In this paper, we propose a highly digital architecture for a DPLL - one which minimizes the design effort typically required for analog circuits. The power and area-consuming circuits in prior works are replaced by power and area-efficient circuits with competitive performance. For example, a conventional time-to-digital converter (TDC) usually occupies considerable chip area in order to maximize input dynamic range with precise resolution [1]. Instead, in this work, a time-windowed phase-to-digital converter using interpolated DCO phases as a phase reference is adopted. In addition, conventional synchronous counters in the feedback path drastically increase the power consumption. Furthermore, retiming of data from the TDC is unavoidable due to the meta-stability of the sampling flip-flops [1]. The proposed divider scheme, which is composed of a multi-modulus frequency divider and a dead-zone-free phase and frequency detector (PFD), eliminates the need for a synchronous counter and retiming circuits. A calibration-free ΔΣ modulator (DSM) noise canceller is also included.
{"title":"A 0.026mm2 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter","authors":"Taekwang Jang, Nan Xing, Frank Liu, Jungeun Shin, Hyungreal Ryu, Jihyun F. Kim, Taeik Kim, Jaejin Park, Hojin Park","doi":"10.1109/ISSCC.2013.6487723","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487723","url":null,"abstract":"Recent innovations in semiconductor processes have accelerated the transition from analog circuits to their digital counterparts, with digital PLLs (DPLLs) being an example of this trend [1]. All-digital or fully synthesizable approaches, which exploit the merits of advanced processes, suffer from poor noise performance and high power consumption [2]. On the other hand, hybrid approaches, which employ analog components such as digital-to-analog converters (DACs), digital-to-time converters, phase interpolators (PIs) and regulators, have the typical difficulties associated with analog circuits, such as low output resistance, small voltage headroom and large variation. In this paper, we propose a highly digital architecture for a DPLL - one which minimizes the design effort typically required for analog circuits. The power and area-consuming circuits in prior works are replaced by power and area-efficient circuits with competitive performance. For example, a conventional time-to-digital converter (TDC) usually occupies considerable chip area in order to maximize input dynamic range with precise resolution [1]. Instead, in this work, a time-windowed phase-to-digital converter using interpolated DCO phases as a phase reference is adopted. In addition, conventional synchronous counters in the feedback path drastically increase the power consumption. Furthermore, retiming of data from the TDC is unavoidable due to the meta-stability of the sampling flip-flops [1]. The proposed divider scheme, which is composed of a multi-modulus frequency divider and a dead-zone-free phase and frequency detector (PFD), eliminates the need for a synchronous counter and retiming circuits. A calibration-free ΔΣ modulator (DSM) noise canceller is also included.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"5 1","pages":"254-255"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74956387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487786
A. Bhuyan, J. Choe, Byung-chul Lee, I. Wygant, A. Nikoozadeh, Ömer Oralkan, B. Khuri-Yakub
3D ultrasound imaging is becoming increasingly prevalent in the medical field. Compared to conventional 2D imaging systems, 3D imaging can provide a detailed view of tissue structures that makes diagnosis easier for the physicians. In addition, 2D image slices can be formed at various orientations to the transducer, making the examination less dependent on the skill of the sonographer. However, various challenges exist in developing a 3D imaging system, such as integration of a large number of elements, as well as post-processing of datasets received from a large number of channels. 2D transducer arrays are typically integrated with custom ICs in the probe handle to perform some intermediate beamforming and to reduce the number of cable connections to the imaging system. Capacitive micromachined ultrasonic transducers (CMUTs) have emerged as an alternative to piezoelectric transducers. Being a MEMS device, they greatly benefit from flexibility and ease of fabrication, and can be seamlessly integrated with electronics. Previous work demonstrates 3D stacking of CMUTs and dummy ICs with an intermediate interposer layer. However, that represents more of a mechanical demonstration of 3D integration. In this paper, we present a fully functional 3D ultrasound imaging system comprising a 32×32 2D CMUT array, 3D-stacked with front-end ICs using flip-chip bonding technology. The imaging system is capable of capturing real-time volumetric ultrasound data, and displaying 2D and 3D ultrasound images.
{"title":"3D volumetric ultrasound imaging with a 32×32 CMUT array integrated with front-end ICs using flip-chip bonding technology","authors":"A. Bhuyan, J. Choe, Byung-chul Lee, I. Wygant, A. Nikoozadeh, Ömer Oralkan, B. Khuri-Yakub","doi":"10.1109/ISSCC.2013.6487786","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487786","url":null,"abstract":"3D ultrasound imaging is becoming increasingly prevalent in the medical field. Compared to conventional 2D imaging systems, 3D imaging can provide a detailed view of tissue structures that makes diagnosis easier for the physicians. In addition, 2D image slices can be formed at various orientations to the transducer, making the examination less dependent on the skill of the sonographer. However, various challenges exist in developing a 3D imaging system, such as integration of a large number of elements, as well as post-processing of datasets received from a large number of channels. 2D transducer arrays are typically integrated with custom ICs in the probe handle to perform some intermediate beamforming and to reduce the number of cable connections to the imaging system. Capacitive micromachined ultrasonic transducers (CMUTs) have emerged as an alternative to piezoelectric transducers. Being a MEMS device, they greatly benefit from flexibility and ease of fabrication, and can be seamlessly integrated with electronics. Previous work demonstrates 3D stacking of CMUTs and dummy ICs with an intermediate interposer layer. However, that represents more of a mechanical demonstration of 3D integration. In this paper, we present a fully functional 3D ultrasound imaging system comprising a 32×32 2D CMUT array, 3D-stacked with front-end ICs using flip-chip bonding technology. The imaging system is capable of capturing real-time volumetric ultrasound data, and displaying 2D and 3D ultrasound images.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"94 1","pages":"396-397"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75168441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487627
A. Hafez, Ming-Shuan Chen, C. Yang
Serial-link transmitters are widely used in applications like optical transceivers and multi-gigabit Ethernet. At tens of Gb/s, the operating range of bit-rates is narrow; limited by the speed of the multiplexing and the setup and hold time constraints of the last stage in the serializer. This constraint leads to using delay-matching buffers [1] or delay calibration loops [1-2] to guarantee that timing constraints are always met at the desired bit-rate across all PVT corners. This additional circuitry increases power, area, and overall complexity of the transmitter. The timing constraint and power penalty are particularly severe when the data rate is high compared to the inherent speed of the technology.
{"title":"A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS","authors":"A. Hafez, Ming-Shuan Chen, C. Yang","doi":"10.1109/ISSCC.2013.6487627","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487627","url":null,"abstract":"Serial-link transmitters are widely used in applications like optical transceivers and multi-gigabit Ethernet. At tens of Gb/s, the operating range of bit-rates is narrow; limited by the speed of the multiplexing and the setup and hold time constraints of the last stage in the serializer. This constraint leads to using delay-matching buffers [1] or delay calibration loops [1-2] to guarantee that timing constraints are always met at the desired bit-rate across all PVT corners. This additional circuitry increases power, area, and overall complexity of the transmitter. The timing constraint and power penalty are particularly severe when the data rate is high compared to the inherent speed of the technology.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"1 1","pages":"38-39"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78798314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487742
M. Monge, M. Raj, M. H. Nazari, Jay Han-Chieh Chang, Yu Zhao, J. Weiland, M. Humayun, Y. Tai, A. Emami-Neyestanak
Since their conception and success in human trials, the flexibility and spatial resolution of retinal prostheses have been of major interest. Clinical studies have revealed that hundreds of channels are needed to restore functional visual perception, and more sophisticated waveforms present advantages over biphasic pulses. Initial designs targeted stimulation current levels up to 1mA to ensure functionality. For such designs, an output compliance of >10V was required, and HV technologies were used at the expense of area and power consumption. Human clinical trials have recently shown that implanted electrodes present a stimulus threshold as low as 50μA. In addition, advances in implant technology promise close placement of electrode array and retinal tissue, which can further decrease the required current. Thus, highly scaled LV technologies can provide alternative means to reduce area and power, and to support hundreds of flexible independent channels for fully intraocular implants. In this paper, a self-calibrating 512-channel epiretinal prosthesis in 65nm CMOS is presented. It features dual-band telemetry for power and data, clock recovery, a 2-step calibration technique to match biphasic stimulation currents, and an independent arbitrary output waveform per channel. The implant integrates coils (power and data), IC, external capacitors and electrode array using a biocompatible parylene substrate, providing a fully intraocular solution.
{"title":"A fully intraocular 0.0169mm2/pixel 512-channel self-calibrating epiretinal prosthesis in 65nm CMOS","authors":"M. Monge, M. Raj, M. H. Nazari, Jay Han-Chieh Chang, Yu Zhao, J. Weiland, M. Humayun, Y. Tai, A. Emami-Neyestanak","doi":"10.1109/ISSCC.2013.6487742","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487742","url":null,"abstract":"Since their conception and success in human trials, the flexibility and spatial resolution of retinal prostheses have been of major interest. Clinical studies have revealed that hundreds of channels are needed to restore functional visual perception, and more sophisticated waveforms present advantages over biphasic pulses. Initial designs targeted stimulation current levels up to 1mA to ensure functionality. For such designs, an output compliance of >10V was required, and HV technologies were used at the expense of area and power consumption. Human clinical trials have recently shown that implanted electrodes present a stimulus threshold as low as 50μA. In addition, advances in implant technology promise close placement of electrode array and retinal tissue, which can further decrease the required current. Thus, highly scaled LV technologies can provide alternative means to reduce area and power, and to support hundreds of flexible independent channels for fully intraocular implants. In this paper, a self-calibrating 512-channel epiretinal prosthesis in 65nm CMOS is presented. It features dual-band telemetry for power and data, clock recovery, a 2-step calibration technique to match biphasic stimulation currents, and an independent arbitrary output waveform per channel. The implant integrates coils (power and data), IC, external capacitors and electrode array using a biocompatible parylene substrate, providing a fully intraocular solution.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"14 1","pages":"296-297"},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73287876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487814
Liechao Huang, W. Rieutort-Louis, Yingzhe Hu, J. Sanz-Robinson, S. Wagner, J. Sturm, N. Verma
Large-area electronics presents new form factors, enabling ubiquitous systems that are flexible and capable of scaling to very large areas. By processing thin-film transistors (TFTs) at low temperatures on plastic (using organics, amorphous silicon, metal oxides, etc.), blocks such as ADCs, amplifiers, and processors can be realized [1,2]; however, aside from short-range RFID tags [3], wireless links for long-range communication have not been achieved. A key challenge is that wireless systems typically depend on the ability to generate and operate at high frequencies, yet TFTs are limited to very low performance (ft ~1MHz). Specifically, the challenge is low device gm, due to low mobility and limited gate-dielectric scalability, as well as high device capacitance, due to limited feature scalability and large overlaps for alignment margining on flexible substrates. This work presents a super-regenerative (SR) transceiver with integrated antenna on plastic that leverages the attribute of large area to create highquality passives; this enables resonant TFT circuits at high frequencies (near ft) and allows for large antennas, maximizing the communication distance. The resulting carrier frequency is 900kHz, and the range is over 12m (at 2kb/s). As shown in Fig. 25.10.1, this will enable sheets with integrated arrays of radio frontends for distributing a large number of communication links over large areas.
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