Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248874
Tae-Kyu Lee, Hongtao Ma
Isothermal aging effects on lead-free solders have been extensively investigated in recent studies for both bulk solders and package solder joints. Researches show that aging significantly degrades the mechanical properties of bulk lead-free solders and dynamic performances of lead-free solder joints. There are studies exploring the impact of aging on accelerated thermal cycling (ATC) performance of lead-free solder joints, however, the results are discrepant, some research shows minimal impact of isothermal aging on long term ATC performances since most of the failure mode are not related to intermetallic (IMC) growth which has been impacted more significantly during aging. Some others show significant degradation of the of ATC life due to evidence of weakening of solder joints after aging. This study is intended to explore the factors that may affect the aging impact on the lead-free solder joint fatigue life. The test vehicle is designed with different package types, pitch sizes, and solder alloy metallurgies to capture the impact of affecting factors. The test vehicles have been aged at 100°C and 150°C for different aging durations, ATC test were subsequently performed on the aged samples and with the non aged samples as control. The effects of aging on the fatigue life of lead-free solder joints are extensively explored in this study.
{"title":"Aging impact on the accelerated thermal cycling performance of lead-free BGA solder joints in various stress conditions","authors":"Tae-Kyu Lee, Hongtao Ma","doi":"10.1109/ECTC.2012.6248874","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248874","url":null,"abstract":"Isothermal aging effects on lead-free solders have been extensively investigated in recent studies for both bulk solders and package solder joints. Researches show that aging significantly degrades the mechanical properties of bulk lead-free solders and dynamic performances of lead-free solder joints. There are studies exploring the impact of aging on accelerated thermal cycling (ATC) performance of lead-free solder joints, however, the results are discrepant, some research shows minimal impact of isothermal aging on long term ATC performances since most of the failure mode are not related to intermetallic (IMC) growth which has been impacted more significantly during aging. Some others show significant degradation of the of ATC life due to evidence of weakening of solder joints after aging. This study is intended to explore the factors that may affect the aging impact on the lead-free solder joint fatigue life. The test vehicle is designed with different package types, pitch sizes, and solder alloy metallurgies to capture the impact of affecting factors. The test vehicles have been aged at 100°C and 150°C for different aging durations, ATC test were subsequently performed on the aged samples and with the non aged samples as control. The effects of aging on the fatigue life of lead-free solder joints are extensively explored in this study.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77202152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248844
V. Sundaram, Q. Chen, Y. Suzuki, G. Kumar, Fuhan Liu, R. Tummala
This paper presents the design, fabrication and electrical characterization of a low loss and low cost non-traditional silicon interposer, demonstrating the high bandwidth chip-to-chip interconnection capability of the 3D silicon interposer, with equivalent or better performance than 3D ICs with TSVs, at a much lower cost. This scalable approach uses thin polycrystalline silicon in wafer or panel form, forms lower cost through-package-vias (TPVs) at fine pitch by special high throughput laser processes. The electrical performance is improved by thick polymer liners within the TPVs. Double side package processes for TPV metallization and RDL layers using dry film polymers and plating leads to significant cost reduction compared to single side TSV and BEOL wafer processes. Combined loss of 3mm long CPW lines and two TPVs in the low loss silicon interposer was demonstrated at less than 1dB at 10GHz. The fine pitch TPV capability and low loss of this non-traditional silicon interposer leads to 3D interposers with double side chips interconnected at equivalent bandwidth to wide bus I/O 3D ICs at a much lower cost and with better testability, thermal management and scalability.
本文介绍了一种低损耗、低成本的非传统硅中间体的设计、制造和电学特性，展示了3D硅中间体的高带宽片对片互连能力，其性能与带有tsv的3D集成电路相当或更好，成本低得多。这种可扩展的方法使用晶圆或面板形式的薄多晶硅，通过特殊的高通量激光工艺在细间距上形成低成本的通封装通孔(TPVs)。电性能得到改善的厚聚合物衬里的TPVs。与单面TSV和BEOL晶圆工艺相比，使用干膜聚合物和电镀的TPV金属化和RDL层的双面封装工艺可显着降低成本。低损耗硅中间体中3mm长的CPW线和两个TPVs的综合损耗在10GHz时小于1dB。这种非传统硅中间体的细间距TPV能力和低损耗导致具有双面芯片的3D中间体以同等带宽与宽总线I/O 3D ic互连，成本低得多，具有更好的可测试性，热管理和可扩展性。
{"title":"Low-cost and low-loss 3D silicon interposer for high bandwidth logic-to-memory interconnections without TSV in the logic IC","authors":"V. Sundaram, Q. Chen, Y. Suzuki, G. Kumar, Fuhan Liu, R. Tummala","doi":"10.1109/ECTC.2012.6248844","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248844","url":null,"abstract":"This paper presents the design, fabrication and electrical characterization of a low loss and low cost non-traditional silicon interposer, demonstrating the high bandwidth chip-to-chip interconnection capability of the 3D silicon interposer, with equivalent or better performance than 3D ICs with TSVs, at a much lower cost. This scalable approach uses thin polycrystalline silicon in wafer or panel form, forms lower cost through-package-vias (TPVs) at fine pitch by special high throughput laser processes. The electrical performance is improved by thick polymer liners within the TPVs. Double side package processes for TPV metallization and RDL layers using dry film polymers and plating leads to significant cost reduction compared to single side TSV and BEOL wafer processes. Combined loss of 3mm long CPW lines and two TPVs in the low loss silicon interposer was demonstrated at less than 1dB at 10GHz. The fine pitch TPV capability and low loss of this non-traditional silicon interposer leads to 3D interposers with double side chips interconnected at equivalent bandwidth to wide bus I/O 3D ICs at a much lower cost and with better testability, thermal management and scalability.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80199194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248995
S. Yoon, Jose Alvin Caparas, Yaojian Lin, P. Marimuthu
Current portable electronic products are driving component packaging towards 3D packaging technologies for integrating multiple memory die and application processors (AP). Among the 3D technologies, Package-on-Package (PoP) is increasingly becoming mainstream due to its flexibility of combination and sourcing. Moreover, device designs require functional integration of IC's, especially in the 3rd dimension, hence driving new technology development towards making IC components “thin and thinner”. eWLB (embedded Wafer Level Ball Grid Array) has been introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. There is also great opportunity related to a 3D variation of eWLB which would allow for mounting of components or another package on the top surface with thinner profile and Package-on-Package (eWBL-PoP) technology. 3D PoP-eWLB is envisioned as an exciting technology which will open up the floodgates for system level integration utilizing very thin stacked eWLB packages as building blocks in mobile applications. This paper reports developments that are aimed to extend the low profile PoP application with eWLB + PoP technology. Test vehicle is designed and fabricated to demonstrate to be thin and 3D PoP solution for mobile and portable electronics. Assembly process details including laser ablation and interconnects process and mechanical characterizations are to be discussed with component and board level reliability results. Innovative package structures optimization that provide dual advantages of both form factor reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, package with multi layer redistribution (RDL) and 10um/10um line width/spacing is fabricated and implemented on eWLB platform. Successful reliability characterization results on low profile PoP package configurations are reported that demonstrate eWLB-PoP as an enabling technology for miniaturized, low profile and cost-effective 3D PoP.
{"title":"Advanced low profile PoP solution with embedded wafer level PoP (eWLB-PoP) technology","authors":"S. Yoon, Jose Alvin Caparas, Yaojian Lin, P. Marimuthu","doi":"10.1109/ECTC.2012.6248995","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248995","url":null,"abstract":"Current portable electronic products are driving component packaging towards 3D packaging technologies for integrating multiple memory die and application processors (AP). Among the 3D technologies, Package-on-Package (PoP) is increasingly becoming mainstream due to its flexibility of combination and sourcing. Moreover, device designs require functional integration of IC's, especially in the 3rd dimension, hence driving new technology development towards making IC components “thin and thinner”. eWLB (embedded Wafer Level Ball Grid Array) has been introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. There is also great opportunity related to a 3D variation of eWLB which would allow for mounting of components or another package on the top surface with thinner profile and Package-on-Package (eWBL-PoP) technology. 3D PoP-eWLB is envisioned as an exciting technology which will open up the floodgates for system level integration utilizing very thin stacked eWLB packages as building blocks in mobile applications. This paper reports developments that are aimed to extend the low profile PoP application with eWLB + PoP technology. Test vehicle is designed and fabricated to demonstrate to be thin and 3D PoP solution for mobile and portable electronics. Assembly process details including laser ablation and interconnects process and mechanical characterizations are to be discussed with component and board level reliability results. Innovative package structures optimization that provide dual advantages of both form factor reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, package with multi layer redistribution (RDL) and 10um/10um line width/spacing is fabricated and implemented on eWLB platform. Successful reliability characterization results on low profile PoP package configurations are reported that demonstrate eWLB-PoP as an enabling technology for miniaturized, low profile and cost-effective 3D PoP.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80545828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248799
E. Morinaga, Y. Oka, H. Nishimori, H. Miyagawa, R. Satoh, Y. Iwata, R. Kanezaki
The three dimensional system in package (3D-SiP) has been regarded as a promising solution to the scaling limit problem in the semiconductor industry. Practical realization of the 3D-SiP needs establishing a standard bonding technology for chip stacking. This research focuses on a low temperature and high heat-resistant fluxless bonding method, which can overcome the bump height variation problem in a chip/wafer, using high-boiling alcohol, an indium-tin (InSn) thin film and its transformation into high-melting intermetallic compound (IMC). Experimental studies showed high-rate deposition of InSn alloy and successive deposition of silver achieve successful bonding where the joint has high melting point (higher than 673K).
{"title":"Study of low temperature and high heat-resistant fluxless bonding via nanoscale thin film control toward wafer-level multiple chip stacking for 3D LSI","authors":"E. Morinaga, Y. Oka, H. Nishimori, H. Miyagawa, R. Satoh, Y. Iwata, R. Kanezaki","doi":"10.1109/ECTC.2012.6248799","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248799","url":null,"abstract":"The three dimensional system in package (3D-SiP) has been regarded as a promising solution to the scaling limit problem in the semiconductor industry. Practical realization of the 3D-SiP needs establishing a standard bonding technology for chip stacking. This research focuses on a low temperature and high heat-resistant fluxless bonding method, which can overcome the bump height variation problem in a chip/wafer, using high-boiling alcohol, an indium-tin (InSn) thin film and its transformation into high-melting intermetallic compound (IMC). Experimental studies showed high-rate deposition of InSn alloy and successive deposition of silver achieve successful bonding where the joint has high melting point (higher than 673K).","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80675154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249064
Thomas D. Ewald, Norbert Holle, Klaus-Jurgen Wolter
In the present study the interaction between solder paste and the PCB surface finish and its impact on void formation was investigated. Therefore, a comprehensive set of tests was performed on test vehicles with different diameter of the solder powder, solder alloy composition, PCB surface finish and flux chemistry. Based on these experimental results a hypothesis of void generating mechanisms is presented characterizing the wetting process.
{"title":"Void formation during reflow soldering","authors":"Thomas D. Ewald, Norbert Holle, Klaus-Jurgen Wolter","doi":"10.1109/ECTC.2012.6249064","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249064","url":null,"abstract":"In the present study the interaction between solder paste and the PCB surface finish and its impact on void formation was investigated. Therefore, a comprehensive set of tests was performed on test vehicles with different diameter of the solder powder, solder alloy composition, PCB surface finish and flux chemistry. Based on these experimental results a hypothesis of void generating mechanisms is presented characterizing the wetting process.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82925253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248860
T. Fukushima, Y. Ohara, J. Bea, M. Murugesan, K. Lee, T. Tanaka, M. Koyanagi
Two key technologies consisting of chip-to-wafer bonding through a non-conductive film (NCF) and wafer-level packaging using compression molding were studied for self-assembly-based 3D integration, especially reconfigured wafer-to-wafer stacking. 4-mm-by-5-mm chips having 20-μm-pitch Cu-SnAg microbumps were successfully bonded to wafers through NCF. The resulting daisy chain obtained from the chip-to-wafer structure showed low contact resistance of approximately 50 MΩ/bump. Compression molding was implemented to a chip-on-wafer structure. Grinding of the chip-on-wafer structure gave low total thickness variation (TTV) within 1 μm and the following CMP led good planarization capability.
研究了基于自组装的三维集成的两个关键技术，即通过非导电薄膜(NCF)的晶片键合和使用压缩成型的晶片级封装，特别是重新配置的晶片到晶片堆叠。具有20 μm间距Cu-SnAg微凸起的4 mm × 5 mm芯片通过NCF成功结合到晶圆上。从芯片到晶圆结构得到的菊花链显示出约50 MΩ/bump的低接触电阻。对片上芯片结构进行了压缩成型。对片上晶片结构进行磨削后，总厚度变化(TTV)在1 μm以内，磨削后的CMP具有良好的平面化能力。
{"title":"Non-conductive film and compression molding technology for self-assembly-based 3D integration","authors":"T. Fukushima, Y. Ohara, J. Bea, M. Murugesan, K. Lee, T. Tanaka, M. Koyanagi","doi":"10.1109/ECTC.2012.6248860","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248860","url":null,"abstract":"Two key technologies consisting of chip-to-wafer bonding through a non-conductive film (NCF) and wafer-level packaging using compression molding were studied for self-assembly-based 3D integration, especially reconfigured wafer-to-wafer stacking. 4-mm-by-5-mm chips having 20-μm-pitch Cu-SnAg microbumps were successfully bonded to wafers through NCF. The resulting daisy chain obtained from the chip-to-wafer structure showed low contact resistance of approximately 50 MΩ/bump. Compression molding was implemented to a chip-on-wafer structure. Grinding of the chip-on-wafer structure gave low total thickness variation (TTV) within 1 μm and the following CMP led good planarization capability.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81053187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249097
Sha Xu, Xiaoxin Zhu, H. Kotadia, Hua Lu, S. Mannan, C. Bailey, Y. Chan
Electromigration is a critical reliability problem in electronic industry, especially with the shrinkage and downscaling of microelectronic feature size, which results in gradual increase of current density. Carbon nanotube(CNT) doping is adopted in this paper. CNT has demonstrated high electromigration resistance. In our work, CNT doping is combined with SAC interconnects. A CNT after surfactant will be incorporated into SAC solder interconnection. Best percentage of CNT doping is found from this experiment, and better electromigration reliability can be observed from this work by SEM image. Moreover, the shear stress distribution is improved using computational study, which shows better mechanical properties. The combination of experimental and numerical study is highlighted in this work.
{"title":"Remedies to control electromigration: Effects of CNT doped Sn-Ag-Cu interconnects","authors":"Sha Xu, Xiaoxin Zhu, H. Kotadia, Hua Lu, S. Mannan, C. Bailey, Y. Chan","doi":"10.1109/ECTC.2012.6249097","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249097","url":null,"abstract":"Electromigration is a critical reliability problem in electronic industry, especially with the shrinkage and downscaling of microelectronic feature size, which results in gradual increase of current density. Carbon nanotube(CNT) doping is adopted in this paper. CNT has demonstrated high electromigration resistance. In our work, CNT doping is combined with SAC interconnects. A CNT after surfactant will be incorporated into SAC solder interconnection. Best percentage of CNT doping is found from this experiment, and better electromigration reliability can be observed from this work by SEM image. Moreover, the shear stress distribution is improved using computational study, which shows better mechanical properties. The combination of experimental and numerical study is highlighted in this work.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89986469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248846
Y. Li, D. Velenis, T. Kauerauf, M. Stucchi, Y. Civale, A. Redolfi, K. Croes
In this paper, the controlled I-V (IVctrl) method is adopted for the barrier integrity characterization of TSVs at wafer level. Planar capacitor structures are used for the initial validation of the IVctrl method with respect to the traditional time dependent dielectric breakdown (TDDB) methodology. The TDDB field acceleration factor of the TSV liner is extracted by IVctrl in a reasonable time, and the results demonstrate that defective barriers can degrade TDDB field acceleration factor and thus TSV liner reliability.
{"title":"Electrical characterization method to study barrier integrity in 3D through-silicon vias","authors":"Y. Li, D. Velenis, T. Kauerauf, M. Stucchi, Y. Civale, A. Redolfi, K. Croes","doi":"10.1109/ECTC.2012.6248846","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248846","url":null,"abstract":"In this paper, the controlled I-V (IVctrl) method is adopted for the barrier integrity characterization of TSVs at wafer level. Planar capacitor structures are used for the initial validation of the IVctrl method with respect to the traditional time dependent dielectric breakdown (TDDB) methodology. The TDDB field acceleration factor of the TSV liner is extracted by IVctrl in a reasonable time, and the results demonstrate that defective barriers can degrade TDDB field acceleration factor and thus TSV liner reliability.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89986741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249142
M. Mostofizadeh, K. Kokko, L. Frisk
With the advent of miniaturization in the electronics industry, the application of flexible interconnections has become necessary and inevitable for many new designs such as flexible circuits (flex) to printed circuit boards (PCB), flex to flex, and multiwire to PCB. Pulse-heated reflow soldering is demonstrably a reliable and repeatable soldering process for manufacturing such products, especially in the attachment of flex-to-PCB in the electronics industry. This paper reports on the microstructure and reliability of flex-to-PCB solder joints. Flex-to-PCB samples were made using Pulse-heated reflow soldering and conventional reflow oven soldering. To study the reliability of the solder joints, three different environmental tests were conducted including thermal shock, thermal humidity, and thermal aging. Microstructural studies and failure analysis were performed on all samples before and after the reliability tests in order to ascertain the cause of failure in both bonding methods. Additionally, a comparison of both attachment methods comprising pulse-heated reflow soldering and reflow oven is presented demonstrating their applicability in manufacturing flex-to-PCB assemblies.
{"title":"Reliability and microstructural studies of Sn-Ag-Cu lead-free solder joints in pulse-heated reflow soldering","authors":"M. Mostofizadeh, K. Kokko, L. Frisk","doi":"10.1109/ECTC.2012.6249142","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249142","url":null,"abstract":"With the advent of miniaturization in the electronics industry, the application of flexible interconnections has become necessary and inevitable for many new designs such as flexible circuits (flex) to printed circuit boards (PCB), flex to flex, and multiwire to PCB. Pulse-heated reflow soldering is demonstrably a reliable and repeatable soldering process for manufacturing such products, especially in the attachment of flex-to-PCB in the electronics industry. This paper reports on the microstructure and reliability of flex-to-PCB solder joints. Flex-to-PCB samples were made using Pulse-heated reflow soldering and conventional reflow oven soldering. To study the reliability of the solder joints, three different environmental tests were conducted including thermal shock, thermal humidity, and thermal aging. Microstructural studies and failure analysis were performed on all samples before and after the reliability tests in order to ascertain the cause of failure in both bonding methods. Additionally, a comparison of both attachment methods comprising pulse-heated reflow soldering and reflow oven is presented demonstrating their applicability in manufacturing flex-to-PCB assemblies.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91269660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248890
Minhua Lu, S. Wright, Gerard McVicker, S. M. Sri-Jayantha
Temperature and current are two major parameters that impact electromigration reliability. Due to the large current used in the accelerated electromigration test, the Joule self-heating associated with the stress current can be significant. The paper presents a study of electromigration fails in Pb-free interconnect from the point of view of localized Joule heating. The Joule heating effect in two types of packages, a fully assembled flip chip module with standard C4s and a silicon to silicon assembly with microbumps, is considered. A thermal FEM model is used as a guide to interpret the experimental observations.
{"title":"Effect of Joule heating on electromigration reliability of Pb-free interconnect","authors":"Minhua Lu, S. Wright, Gerard McVicker, S. M. Sri-Jayantha","doi":"10.1109/ECTC.2012.6248890","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248890","url":null,"abstract":"Temperature and current are two major parameters that impact electromigration reliability. Due to the large current used in the accelerated electromigration test, the Joule self-heating associated with the stress current can be significant. The paper presents a study of electromigration fails in Pb-free interconnect from the point of view of localized Joule heating. The Joule heating effect in two types of packages, a fully assembled flip chip module with standard C4s and a silicon to silicon assembly with microbumps, is considered. A thermal FEM model is used as a guide to interpret the experimental observations.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81070293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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