Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248937
L. Yip
With the industry movement towards lead-free solders and advanced silicon process nodes with ultra low-k dielectrics, flip chip packaging is faced with significant assembly and reliability challenges. Since lead-free solder bumps are brittle, they can easily crack without adequate support from the underfill material during thermal stress. Lead-free solder bumps have less solder fatigue resistance compared to tin-lead eutectic or high-lead bumps and require higher Tg underfills for protection. However, the higher Tg underfill and the higher reflow temperature needed for lead-free bump assembly will increase die stress and package warpage. Since lower k dielectric materials have lower mechanical strength and lower adhesion than the dielectric materials used for prior silicon generations, the high stress induced by the lead-free assembly process and material set can cause delamination within the die, especially in devices with large die and large package sizes. In order to develop and qualify a reliable and robust lead-free package, care must be taken in the materials selection and optimization of the package structure. This paper discusses the effect of different factors such as underfill, substrate core, substrate pad structure, and lid design on package reliability of lead-free fine-pitch flip chip devices. It also reviews the assembly process related factors that impact the reliability of the lead-free bump and ultra low-k devices. Our studies show that a highly reliable lead-free package on organic substrate can be achieved for devices with large die and large package sizes. The reliability results for large die with different silicon nodes from 90 nm to 28 nm are presented.
{"title":"Reliability of large die ultra low-k lead-free flip chip packages","authors":"L. Yip","doi":"10.1109/ECTC.2012.6248937","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248937","url":null,"abstract":"With the industry movement towards lead-free solders and advanced silicon process nodes with ultra low-k dielectrics, flip chip packaging is faced with significant assembly and reliability challenges. Since lead-free solder bumps are brittle, they can easily crack without adequate support from the underfill material during thermal stress. Lead-free solder bumps have less solder fatigue resistance compared to tin-lead eutectic or high-lead bumps and require higher Tg underfills for protection. However, the higher Tg underfill and the higher reflow temperature needed for lead-free bump assembly will increase die stress and package warpage. Since lower k dielectric materials have lower mechanical strength and lower adhesion than the dielectric materials used for prior silicon generations, the high stress induced by the lead-free assembly process and material set can cause delamination within the die, especially in devices with large die and large package sizes. In order to develop and qualify a reliable and robust lead-free package, care must be taken in the materials selection and optimization of the package structure. This paper discusses the effect of different factors such as underfill, substrate core, substrate pad structure, and lid design on package reliability of lead-free fine-pitch flip chip devices. It also reviews the assembly process related factors that impact the reliability of the lead-free bump and ultra low-k devices. Our studies show that a highly reliable lead-free package on organic substrate can be achieved for devices with large die and large package sizes. The reliability results for large die with different silicon nodes from 90 nm to 28 nm are presented.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"420 1","pages":"877-881"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77028356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248943
P. Raj, K. Murali, S. Gandhi, R. Tummala, K. Slenes, N. Berg
This paper reports novel material and process technologies for near-zero Temperature-Coefficient Resistors (TCR) and zero temperature coefficient of capacitance (TCC) capacitors and their integration into organic or silicon packages for precision RF components. A new concept of self-compensating resistors, leading to zero TCR was explored and demonstrated for the first time, using heterogeneous resistor stack structures consisting of metal layers with positive TCR and semiconducting oxide layers with negative TCR. Zero TCC capacitors were demonstrated with a film-stack consisting of ceramic nanocomposites of positive TCC and negative TCC. In both cases, the film thickness was designed such that there is internal compensation in temperature deviation, which results in zero temperature-coefficient. Material models were developed for the film-stack to design the films for zero temperature-coefficient.
{"title":"Integration of precision resistors and capacitors with near-zero temperature coefficients in silicon and organic packages","authors":"P. Raj, K. Murali, S. Gandhi, R. Tummala, K. Slenes, N. Berg","doi":"10.1109/ECTC.2012.6248943","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248943","url":null,"abstract":"This paper reports novel material and process technologies for near-zero Temperature-Coefficient Resistors (TCR) and zero temperature coefficient of capacitance (TCC) capacitors and their integration into organic or silicon packages for precision RF components. A new concept of self-compensating resistors, leading to zero TCR was explored and demonstrated for the first time, using heterogeneous resistor stack structures consisting of metal layers with positive TCR and semiconducting oxide layers with negative TCR. Zero TCC capacitors were demonstrated with a film-stack consisting of ceramic nanocomposites of positive TCC and negative TCC. In both cases, the film thickness was designed such that there is internal compensation in temperature deviation, which results in zero temperature-coefficient. Material models were developed for the film-stack to design the films for zero temperature-coefficient.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"565 1","pages":"910-914"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77762629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249109
V. Mokkapati, O. Bethge, R. Hainberger, H. Brueckl
Conventional fabrication of microfluidic chips is based on silicon, glass, PDMS and various other polymeric materials (COC, polycarbonate, PMMA etc). Silicon and glass processing technologies are highly developed and the chips can be fabricated with ease. Polymeric microfluidic chips have become very common in recent years due to the demand for the cheap and disposable devices. New entrants in to the field are UV curable adhesives which are gaining recognition as promising players in microfluidics. UV curable adhesives are generally used in various applications ranging from usage in the manufacture of parts of an aircraft to sealing/packaging of microfluidic chips. Unlike any other previously discussed materials UV curable adhesives have the flexibility in alignment and bonding during fabrication process. These adhesives can be applied in between two surfaces which are to be glued and can be left like that for hours to days without bonding them as long as the glue is not exposed to UV light. In this paper we explain the detailed fabrication of microfluidic chips (100μm wide and 3μm (NOA74), 22μm (NOA 68) deep) completely made from UV curable adhesives having better chemical resistance, permeability and flexible surface treatments compared to other known polymeric materials. Firstly the patterns were etched on silicon, followed by PDMS molding and subsequently UV curable adhesives were casted and cured on structured PDMS master. After unmolding the stamps were mounted on a glass substrate and permanent bonding was achieved by further UV treatment and/or oxygen plasma treatment. The final devices were successfully tested for any leakage. These microfluidic chips will be integrated with a sensor and antenna for further biological studies. UV curable adhesives are also used for permanent/temporary sealing of microfluidic channels. These adhesives, which are still new to the fluidics branch can functionally and economically, have a greater impact on microfluidics.
{"title":"Microfluidic chips fabrication from UV curable adhesives for heterogeneous integration","authors":"V. Mokkapati, O. Bethge, R. Hainberger, H. Brueckl","doi":"10.1109/ECTC.2012.6249109","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249109","url":null,"abstract":"Conventional fabrication of microfluidic chips is based on silicon, glass, PDMS and various other polymeric materials (COC, polycarbonate, PMMA etc). Silicon and glass processing technologies are highly developed and the chips can be fabricated with ease. Polymeric microfluidic chips have become very common in recent years due to the demand for the cheap and disposable devices. New entrants in to the field are UV curable adhesives which are gaining recognition as promising players in microfluidics. UV curable adhesives are generally used in various applications ranging from usage in the manufacture of parts of an aircraft to sealing/packaging of microfluidic chips. Unlike any other previously discussed materials UV curable adhesives have the flexibility in alignment and bonding during fabrication process. These adhesives can be applied in between two surfaces which are to be glued and can be left like that for hours to days without bonding them as long as the glue is not exposed to UV light. In this paper we explain the detailed fabrication of microfluidic chips (100μm wide and 3μm (NOA74), 22μm (NOA 68) deep) completely made from UV curable adhesives having better chemical resistance, permeability and flexible surface treatments compared to other known polymeric materials. Firstly the patterns were etched on silicon, followed by PDMS molding and subsequently UV curable adhesives were casted and cured on structured PDMS master. After unmolding the stamps were mounted on a glass substrate and permanent bonding was achieved by further UV treatment and/or oxygen plasma treatment. The final devices were successfully tested for any leakage. These microfluidic chips will be integrated with a sensor and antenna for further biological studies. UV curable adhesives are also used for permanent/temporary sealing of microfluidic channels. These adhesives, which are still new to the fluidics branch can functionally and economically, have a greater impact on microfluidics.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"33 1","pages":"1965-1969"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76223806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249047
S. Babikian, Liang L. Wu, G. Li, M. Bachman
We report the development of a packaged thermal component with integrated sensor for use in integrated microfluidic systems that need to accurately and conveniently control fluid temperature in one or more microfluidic reservoirs. The small surface mounted component can be assembled on a circuit board and encapsulated in biocompatible polymer for use as part of a “lab-on-a-chip” system. Such systems can be readily utilized in miniaturized lab applications that require precision heating, such as cell lysing, polymerase chain reaction (PCR) and sterilization.
{"title":"Microfluidic thermal component for integrated microfluidic systems","authors":"S. Babikian, Liang L. Wu, G. Li, M. Bachman","doi":"10.1109/ECTC.2012.6249047","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249047","url":null,"abstract":"We report the development of a packaged thermal component with integrated sensor for use in integrated microfluidic systems that need to accurately and conveniently control fluid temperature in one or more microfluidic reservoirs. The small surface mounted component can be assembled on a circuit board and encapsulated in biocompatible polymer for use as part of a “lab-on-a-chip” system. Such systems can be readily utilized in miniaturized lab applications that require precision heating, such as cell lysing, polymerase chain reaction (PCR) and sterilization.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"52 1","pages":"1582-1587"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76654826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249020
Wei Lin, S. Wen, A. Yoshida, Jeong-Cheol Shin
Thin substrates have been used in more and more package-on-package (PoP) designs to meet the overall package thickness requirement. Low CTE cores are becoming more popular to reduce thin package warpage. On the other hand, substrates used in the same product are often sourced from multiple suppliers. Packages built with thin substrates sourced from different suppliers were found to have different end-of-line (EOL) package warpage. In this paper, 5 legs of substrates from 3 different suppliers were studied and compared with regard to raw substrate warpage, raw substrate modulus and CTE properties, and their reactions to 1× reflow thermal conditioning in order to understand any correlation to end-of-line package warpage. It was found that raw substrates sourced from different suppliers, or different processes in the same supplier, could have different levels of initial bare substrate warpage due to residual stress. Simulation results showed clear correlation between bare substrate warpage and EOL package warpage. However, such correlation was not observed with the limited measurement data collected. It was also found that properties (CTE and modulus) of finished composite substrates from different suppliers and processes could vary significantly, especially in the high temperature range. The difference in properties could be correlated to the difference at end-of-line package warpage in some cases. Further more, the substrates from different suppliers or processes could change their warpage, modulus and CTE properties in different ways after 1× reflow temperature conditioning. The study shows that it becomes more and more important to have better quality control of substrates sourced from different suppliers as substrate becomes thin and low CTE core is used.
{"title":"Evaluation of raw substrate variation from different suppliers and processes and their impact on package warpage","authors":"Wei Lin, S. Wen, A. Yoshida, Jeong-Cheol Shin","doi":"10.1109/ECTC.2012.6249020","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249020","url":null,"abstract":"Thin substrates have been used in more and more package-on-package (PoP) designs to meet the overall package thickness requirement. Low CTE cores are becoming more popular to reduce thin package warpage. On the other hand, substrates used in the same product are often sourced from multiple suppliers. Packages built with thin substrates sourced from different suppliers were found to have different end-of-line (EOL) package warpage. In this paper, 5 legs of substrates from 3 different suppliers were studied and compared with regard to raw substrate warpage, raw substrate modulus and CTE properties, and their reactions to 1× reflow thermal conditioning in order to understand any correlation to end-of-line package warpage. It was found that raw substrates sourced from different suppliers, or different processes in the same supplier, could have different levels of initial bare substrate warpage due to residual stress. Simulation results showed clear correlation between bare substrate warpage and EOL package warpage. However, such correlation was not observed with the limited measurement data collected. It was also found that properties (CTE and modulus) of finished composite substrates from different suppliers and processes could vary significantly, especially in the high temperature range. The difference in properties could be correlated to the difference at end-of-line package warpage in some cases. Further more, the substrates from different suppliers or processes could change their warpage, modulus and CTE properties in different ways after 1× reflow temperature conditioning. The study shows that it becomes more and more important to have better quality control of substrates sourced from different suppliers as substrate becomes thin and low CTE core is used.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"1 1","pages":"1406-1411"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78251613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248856
M. Henry, K. D. Greth, J. Nguyen, C. Nordquist, R. Shul, M. Wiwi, T. A. Plut, R. Olsson
The work presented here details the wafer-level fabrication and integration of aluminum nitride (AlN) micro resonators into hermetic micro environments. By etching cavities into the lid wafer and then bonding the lid wafer to a wafer of AlN micro resonators, a hermetic micro environment is created. After bonding, the lid wafer is thinned by plasma etching to expose individual die. This sequence presents the opportunity to perform resonator release on a wafer level while providing protection from dicing and other fabrication steps. We present here, fabrication and integration specifics on the wafer-level-packaging (WLP). Further we detail challenges encountered during the integration process including: elimination of micro voids created during eutectic wafer bonding, the use of plasma etching of lid wafers as a replacement to polish based wafer thinning, techniques to confirm hermetic environments, and significant failure mechanisms of the process limiting yield. Finally, we quantify improvements of the AlN micro resonators by correlating quality factors and integrated Pirani gauges.
{"title":"Hermetic wafer-level packaging for RF MEMs: Effects on resonator performance","authors":"M. Henry, K. D. Greth, J. Nguyen, C. Nordquist, R. Shul, M. Wiwi, T. A. Plut, R. Olsson","doi":"10.1109/ECTC.2012.6248856","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248856","url":null,"abstract":"The work presented here details the wafer-level fabrication and integration of aluminum nitride (AlN) micro resonators into hermetic micro environments. By etching cavities into the lid wafer and then bonding the lid wafer to a wafer of AlN micro resonators, a hermetic micro environment is created. After bonding, the lid wafer is thinned by plasma etching to expose individual die. This sequence presents the opportunity to perform resonator release on a wafer level while providing protection from dicing and other fabrication steps. We present here, fabrication and integration specifics on the wafer-level-packaging (WLP). Further we detail challenges encountered during the integration process including: elimination of micro voids created during eutectic wafer bonding, the use of plasma etching of lid wafers as a replacement to polish based wafer thinning, techniques to confirm hermetic environments, and significant failure mechanisms of the process limiting yield. Finally, we quantify improvements of the AlN micro resonators by correlating quality factors and integrated Pirani gauges.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"38 1","pages":"362-369"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77663207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249036
S. Ura, T. Majima, K. Kintaka, K. Hatanaka, J. Inoue, K. Nishio, Y. Awatsuji
A cavity-resonator-integrated guided-mode-resonance filter (CRIGF) consisting of a grating coupler (GC) and a pair of distributed-Bragg-reflectors (DBRs) on a thin film waveguide has been recently proposed and investigated to provide a narrow-band reflection spectrum for an incident wave of a small beam width from the free space. A CRIGF demonstrated so far shows polarization dependence because propagation constants of guided waves excited by GC are different between TE and TM incident waves. In order to construct a polarization-independent guided-mode resonance filter with small aperture, an integration of two CRIGFs crossed each other was proposed and discussed in this paper. A device was designed for a resonance wavelength of 1550 nm and its reflection and transmission spectra were predicted by a newly developed analysis based on the coupled-mode theory. A reflectance of 96 % with 1 nm bandwidth was expected for an incident beam diameter of 10 μm. A test sample working at 846 nm was fabricated and characterized. A Ge:SiO2 guiding core layer was deposited on a SiO2 glass substrate, and GC and DBRs were formed by the electron-beam direct writing lithography. Measured reflection spectra for TE and TM incident beams were well coincident with each other.
{"title":"Small-aperture guided-mode-resonance filter with cavity resonators","authors":"S. Ura, T. Majima, K. Kintaka, K. Hatanaka, J. Inoue, K. Nishio, Y. Awatsuji","doi":"10.1109/ECTC.2012.6249036","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249036","url":null,"abstract":"A cavity-resonator-integrated guided-mode-resonance filter (CRIGF) consisting of a grating coupler (GC) and a pair of distributed-Bragg-reflectors (DBRs) on a thin film waveguide has been recently proposed and investigated to provide a narrow-band reflection spectrum for an incident wave of a small beam width from the free space. A CRIGF demonstrated so far shows polarization dependence because propagation constants of guided waves excited by GC are different between TE and TM incident waves. In order to construct a polarization-independent guided-mode resonance filter with small aperture, an integration of two CRIGFs crossed each other was proposed and discussed in this paper. A device was designed for a resonance wavelength of 1550 nm and its reflection and transmission spectra were predicted by a newly developed analysis based on the coupled-mode theory. A reflectance of 96 % with 1 nm bandwidth was expected for an incident beam diameter of 10 μm. A test sample working at 846 nm was fabricated and characterized. A Ge:SiO2 guiding core layer was deposited on a SiO2 glass substrate, and GC and DBRs were formed by the electron-beam direct writing lithography. Measured reflection spectra for TE and TM incident beams were well coincident with each other.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"11 1","pages":"1511-1517"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80143117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248844
V. Sundaram, Q. Chen, Y. Suzuki, G. Kumar, Fuhan Liu, R. Tummala
This paper presents the design, fabrication and electrical characterization of a low loss and low cost non-traditional silicon interposer, demonstrating the high bandwidth chip-to-chip interconnection capability of the 3D silicon interposer, with equivalent or better performance than 3D ICs with TSVs, at a much lower cost. This scalable approach uses thin polycrystalline silicon in wafer or panel form, forms lower cost through-package-vias (TPVs) at fine pitch by special high throughput laser processes. The electrical performance is improved by thick polymer liners within the TPVs. Double side package processes for TPV metallization and RDL layers using dry film polymers and plating leads to significant cost reduction compared to single side TSV and BEOL wafer processes. Combined loss of 3mm long CPW lines and two TPVs in the low loss silicon interposer was demonstrated at less than 1dB at 10GHz. The fine pitch TPV capability and low loss of this non-traditional silicon interposer leads to 3D interposers with double side chips interconnected at equivalent bandwidth to wide bus I/O 3D ICs at a much lower cost and with better testability, thermal management and scalability.
本文介绍了一种低损耗、低成本的非传统硅中间体的设计、制造和电学特性，展示了3D硅中间体的高带宽片对片互连能力，其性能与带有tsv的3D集成电路相当或更好，成本低得多。这种可扩展的方法使用晶圆或面板形式的薄多晶硅，通过特殊的高通量激光工艺在细间距上形成低成本的通封装通孔(TPVs)。电性能得到改善的厚聚合物衬里的TPVs。与单面TSV和BEOL晶圆工艺相比，使用干膜聚合物和电镀的TPV金属化和RDL层的双面封装工艺可显着降低成本。低损耗硅中间体中3mm长的CPW线和两个TPVs的综合损耗在10GHz时小于1dB。这种非传统硅中间体的细间距TPV能力和低损耗导致具有双面芯片的3D中间体以同等带宽与宽总线I/O 3D ic互连，成本低得多，具有更好的可测试性，热管理和可扩展性。
{"title":"Low-cost and low-loss 3D silicon interposer for high bandwidth logic-to-memory interconnections without TSV in the logic IC","authors":"V. Sundaram, Q. Chen, Y. Suzuki, G. Kumar, Fuhan Liu, R. Tummala","doi":"10.1109/ECTC.2012.6248844","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248844","url":null,"abstract":"This paper presents the design, fabrication and electrical characterization of a low loss and low cost non-traditional silicon interposer, demonstrating the high bandwidth chip-to-chip interconnection capability of the 3D silicon interposer, with equivalent or better performance than 3D ICs with TSVs, at a much lower cost. This scalable approach uses thin polycrystalline silicon in wafer or panel form, forms lower cost through-package-vias (TPVs) at fine pitch by special high throughput laser processes. The electrical performance is improved by thick polymer liners within the TPVs. Double side package processes for TPV metallization and RDL layers using dry film polymers and plating leads to significant cost reduction compared to single side TSV and BEOL wafer processes. Combined loss of 3mm long CPW lines and two TPVs in the low loss silicon interposer was demonstrated at less than 1dB at 10GHz. The fine pitch TPV capability and low loss of this non-traditional silicon interposer leads to 3D interposers with double side chips interconnected at equivalent bandwidth to wide bus I/O 3D ICs at a much lower cost and with better testability, thermal management and scalability.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"1 1","pages":"292-297"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80199194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248995
S. Yoon, Jose Alvin Caparas, Yaojian Lin, P. Marimuthu
Current portable electronic products are driving component packaging towards 3D packaging technologies for integrating multiple memory die and application processors (AP). Among the 3D technologies, Package-on-Package (PoP) is increasingly becoming mainstream due to its flexibility of combination and sourcing. Moreover, device designs require functional integration of IC's, especially in the 3rd dimension, hence driving new technology development towards making IC components “thin and thinner”. eWLB (embedded Wafer Level Ball Grid Array) has been introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. There is also great opportunity related to a 3D variation of eWLB which would allow for mounting of components or another package on the top surface with thinner profile and Package-on-Package (eWBL-PoP) technology. 3D PoP-eWLB is envisioned as an exciting technology which will open up the floodgates for system level integration utilizing very thin stacked eWLB packages as building blocks in mobile applications. This paper reports developments that are aimed to extend the low profile PoP application with eWLB + PoP technology. Test vehicle is designed and fabricated to demonstrate to be thin and 3D PoP solution for mobile and portable electronics. Assembly process details including laser ablation and interconnects process and mechanical characterizations are to be discussed with component and board level reliability results. Innovative package structures optimization that provide dual advantages of both form factor reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, package with multi layer redistribution (RDL) and 10um/10um line width/spacing is fabricated and implemented on eWLB platform. Successful reliability characterization results on low profile PoP package configurations are reported that demonstrate eWLB-PoP as an enabling technology for miniaturized, low profile and cost-effective 3D PoP.
{"title":"Advanced low profile PoP solution with embedded wafer level PoP (eWLB-PoP) technology","authors":"S. Yoon, Jose Alvin Caparas, Yaojian Lin, P. Marimuthu","doi":"10.1109/ECTC.2012.6248995","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248995","url":null,"abstract":"Current portable electronic products are driving component packaging towards 3D packaging technologies for integrating multiple memory die and application processors (AP). Among the 3D technologies, Package-on-Package (PoP) is increasingly becoming mainstream due to its flexibility of combination and sourcing. Moreover, device designs require functional integration of IC's, especially in the 3rd dimension, hence driving new technology development towards making IC components “thin and thinner”. eWLB (embedded Wafer Level Ball Grid Array) has been introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. There is also great opportunity related to a 3D variation of eWLB which would allow for mounting of components or another package on the top surface with thinner profile and Package-on-Package (eWBL-PoP) technology. 3D PoP-eWLB is envisioned as an exciting technology which will open up the floodgates for system level integration utilizing very thin stacked eWLB packages as building blocks in mobile applications. This paper reports developments that are aimed to extend the low profile PoP application with eWLB + PoP technology. Test vehicle is designed and fabricated to demonstrate to be thin and 3D PoP solution for mobile and portable electronics. Assembly process details including laser ablation and interconnects process and mechanical characterizations are to be discussed with component and board level reliability results. Innovative package structures optimization that provide dual advantages of both form factor reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, package with multi layer redistribution (RDL) and 10um/10um line width/spacing is fabricated and implemented on eWLB platform. Successful reliability characterization results on low profile PoP package configurations are reported that demonstrate eWLB-PoP as an enabling technology for miniaturized, low profile and cost-effective 3D PoP.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"82 1","pages":"1250-1254"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80545828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248923
Y. Morikawa, T. Murayama, T. Sakuishi, M. Yoshii, K. Suu
In recent years, "2.5D silicon interposers" and "Full 3D stacked" technology for high-performance LSI has attracted much attention since this technology can solve interconnection problems using TSV (Through Silicon Via) to electrically connect stacked LSI. 2.5D and 3D Si integration has great advantages over conventional two-dimensional devices such as high packaging density, small wire length, high-speed operation, low power consumption, and high feasibility for parallel processing.
{"title":"A novel scallop free TSV etching method in magnetic neutral loop discharge plasma","authors":"Y. Morikawa, T. Murayama, T. Sakuishi, M. Yoshii, K. Suu","doi":"10.1109/ECTC.2012.6248923","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248923","url":null,"abstract":"In recent years, \"2.5D silicon interposers\" and \"Full 3D stacked\" technology for high-performance LSI has attracted much attention since this technology can solve interconnection problems using TSV (Through Silicon Via) to electrically connect stacked LSI. 2.5D and 3D Si integration has great advantages over conventional two-dimensional devices such as high packaging density, small wire length, high-speed operation, low power consumption, and high feasibility for parallel processing.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":"19 1","pages":"794-795"},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83173427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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