Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249010
A. Ghannam, D. Bourrier, L. Ourak, C. Viallon, T. Parra
This work presents a new and low cost multi-level 3D copper interconnect process for RF and microwave applications. This process extends 3D interconnect integration technologies from silicon to above-IC polymer. Therefore, 3D passive devices and multi-level interconnects can be integrated using a single electroplating step making the process suitable for 3D-MMIC integration. 3D interconnects are realized by patterning the SU-8 to specific locations to create the desired 3D shape. A 3D seed layer is deposited above the SU-8 and the substrate to insure 3D electroplating current flow. The BPN is used as a thick mold for copper electroplating with an aspect ratio as high as 16:1. An optimized electroplating process is later used to grow copper in a 3D technique, insuring transition between all metallic layers. Finally, high-Q (60 @ 6 GHz) power inductors have been designed and integrated above a 50 W RF power LDMOS device, using this process.
本文提出了一种新的、低成本的、用于射频和微波应用的多层三维铜互连工艺。该工艺将3D互连集成技术从硅扩展到ic以上聚合物。因此，3D无源器件和多层次互连可以使用单个电镀步骤集成，使该工艺适合3D- mmic集成。3D互连是通过将SU-8图案化到特定位置以创建所需的3D形状来实现的。3D种子层沉积在SU-8和基板之上，以确保3D电镀电流的流动。BPN是电镀铜用的厚模，宽高比高达16:1。优化的电镀工艺随后用于在3D技术中生长铜，确保所有金属层之间的过渡。最后，采用该工艺设计了高q (60 @ 6 GHz)功率电感器，并将其集成在50 W RF功率LDMOS器件上。
{"title":"Low cost 3D multilevel interconnect integration for RF and microwave applications","authors":"A. Ghannam, D. Bourrier, L. Ourak, C. Viallon, T. Parra","doi":"10.1109/ECTC.2012.6249010","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249010","url":null,"abstract":"This work presents a new and low cost multi-level 3D copper interconnect process for RF and microwave applications. This process extends 3D interconnect integration technologies from silicon to above-IC polymer. Therefore, 3D passive devices and multi-level interconnects can be integrated using a single electroplating step making the process suitable for 3D-MMIC integration. 3D interconnects are realized by patterning the SU-8 to specific locations to create the desired 3D shape. A 3D seed layer is deposited above the SU-8 and the substrate to insure 3D electroplating current flow. The BPN is used as a thick mold for copper electroplating with an aspect ratio as high as 16:1. An optimized electroplating process is later used to grow copper in a 3D technique, insuring transition between all metallic layers. Finally, high-Q (60 @ 6 GHz) power inductors have been designed and integrated above a 50 W RF power LDMOS device, using this process.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87484836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248968
J. Knickerbocker, P. Andry, E. Colgan, B. Dang, T. Dickson, X. Gu, C. Haymes, C. Jahnes, Y. Liu, J. Maria, R. Polastre, C. Tsang, L. Turlapati, B. Webb, L. Wiggins, S. Wright
Three-dimensional (3D) chip integration with through-silicon-vias (TSV's) can enable system benefits of enhanced performance, power efficiency, and cost reduction leveraging micro-architecture designs such as 2.5D silicon packages and 3D die stacks. 2.5D silicon packages and 3D die stacks structures integrated in modules each have unique technical challenges but each can provide system benefits including lower latency and higher bandwidth compared to traditional packaging solutions. Additional system benefits using 2.5D or 3D integration can include product miniaturization or increased function in the same size product. Leveraging proper design and micro-architecture for a system application, 3D technology can aide chip manufacturability for lower costs, sub-component heterogeneous integration, modular design and sub-component design reuse, which can reduce development expense and decrease time to market. 2.5D and 3D technology can reduce interconnection length between circuits leading to lower power consumption and lower latency as well as increase the number of interconnections which supports increased bandwidth to traditional 2D off chip interconnection. Appropriate design ground rules, clocking, and electrical models should match well defined technology attributes such as TSV's and silicon to silicon interconnection electrical parametrics. In addition a wafer test methodology for known good die (KGD) and high yield assembly integration approach are important to obtain integrated 2.5D and 3D modules. For complex 3D integration, proper consideration for module or integrated die stacked with TSV's and Si to Si interconnection may require redundancy and an integral repair methodology. 2.5D and 3D technology challenges may include an increase in the power delivery and cooling requirements to meet the increased circuit density and power density of these structures. For small, low power applications such as mobile devices, 2.5D and 3D technology can provide substantial benefit through both performance benefit and power savings and lead to longer battery life for the same function. For some high performance and high power applications, the 2.5D approach simplifies heterogeneous die integration without requiring leading to increases power density and heat removal cooling density. Whereas some high performance and high power applications using 3D technology may require extensive planning for power delivery with localized power regulation and specialized cooling approaches to avoid excessive in die stack temperatures while taking advantage of performance gains that these short links between heterogeneous die can provide. 3D die stacks using multi-core processors and wide I/O DRAM, eDRAM, SRAM or cache stacks can provide high bandwidth, performance improvements with lower latency. In addition to the power delivery and thermal challenges of 2.5D and 3D described above, there are 3D fabrication and industry compatibility challenges. Technology challenges i
{"title":"2.5D and 3D technology challenges and test vehicle demonstrations","authors":"J. Knickerbocker, P. Andry, E. Colgan, B. Dang, T. Dickson, X. Gu, C. Haymes, C. Jahnes, Y. Liu, J. Maria, R. Polastre, C. Tsang, L. Turlapati, B. Webb, L. Wiggins, S. Wright","doi":"10.1109/ECTC.2012.6248968","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248968","url":null,"abstract":"Three-dimensional (3D) chip integration with through-silicon-vias (TSV's) can enable system benefits of enhanced performance, power efficiency, and cost reduction leveraging micro-architecture designs such as 2.5D silicon packages and 3D die stacks. 2.5D silicon packages and 3D die stacks structures integrated in modules each have unique technical challenges but each can provide system benefits including lower latency and higher bandwidth compared to traditional packaging solutions. Additional system benefits using 2.5D or 3D integration can include product miniaturization or increased function in the same size product. Leveraging proper design and micro-architecture for a system application, 3D technology can aide chip manufacturability for lower costs, sub-component heterogeneous integration, modular design and sub-component design reuse, which can reduce development expense and decrease time to market. 2.5D and 3D technology can reduce interconnection length between circuits leading to lower power consumption and lower latency as well as increase the number of interconnections which supports increased bandwidth to traditional 2D off chip interconnection. Appropriate design ground rules, clocking, and electrical models should match well defined technology attributes such as TSV's and silicon to silicon interconnection electrical parametrics. In addition a wafer test methodology for known good die (KGD) and high yield assembly integration approach are important to obtain integrated 2.5D and 3D modules. For complex 3D integration, proper consideration for module or integrated die stacked with TSV's and Si to Si interconnection may require redundancy and an integral repair methodology. 2.5D and 3D technology challenges may include an increase in the power delivery and cooling requirements to meet the increased circuit density and power density of these structures. For small, low power applications such as mobile devices, 2.5D and 3D technology can provide substantial benefit through both performance benefit and power savings and lead to longer battery life for the same function. For some high performance and high power applications, the 2.5D approach simplifies heterogeneous die integration without requiring leading to increases power density and heat removal cooling density. Whereas some high performance and high power applications using 3D technology may require extensive planning for power delivery with localized power regulation and specialized cooling approaches to avoid excessive in die stack temperatures while taking advantage of performance gains that these short links between heterogeneous die can provide. 3D die stacks using multi-core processors and wide I/O DRAM, eDRAM, SRAM or cache stacks can provide high bandwidth, performance improvements with lower latency. In addition to the power delivery and thermal challenges of 2.5D and 3D described above, there are 3D fabrication and industry compatibility challenges. Technology challenges i","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87513698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248862
Zhuo Li, Rongwei Zhang, Yan Liu, T. Le, C. Wong
We demonstrated a novel approach to synthesize flexible isotropic conductive adhesives (ICAs) that can not only withstand a high deformation rate but also exhibit superior electrical conductivity and adhesion strength. The ICA is made of polyurethane (PU) filled with silver flakes. It can achieve resistivity as low as 1.1×10-5 Ω.cm at 80 wt.% loadings, which is even better than most solders. The high electrical conductivity results from 1) large shrinkage of the PU matrix during cuing; 2) the in-situ reduction of the silver carboxylate layer present on the surface of silver flakes by the selected curing agent so that direct metallic contact can be formed between silver flakes; 3) the microphase separation that is unique to PU matrix providing more conduction paths. The combination of the three above effects leads to the superior electrical conductivity that can be rarely seen in other ICA materials at equivalent loading level. In terms of adhesion, lap shear test measurements show that the adhesion strength to Cu surfaces at room temperature can reach 0.12 kg/mm2 at 80 wt% loading, equivalent to some epoxy based ICAs reported before. In addition, the developed ICAs have also demonstrated other advantages such as a low curing temperature, which enable them to be printed on low cost and flexible substrates such as paper and fabrics; simple and cost-effective processing, eliminating the usage of Ag nanoparticles to achieve high electrical conductivity; and good bio-compatibility. These superior material properties combined with low cost and simple processing make it very promising for emerging flexible electronics. A wearable antenna fabricated by printing the PU based ICAs on flexible fabrics was also presented as a demonstration of such devices.
{"title":"Highly conductive, flexible, bio-compatible poly-urethane based isotropic conductive adhesives for flexible electronics","authors":"Zhuo Li, Rongwei Zhang, Yan Liu, T. Le, C. Wong","doi":"10.1109/ECTC.2012.6248862","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248862","url":null,"abstract":"We demonstrated a novel approach to synthesize flexible isotropic conductive adhesives (ICAs) that can not only withstand a high deformation rate but also exhibit superior electrical conductivity and adhesion strength. The ICA is made of polyurethane (PU) filled with silver flakes. It can achieve resistivity as low as 1.1×10-5 Ω.cm at 80 wt.% loadings, which is even better than most solders. The high electrical conductivity results from 1) large shrinkage of the PU matrix during cuing; 2) the in-situ reduction of the silver carboxylate layer present on the surface of silver flakes by the selected curing agent so that direct metallic contact can be formed between silver flakes; 3) the microphase separation that is unique to PU matrix providing more conduction paths. The combination of the three above effects leads to the superior electrical conductivity that can be rarely seen in other ICA materials at equivalent loading level. In terms of adhesion, lap shear test measurements show that the adhesion strength to Cu surfaces at room temperature can reach 0.12 kg/mm2 at 80 wt% loading, equivalent to some epoxy based ICAs reported before. In addition, the developed ICAs have also demonstrated other advantages such as a low curing temperature, which enable them to be printed on low cost and flexible substrates such as paper and fabrics; simple and cost-effective processing, eliminating the usage of Ag nanoparticles to achieve high electrical conductivity; and good bio-compatibility. These superior material properties combined with low cost and simple processing make it very promising for emerging flexible electronics. A wearable antenna fabricated by printing the PU based ICAs on flexible fabrics was also presented as a demonstration of such devices.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87884672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248895
P. Saettler, M. Boettcher, K. Wolter
Herein we describe the annealing behavior of copper Through Silicon Vias (TSVs) in a series of experiments. Temperatures ranged from 150°C to 450°C and the dwell of the temperature varied between 30 min and 4 h. Copper protrusion, test samples warpage and the copper microstructure were examined in a subsequent characterization. Combining the results of these measurements enables the determination of an optimized temperature and dwell set, which avoids further protrusion and minimizes stress after annealing. Additionally, the data analysis shows a temperature- and dwell-dependency of copper protrusion and die warpage. Electron backscatter diffraction (EBSD) measurements on TSV cross sections show changes of the micro structure. Hence it could be verified that copper underwent grain growth during annealing. The described investigations represent a new systematic approach for the characterization of the copper annealing behavior in TSVs. The evaluation of the specific experiments and the comparison between different annealing conditions enable insights into the structural changes of the material during the annealing process. With help of the implemented characterization this approach succeeds in giving optimized settings for the TSV annealing process. Based on the measurement data it is possible to choose a suitable temperature and dwell process set depending on subsequent redirection layer (RDL) processing steps. Furthermore a model for the annealing procedure in TSVs is derived from the measurement results.
{"title":"Characterization of the annealing behavior for copper-filled TSVs","authors":"P. Saettler, M. Boettcher, K. Wolter","doi":"10.1109/ECTC.2012.6248895","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248895","url":null,"abstract":"Herein we describe the annealing behavior of copper Through Silicon Vias (TSVs) in a series of experiments. Temperatures ranged from 150°C to 450°C and the dwell of the temperature varied between 30 min and 4 h. Copper protrusion, test samples warpage and the copper microstructure were examined in a subsequent characterization. Combining the results of these measurements enables the determination of an optimized temperature and dwell set, which avoids further protrusion and minimizes stress after annealing. Additionally, the data analysis shows a temperature- and dwell-dependency of copper protrusion and die warpage. Electron backscatter diffraction (EBSD) measurements on TSV cross sections show changes of the micro structure. Hence it could be verified that copper underwent grain growth during annealing. The described investigations represent a new systematic approach for the characterization of the copper annealing behavior in TSVs. The evaluation of the specific experiments and the comparison between different annealing conditions enable insights into the structural changes of the material during the annealing process. With help of the implemented characterization this approach succeeds in giving optimized settings for the TSV annealing process. Based on the measurement data it is possible to choose a suitable temperature and dwell process set depending on subsequent redirection layer (RDL) processing steps. Furthermore a model for the annealing procedure in TSVs is derived from the measurement results.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88504710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248985
Y. Liu, Qiuxiao Qian, M. Ring, Jihwan Kim, D. Kinzer
Comprehensive finite element analysis (FEA) modeling is carried out to improve the performance of critical designs of wafer level chip scale package (WLCSP). First, a design with one layer redistribution layout (RDL) copper with etched pocket in the non-covered UBM area and one layer polyimide structure (1Cu1Pi design) is investigated. Different polyimide layouts, copper thicknesses, pocket parameters and non-covered UBM diameters are studied through finite element modeling. Then, a stacked metal design with the sputtered copper UBM stacked on the RDL copper layer, with one polyimide layer between them (2Cu1Pi) for the WLCSP is examined. Parameter study of different UBM diameters with the same solder volume and different UBM diameters with the same solder joint height is conducted by the simulation. Finally the correlation and comparison of the failure mechanism between the modeling and the test are presented and discussed.
{"title":"Modeling for critical design and performance of wafer level chip scale package","authors":"Y. Liu, Qiuxiao Qian, M. Ring, Jihwan Kim, D. Kinzer","doi":"10.1109/ECTC.2012.6248985","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248985","url":null,"abstract":"Comprehensive finite element analysis (FEA) modeling is carried out to improve the performance of critical designs of wafer level chip scale package (WLCSP). First, a design with one layer redistribution layout (RDL) copper with etched pocket in the non-covered UBM area and one layer polyimide structure (1Cu1Pi design) is investigated. Different polyimide layouts, copper thicknesses, pocket parameters and non-covered UBM diameters are studied through finite element modeling. Then, a stacked metal design with the sputtered copper UBM stacked on the RDL copper layer, with one polyimide layer between them (2Cu1Pi) for the WLCSP is examined. Parameter study of different UBM diameters with the same solder volume and different UBM diameters with the same solder joint height is conducted by the simulation. Finally the correlation and comparison of the failure mechanism between the modeling and the test are presented and discussed.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88210269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248925
M. Wilke, M. Topper, Hue Quoc Huynh, K. Lang
One of the key technologies for 3D packaging is forming the Through Silicon Vias (TSV) using plasma etching. For the 3D packaging of active devices such as CMOS sensors, which exhibit low to moderate I/O counts, it was shown in recent years, that costs for TSV interconnects can be reduced by producing tapered via features, which ease subsequent process steps such as deposition of dielectrics, metal layers and photo resists. For different applications the adjustment of dedicated via profiles is desirable. For the practical use the process engineer is confronted with a variety of different process parameters, which exhibit strong interactions between each other and therefore make an extensive testing necessary when a new process needs to be developed. The knowledge of these interactions is therefore needed. The etching of tapered TSVs using fluorine based chemistry is discussed in this paper. The influence of the governing process parameters such as pressure, gas flow ratio and power is discussed in order to produce profiles with continuous tangent and minimal surface roughness of the structures. Emerging structures with etching effects such as micro masking or the appearance of profiles with gradient taper are shown in order to reveal guidelines in which direction the process needs to be adjusted to stay in the process window. A model is presented and discussed which is able to predict the profile angle as a function of the process parameters. This gives the ability to produce tapered profiles from 65° to 85° without the burden of an enormous experimental effort. Interrelated etching performance such as photoresist selectivity, etching rate and the occurrence of lateral under etching is presented as well so that design rules can be derived for the specific process.
{"title":"Process modeling of dry etching for the 3D-integration with tapered TSVs","authors":"M. Wilke, M. Topper, Hue Quoc Huynh, K. Lang","doi":"10.1109/ECTC.2012.6248925","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248925","url":null,"abstract":"One of the key technologies for 3D packaging is forming the Through Silicon Vias (TSV) using plasma etching. For the 3D packaging of active devices such as CMOS sensors, which exhibit low to moderate I/O counts, it was shown in recent years, that costs for TSV interconnects can be reduced by producing tapered via features, which ease subsequent process steps such as deposition of dielectrics, metal layers and photo resists. For different applications the adjustment of dedicated via profiles is desirable. For the practical use the process engineer is confronted with a variety of different process parameters, which exhibit strong interactions between each other and therefore make an extensive testing necessary when a new process needs to be developed. The knowledge of these interactions is therefore needed. The etching of tapered TSVs using fluorine based chemistry is discussed in this paper. The influence of the governing process parameters such as pressure, gas flow ratio and power is discussed in order to produce profiles with continuous tangent and minimal surface roughness of the structures. Emerging structures with etching effects such as micro masking or the appearance of profiles with gradient taper are shown in order to reveal guidelines in which direction the process needs to be adjusted to stay in the process window. A model is presented and discussed which is able to predict the profile angle as a function of the process parameters. This gives the ability to produce tapered profiles from 65° to 85° without the burden of an enormous experimental effort. Interrelated etching performance such as photoresist selectivity, etching rate and the occurrence of lateral under etching is presented as well so that design rules can be derived for the specific process.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86723996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248855
M. Matin, K. Ozaki, D. Akai, K. Sawada, M. Ishida
Micro-electro-mechanical systems (MEMS) technology can offer a viable alternative to realize miniaturized and less expensive actuators for deformable mirror in adaptive optics for high resolution retinal imaging. However, during fabrication of such devices, functional multilayered thin films are generally deposited at elevated temperatures. These films are therefore subjected to residual stresses which may result in bending of the structure. The bending thus occurred may lead to failure at interfaces between films. A successful fabrication of device therefore relies on the engineering justification of multi-structured device design and growth parameters used in fabrication. In this paper, we present the design of a piezoelectric (ceramic) thin film based MEMS actuator for deformable mirror used in retinal imaging. A proto-type piezoelectric thin film actuator has been fabricated epitaxially using Pt/PZT/SRO/Pt/γ-Al2O3/Si structure. Advanced 3D finite element simulations were conducted to correlate the bending of fabricated structure with residual stresses. A smart alternative design was also proposed employing an extra layer of aluminium in the diaphragm region. Simulation results predict a failsafe structure when the thickness of extra Al-layer is tailored to an optimal thickness. The outcome of this research can be used to overcome the challenge encountered (bending due to residual stresses) to obtain a failsafe wafer-level packaged MEMS actuator for deformable mirror.
{"title":"Failsafe wafer-level packaging of a piezoelectric MEMS actuator","authors":"M. Matin, K. Ozaki, D. Akai, K. Sawada, M. Ishida","doi":"10.1109/ECTC.2012.6248855","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248855","url":null,"abstract":"Micro-electro-mechanical systems (MEMS) technology can offer a viable alternative to realize miniaturized and less expensive actuators for deformable mirror in adaptive optics for high resolution retinal imaging. However, during fabrication of such devices, functional multilayered thin films are generally deposited at elevated temperatures. These films are therefore subjected to residual stresses which may result in bending of the structure. The bending thus occurred may lead to failure at interfaces between films. A successful fabrication of device therefore relies on the engineering justification of multi-structured device design and growth parameters used in fabrication. In this paper, we present the design of a piezoelectric (ceramic) thin film based MEMS actuator for deformable mirror used in retinal imaging. A proto-type piezoelectric thin film actuator has been fabricated epitaxially using Pt/PZT/SRO/Pt/γ-Al2O3/Si structure. Advanced 3D finite element simulations were conducted to correlate the bending of fabricated structure with residual stresses. A smart alternative design was also proposed employing an extra layer of aluminium in the diaphragm region. Simulation results predict a failsafe structure when the thickness of extra Al-layer is tailored to an optimal thickness. The outcome of this research can be used to overcome the challenge encountered (bending due to residual stresses) to obtain a failsafe wafer-level packaged MEMS actuator for deformable mirror.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87069456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249123
Y. Park, Jiwon Shin, Yong-Won Choi, K. Paik
The IMC growth of fine pitch Cu pillar/SnAg solder bumps used for the chip to chip eutectic bonding of 3D-TSV interconnection was investigated. Most of SnAg solder was rapidly consumed by Cu-Sn intermetallic compound (IMC) growth during the eutectic bonding process. The composition of the IMC phase were identified as Cu-Au-Sn ternary phase and the main TEM diffraction patterns were well matched with the Cu6Sn5 crystal structure and the two week diffraction spots between every two strong spots matched with the superlattice of Au atoms. As a result, it was proved that the Cu-Au-Sn ternary IMCs were (Cu, Au)6Sn5. In the case of a large solder joint such as BGA (Ball Grid Array) or CSP (Chip Scale Package), most of the Au deposited on a metal pad was dissolved in the melting solder region due to relatively little Au content. However, in the case of TSV Cu pillar/SnAg solder bump jointed on the Au coated Cu pad, Au atoms were completely dissolved in the solder and participated in the IMC reaction due to the very small amount of solder.
{"title":"A study on the intermetallic growth of fine-pitch Cu pillar/SnAg solder bump for 3D-TSV interconnection","authors":"Y. Park, Jiwon Shin, Yong-Won Choi, K. Paik","doi":"10.1109/ECTC.2012.6249123","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249123","url":null,"abstract":"The IMC growth of fine pitch Cu pillar/SnAg solder bumps used for the chip to chip eutectic bonding of 3D-TSV interconnection was investigated. Most of SnAg solder was rapidly consumed by Cu-Sn intermetallic compound (IMC) growth during the eutectic bonding process. The composition of the IMC phase were identified as Cu-Au-Sn ternary phase and the main TEM diffraction patterns were well matched with the Cu6Sn5 crystal structure and the two week diffraction spots between every two strong spots matched with the superlattice of Au atoms. As a result, it was proved that the Cu-Au-Sn ternary IMCs were (Cu, Au)6Sn5. In the case of a large solder joint such as BGA (Ball Grid Array) or CSP (Chip Scale Package), most of the Au deposited on a metal pad was dissolved in the melting solder region due to relatively little Au content. However, in the case of TSV Cu pillar/SnAg solder bump jointed on the Au coated Cu pad, Au atoms were completely dissolved in the solder and participated in the IMC reaction due to the very small amount of solder.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87152173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6249084
J. Lo, S. Lee, Rong Zhang, Mei Li
Solid state lighting is a good alternative light source with reduced energy consumption. Light-emitting diode (LED) is very efficient in turning electrical energy into light. LED has a number of advantages over the traditional light sources. The optical performance of the LED component is very critical. In general, white light can be obtained by applying phosphor on a blue LED chip. The blue light from the LED excites the phosphor to emit yellow light. The blue and yellow light mixes together to give white light. In order to obtain a good optical performance, it is necessary to apply phosphor properly. It is challenging to distribute a right amount of phosphor on the LED die. Besides, phosphor dispensing is usually the slowest process when compared with die bonding and wire bonding. This controls the overall throughput of the LED packaging process. There are different methods to apply the phosphor. The phosphor is mixed with epoxy or silicone to form slurry and is then dispensed onto the chip. However, the spatial color distribution is poor if phosphor slurry is used. Conformal phosphor coating can be used to improve the spatial color distribution. In this paper, an innovative phosphor stencil printing method is proposed. This paper demonstrates the feasibility of the phosphor stencil printing process for wafer-level LED packaging. LEDs are first mounted on a wafer submount. Wire bonds are used as interconnect. The phosphor is stencil printed on the chip surface after wire bond. The minimum phosphor layer thickness is controlled by the wire bond loop height. In order to achieve a low loop height, reverse wire bonding is used. The first bond is on the wafer submount and the second bond is on the LED chip. The reverse wire bond has a very low profile which allows a thin layer of phosphor to be printed on the chip surface. Prototypes are successfully fabricated. A uniform layer of phosphor is stencil printed on the LED chip on the wafer submount. Experimental result shows that the proposed phosphor printing method is very effective in distributing the right amount of phosphor on the chip surface.
{"title":"Reverse wire bonding and phosphor printing for LED wafer level packaging","authors":"J. Lo, S. Lee, Rong Zhang, Mei Li","doi":"10.1109/ECTC.2012.6249084","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6249084","url":null,"abstract":"Solid state lighting is a good alternative light source with reduced energy consumption. Light-emitting diode (LED) is very efficient in turning electrical energy into light. LED has a number of advantages over the traditional light sources. The optical performance of the LED component is very critical. In general, white light can be obtained by applying phosphor on a blue LED chip. The blue light from the LED excites the phosphor to emit yellow light. The blue and yellow light mixes together to give white light. In order to obtain a good optical performance, it is necessary to apply phosphor properly. It is challenging to distribute a right amount of phosphor on the LED die. Besides, phosphor dispensing is usually the slowest process when compared with die bonding and wire bonding. This controls the overall throughput of the LED packaging process. There are different methods to apply the phosphor. The phosphor is mixed with epoxy or silicone to form slurry and is then dispensed onto the chip. However, the spatial color distribution is poor if phosphor slurry is used. Conformal phosphor coating can be used to improve the spatial color distribution. In this paper, an innovative phosphor stencil printing method is proposed. This paper demonstrates the feasibility of the phosphor stencil printing process for wafer-level LED packaging. LEDs are first mounted on a wafer submount. Wire bonds are used as interconnect. The phosphor is stencil printed on the chip surface after wire bond. The minimum phosphor layer thickness is controlled by the wire bond loop height. In order to achieve a low loop height, reverse wire bonding is used. The first bond is on the wafer submount and the second bond is on the LED chip. The reverse wire bond has a very low profile which allows a thin layer of phosphor to be printed on the chip surface. Prototypes are successfully fabricated. A uniform layer of phosphor is stencil printed on the LED chip on the wafer submount. Experimental result shows that the proposed phosphor printing method is very effective in distributing the right amount of phosphor on the chip surface.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85448884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-07-30DOI: 10.1109/ECTC.2012.6248798
J. Roullard, A. Farcy, S. Capraro, T. Lacrevaz, C. Bermond, G. Houzet, J. Charbonnier, C. Fuchs, C. Ferrandon, P. Leduc, B. Fléchet
3D stacking technologies are electrically studied to predict high speed data transmission for memory on logic applications. Maximal frequency of bandwidth for memory-processor and processor-BGA channels are extracted and compared for Face to Face and Face to Back 3D stacking and between an interposer technology. Using expected electrical specifications of Wide IO applications in terms of data rates, a roadmap is proposed in accordance to the integration density, carried out by the TSV density.
对三维堆叠技术进行了电学研究，以预测存储在逻辑应用中的高速数据传输。提取了存储器-处理器和处理器- bga通道的最大带宽频率，并对Face to Face和Face to Back 3D叠加以及中间体技术进行了比较。根据数据速率方面宽IO应用的预期电气规范，根据TSV密度执行的集成密度提出了路线图。
{"title":"Evaluation of 3D interconnect routing and stacking strategy to optimize high speed signal transmission for memory on logic","authors":"J. Roullard, A. Farcy, S. Capraro, T. Lacrevaz, C. Bermond, G. Houzet, J. Charbonnier, C. Fuchs, C. Ferrandon, P. Leduc, B. Fléchet","doi":"10.1109/ECTC.2012.6248798","DOIUrl":"https://doi.org/10.1109/ECTC.2012.6248798","url":null,"abstract":"3D stacking technologies are electrically studied to predict high speed data transmission for memory on logic applications. Maximal frequency of bandwidth for memory-processor and processor-BGA channels are extracted and compared for Face to Face and Face to Back 3D stacking and between an interposer technology. Using expected electrical specifications of Wide IO applications in terms of data rates, a roadmap is proposed in accordance to the integration density, carried out by the TSV density.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85451585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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