Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433858
Johannes Solhusvik, J. Ahn, J. Bosiers, B. Fowler, M. Ikeda, S. Kawahito, Jerry Lin, Dan McGrath, Katsu Nakamura, J. Ohta, Ramchan Woo
High speed imaging is one of the fastest growing semiconductor markets. Growth is currently driven by consumer and industrial applications such as HD video, slow motion play-back, machine vision, 3D range capture, and robotics. This forum will present chip architectures, circuits, and system-level solutions used in CCD and CMOS image sensors for high speed cameras. Technology topics include photon detection devices, pixel circuits and array readout circuits, A/D converters, image processing and interface circuits presented by world leading experts from industry and academia. The potential applications of this technology will be demonstrated by ultra high speed capture solutions for 3D range imaging and robotics. For advanced applications, techniques for outputing high-throughput pixel data using analog or digital interfaces are described. The forum will conclude with a panel discussion where the attendees have the opportunity to ask questions and to share their views, and this all-day forum encourages open information exchange. The targeted participants are circuit designers and concept engineers working on image sensor and camera system design.
{"title":"F4: High-speed image sensor technologies","authors":"Johannes Solhusvik, J. Ahn, J. Bosiers, B. Fowler, M. Ikeda, S. Kawahito, Jerry Lin, Dan McGrath, Katsu Nakamura, J. Ohta, Ramchan Woo","doi":"10.1109/ISSCC.2010.5433858","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433858","url":null,"abstract":"High speed imaging is one of the fastest growing semiconductor markets. Growth is currently driven by consumer and industrial applications such as HD video, slow motion play-back, machine vision, 3D range capture, and robotics. This forum will present chip architectures, circuits, and system-level solutions used in CCD and CMOS image sensors for high speed cameras. Technology topics include photon detection devices, pixel circuits and array readout circuits, A/D converters, image processing and interface circuits presented by world leading experts from industry and academia. The potential applications of this technology will be demonstrated by ultra high speed capture solutions for 3D range imaging and robotics. For advanced applications, techniques for outputing high-throughput pixel data using analog or digital interfaces are described. The forum will conclude with a panel discussion where the attendees have the opportunity to ask questions and to share their views, and this all-day forum encourages open information exchange. The targeted participants are circuit designers and concept engineers working on image sensor and camera system design.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77841550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433869
A. Mazzanti, E. Monaco, M. Pozzoni, F. Svelto
Ultra-scaled CMOS devices offer the possibility of operation beyond 100GHz where new applications are envisioned in the near future, including imaging and spectroscopy systems for scientific, medical, space, and industrial applications at low cost, light weight and easy assembly [1]. However, a long path toward complete systems of any commercial interest is required, even though simple building blocks have already been presented [2–6]. One of the challenges of such high-frequency transceivers is the on-chip reference generation. Adoption of a voltage-controlled oscillator (VCO) at fundamental frequency sets an increasingly severe trade-off between high spectral purity and frequency tuning due to a dramatic reduction of resonator quality factor and large parasitics introduced by active devices and buffers, operating close to the transition frequency. As an example, state-of-the-art varactor-tuned VCOs beyond 100GHz in standard CMOS technology display a tuning range of less than 3%, not enough to cover process spreads [3–5]. An alternative solution relies on frequency multiplication of a lower frequency reference, with the potential advantage of a higher tuning range and lower phase noise set by the lower frequency VCO enslaving the multiplier.
{"title":"A 13.1% tuning range 115GHz frequency generator based on an injection-locked frequency doubler in 65nm CMOS","authors":"A. Mazzanti, E. Monaco, M. Pozzoni, F. Svelto","doi":"10.1109/ISSCC.2010.5433869","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433869","url":null,"abstract":"Ultra-scaled CMOS devices offer the possibility of operation beyond 100GHz where new applications are envisioned in the near future, including imaging and spectroscopy systems for scientific, medical, space, and industrial applications at low cost, light weight and easy assembly [1]. However, a long path toward complete systems of any commercial interest is required, even though simple building blocks have already been presented [2–6]. One of the challenges of such high-frequency transceivers is the on-chip reference generation. Adoption of a voltage-controlled oscillator (VCO) at fundamental frequency sets an increasingly severe trade-off between high spectral purity and frequency tuning due to a dramatic reduction of resonator quality factor and large parasitics introduced by active devices and buffers, operating close to the transition frequency. As an example, state-of-the-art varactor-tuned VCOs beyond 100GHz in standard CMOS technology display a tuning range of less than 3%, not enough to cover process spreads [3–5]. An alternative solution relies on frequency multiplication of a lower frequency reference, with the potential advantage of a higher tuning range and lower phase noise set by the lower frequency VCO enslaving the multiplier.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75948464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433903
A. Agarwal, S. Mathew, S. Hsu, M. Anders, Himanshu Kaul, F. Sheikh, R. Ramanarayanan, S. Srinivasan, R. Krishnamurthy, S. Borkar
Computationally intensive DSP/media processing applications require specialized hardware accelerators to enable higher energy-efficiency on microprocessor platforms. On-die reconfigurable arrays enable flexible accelerators with dynamic on-the-fly programmability while amortizing die area and time-to-market costs across a wide range of workloads. An ultra-low-voltage fine-grained reconfigurable fabric consisting of a hybrid configurable logic block (CLB) array with process/voltage/temperature (PVT) variation-tolerant register file (Fig. 18.2.1), targeted for on-die acceleration of DSP/media algorithms on power-constrained mobile microprocessors, is fabricated in 32nm high-k/metal-gate CMOS [1]. The CLB combines self-decoded look-up tables (LUTs) for random logic with reconfigurable arithmetic building blocks, hybrid 3∶2 compressors with integrated partial product generation, configurable adder/multiplier carry propagation and optimized CLB input/output multiplexers to achieve peak energy-efficiency of 2.6TOPS/W measured at 340mV, 50°C. The register file includes programmable stacked shared keepers and interruptible operation of both write memory cells and set-dominant latches (SDLs), improving Vcc-min by 300mV across PVT variations with a wide dynamic operating range of 320mV–1.2V, enabling simultaneous dynamic supply/frequency optimization across target workloads and power budgets. These features also achieve: (i) nominal CLB performance of 2.4GHz, 5.3mW measured at 1.0V, (ii) robust CLB functionality measured at 260mV, 27MHz (sub-threshold) consuming 12µW, (iii) scalable register file performance up to 8.2GHz, 125mW measured at 1.2V, 50°C with low-voltage near-threshold operation at 320mV, 252MHz consuming 430µW, (iv) 4-tap FIR filter, radix-2 FFT butterfly and 16b string-match algorithms with peak throughput of 2.1GSamples/s, 2.4GSamples/s and 100Gbps respectively, and (v) application-dependent dual-supply power savings up to 34%.
{"title":"A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS","authors":"A. Agarwal, S. Mathew, S. Hsu, M. Anders, Himanshu Kaul, F. Sheikh, R. Ramanarayanan, S. Srinivasan, R. Krishnamurthy, S. Borkar","doi":"10.1109/ISSCC.2010.5433903","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433903","url":null,"abstract":"Computationally intensive DSP/media processing applications require specialized hardware accelerators to enable higher energy-efficiency on microprocessor platforms. On-die reconfigurable arrays enable flexible accelerators with dynamic on-the-fly programmability while amortizing die area and time-to-market costs across a wide range of workloads. An ultra-low-voltage fine-grained reconfigurable fabric consisting of a hybrid configurable logic block (CLB) array with process/voltage/temperature (PVT) variation-tolerant register file (Fig. 18.2.1), targeted for on-die acceleration of DSP/media algorithms on power-constrained mobile microprocessors, is fabricated in 32nm high-k/metal-gate CMOS [1]. The CLB combines self-decoded look-up tables (LUTs) for random logic with reconfigurable arithmetic building blocks, hybrid 3∶2 compressors with integrated partial product generation, configurable adder/multiplier carry propagation and optimized CLB input/output multiplexers to achieve peak energy-efficiency of 2.6TOPS/W measured at 340mV, 50°C. The register file includes programmable stacked shared keepers and interruptible operation of both write memory cells and set-dominant latches (SDLs), improving Vcc-min by 300mV across PVT variations with a wide dynamic operating range of 320mV–1.2V, enabling simultaneous dynamic supply/frequency optimization across target workloads and power budgets. These features also achieve: (i) nominal CLB performance of 2.4GHz, 5.3mW measured at 1.0V, (ii) robust CLB functionality measured at 260mV, 27MHz (sub-threshold) consuming 12µW, (iii) scalable register file performance up to 8.2GHz, 125mW measured at 1.2V, 50°C with low-voltage near-threshold operation at 320mV, 252MHz consuming 430µW, (iv) 4-tap FIR filter, radix-2 FFT butterfly and 16b string-match algorithms with peak throughput of 2.1GSamples/s, 2.4GSamples/s and 100Gbps respectively, and (v) application-dependent dual-supply power savings up to 34%.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80936614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433943
D. Halupka, Safeen Huda, William Song, A. Sheikholeslami, K. Tsunoda, C. Yoshida, M. Aoki
Spin-torque-transfer (STT) magnetoresistive random-access memory (MRAM) [1–3], a successor to field-induced magnetic switching MRAM [4,5], is an emerging non-volatile memory technology that is CMOS-compatible, scalable, and allows for high-speed access. However, two circuit-level challenges remain for STT-MRAM: potentially destructive read access due to device variation and a high-power write access. This paper presents two STT-MRAM access schemes: a negative-resistance read scheme (NRRS) that guarantees non-destructive read by design, and a negative-resistance write scheme (NRWS) that, on average, reduces the write power consumption by 10.5%. A fabricated and measured test-chip in 0.13µm CMOS confirms both properties.
自旋转矩传递(STT)磁阻随机存取存储器(MRAM)[1-3]是场感应磁开关MRAM[4,5]的后继产品，是一种新兴的非易失性存储器技术，具有cmos兼容、可扩展和高速访问的特点。然而，STT-MRAM仍然存在两个电路级挑战:由于设备变化和高功率写访问而潜在的破坏性读访问。本文提出了两种STT-MRAM访问方案:一种是负阻读方案(NRRS)，从设计上保证了非破坏性读，另一种是负阻写方案(NRWS)，平均可将写功耗降低10.5%。制作和测量的0.13 μ m CMOS测试芯片证实了这两种特性。
{"title":"Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS","authors":"D. Halupka, Safeen Huda, William Song, A. Sheikholeslami, K. Tsunoda, C. Yoshida, M. Aoki","doi":"10.1109/ISSCC.2010.5433943","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433943","url":null,"abstract":"Spin-torque-transfer (STT) magnetoresistive random-access memory (MRAM) [1–3], a successor to field-induced magnetic switching MRAM [4,5], is an emerging non-volatile memory technology that is CMOS-compatible, scalable, and allows for high-speed access. However, two circuit-level challenges remain for STT-MRAM: potentially destructive read access due to device variation and a high-power write access. This paper presents two STT-MRAM access schemes: a negative-resistance read scheme (NRRS) that guarantees non-destructive read by design, and a negative-resistance write scheme (NRWS) that, on average, reduces the write power consumption by 10.5%. A fabricated and measured test-chip in 0.13µm CMOS confirms both properties.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86523880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434022
H. Marien, M. Steyaert, N. Aerle, P. Heremans
Organic electronics is expected to find commercial applications in flexible displays, RFID tags and smart sensor systems, e.g. for food industry or biomedical applications. Key benefits of the technology are the direct production of transistors and circuits on flexible plastic foils, the possibility to directly integrate sensors, light sources, light detectors, a.o. with the same technology, and the low processing temperatures that warrant cost-efficient production. However, organic electronics technologies suffer from important drawbacks versus silicon based technologies, such as its intrinsically lower mobility, the large parameter variation and a very low intrinsic transistor gain (typically 5). Moreover as active components almost exclusively p-type transistors are available and as passive components only capacitors exist. In place of resistors, we are limited to only linear biased transistors. Work on organic RFID [1,2] and several types of organic sensors [3] has been presented. Analog designs in organic technology are in their infancy: a first differential amplifier with differential-mode gain of 10 was presented in [4]; design considerations for analog designs were discussed in [5]; a comparator was presented in [6]; and a 6-bit D/A converter based on a C-2C chain in [7]. In the present work, we disclose the first ADC designed, fabricated and measured in an organic technology on plastic foil with a fully analog design approach.
{"title":"An analog organic first-order CT ΔΣ ADC on a flexible plastic substrate with 26.5dB precision","authors":"H. Marien, M. Steyaert, N. Aerle, P. Heremans","doi":"10.1109/ISSCC.2010.5434022","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434022","url":null,"abstract":"Organic electronics is expected to find commercial applications in flexible displays, RFID tags and smart sensor systems, e.g. for food industry or biomedical applications. Key benefits of the technology are the direct production of transistors and circuits on flexible plastic foils, the possibility to directly integrate sensors, light sources, light detectors, a.o. with the same technology, and the low processing temperatures that warrant cost-efficient production. However, organic electronics technologies suffer from important drawbacks versus silicon based technologies, such as its intrinsically lower mobility, the large parameter variation and a very low intrinsic transistor gain (typically 5). Moreover as active components almost exclusively p-type transistors are available and as passive components only capacitors exist. In place of resistors, we are limited to only linear biased transistors. Work on organic RFID [1,2] and several types of organic sensors [3] has been presented. Analog designs in organic technology are in their infancy: a first differential amplifier with differential-mode gain of 10 was presented in [4]; design considerations for analog designs were discussed in [5]; a comparator was presented in [6]; and a 6-bit D/A converter based on a C-2C chain in [7]. In the present work, we disclose the first ADC designed, fabricated and measured in an organic technology on plastic foil with a fully analog design approach.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86948774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433988
Kwang-Chan Lee, Chang-Seok Chae, Gyu-Ha Cho, G. Cho
Cost and size are very important issues for power-management ICs (PMICs), in particular for portable systems where typically multiple voltage levels are required to achieve multi functionality. To meet these requirements, a single-inductor multiple-output (SIMO) switching converter is a very strong candidate. SIMO converters have been the subject of many recent studies and reports [1–3]. The presented converters uses the current-mode controller and PWM with a constant switching frequency. However, designing the feedback control loop of the PWM converters is not an easy task since their stability inherently depends on the load conditions.
{"title":"A PLL-based high-stability single-inductor 6-channel output DC-DC buck converter","authors":"Kwang-Chan Lee, Chang-Seok Chae, Gyu-Ha Cho, G. Cho","doi":"10.1109/ISSCC.2010.5433988","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433988","url":null,"abstract":"Cost and size are very important issues for power-management ICs (PMICs), in particular for portable systems where typically multiple voltage levels are required to achieve multi functionality. To meet these requirements, a single-inductor multiple-output (SIMO) switching converter is a very strong candidate. SIMO converters have been the subject of many recent studies and reports [1–3]. The presented converters uses the current-mode controller and PWM with a constant switching frequency. However, designing the feedback control loop of the PWM converters is not an easy task since their stability inherently depends on the load conditions.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87867160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433833
Long Yan, Joonsung Bae, Seulki Lee, Binhee Kim, Taehwan Roh, Kiseok Song, H. Yoo
Recently, wearable heart monitoring systems have been developed for cardiovascular-related disease [1] with wearable body sensor network (WBSN) [2–3]. The WBSN introduced in [3] monitored ECG at maximum 48 points, and transferred data using arrayed inductive link for cm-range wireless inter-connectivity. However, most of the previous attempts were limited to sense only ECG signals at limited points [2] on the body with limited network coverage [3]. Thoracic impedance variance (TIV) from the change of aortic blood volume and velocity at each cardiac cycle provides important hemodynamic information (stroke volume, cardiac output). Combined with ECG signals from more than 6 points, it enables the early detection of abnormal symptoms of pandemic diseases like hypertension and heart failure so that the patients can take prophylactic measures [6]. In spite of its importance, the TIV detection was not realized in WBSN due to its requirement of high impedance (≪0.2Ω) detection sensitivity which needs to detect AM signal with modulation depth as low as less than 3%. A pure single tone sinusoidal current signal at 1kHz–100kHz [6] is required to realize such a high sensitivity, and only a bulky implementation was reported so far [7]. In this paper, we report a 3.9mW low power SoC with body-channel-transceiver (BCT), which can detect TIV (0.1Ω) and ECG (up to 8 points) concurrently. The chip is integrated on a 4-layer fabric circuit board with thin flexible battery as a poultice-like plaster. In addition, it can reconfigure the 25-electrode array and optimize them in-situ to automatically consider the user dependency of the TIV/ECG signals. The recorded data is transmitted at 1Mbps through body-channel-communication (BCC) [8] with duty cycle modification to extend battery life time and enlarge the network coverage.
{"title":"A 3.9mW 25-electrode reconfigured thoracic impedance/ECG SoC with body-channel transponder","authors":"Long Yan, Joonsung Bae, Seulki Lee, Binhee Kim, Taehwan Roh, Kiseok Song, H. Yoo","doi":"10.1109/ISSCC.2010.5433833","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433833","url":null,"abstract":"Recently, wearable heart monitoring systems have been developed for cardiovascular-related disease [1] with wearable body sensor network (WBSN) [2–3]. The WBSN introduced in [3] monitored ECG at maximum 48 points, and transferred data using arrayed inductive link for cm-range wireless inter-connectivity. However, most of the previous attempts were limited to sense only ECG signals at limited points [2] on the body with limited network coverage [3]. Thoracic impedance variance (TIV) from the change of aortic blood volume and velocity at each cardiac cycle provides important hemodynamic information (stroke volume, cardiac output). Combined with ECG signals from more than 6 points, it enables the early detection of abnormal symptoms of pandemic diseases like hypertension and heart failure so that the patients can take prophylactic measures [6]. In spite of its importance, the TIV detection was not realized in WBSN due to its requirement of high impedance (≪0.2Ω) detection sensitivity which needs to detect AM signal with modulation depth as low as less than 3%. A pure single tone sinusoidal current signal at 1kHz–100kHz [6] is required to realize such a high sensitivity, and only a bulky implementation was reported so far [7]. In this paper, we report a 3.9mW low power SoC with body-channel-transceiver (BCT), which can detect TIV (0.1Ω) and ECG (up to 8 points) concurrently. The chip is integrated on a 4-layer fabric circuit board with thin flexible battery as a poultice-like plaster. In addition, it can reconfigure the 25-electrode array and optimize them in-situ to automatically consider the user dependency of the TIV/ECG signals. The recorded data is transmitted at 1Mbps through body-channel-communication (BCC) [8] with duty cycle modification to extend battery life time and enlarge the network coverage.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90952061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433995
J. Warnock, L. Sigal, D. Wendel, K. Muller, J. Friedrich, V. Zyuban, E. Cannon, A. KleinOsowski
The design of the clocked storage elements (CSEs) and associated local clocking circuitry is a critical consideration for modern microprocessor projects[1], and the POWER7™ chip[2], designed in a 45nm silicon-on-insulator (SOI) technology, was no exception. The digital logic contained over 2M CSEs, and the design of these elements had a major impact not only on the area, power, and performance of the chip, but also on the reliability, testability, and the ability to debug and optimize the hardware. This paper will focus on the special features added to the CSE design with these considerations in mind.
{"title":"POWER7TM local clocking and clocked storage elements","authors":"J. Warnock, L. Sigal, D. Wendel, K. Muller, J. Friedrich, V. Zyuban, E. Cannon, A. KleinOsowski","doi":"10.1109/ISSCC.2010.5433995","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433995","url":null,"abstract":"The design of the clocked storage elements (CSEs) and associated local clocking circuitry is a critical consideration for modern microprocessor projects[1], and the POWER7™ chip[2], designed in a 45nm silicon-on-insulator (SOI) technology, was no exception. The digital logic contained over 2M CSEs, and the design of these elements had a major impact not only on the area, power, and performance of the chip, but also on the reliability, testability, and the ability to debug and optimize the hardware. This paper will focus on the special features added to the CSE design with these considerations in mind.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81230319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433997
S. Dighe, S. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, K. Bowman, J. Howard, J. Tschanz, V. Erraguntla, N. Borkar, V. De, S. Borkar
Many-core processors with on-die network-on-chip (NoC) interconnects have emerged as viable architectures for Single-Instruction/Multiple-Data (SIMD) vector applications and parallel workloads, and have been implemented in 65nm CMOS with Dynamic Voltage-Frequency Scaling (DVFS). Chips with Single-Voltage/Single-Frequency (SVSF) for all cores running homogeneous threads as well as Multiple-Voltage/Multiple-Frequency (MVMF), running heterogeneous applications and using independent V/F control for each core, have been reported. Combination of DVFS with dynamic core-count scaling (or DVFCS) has been proposed to further improve performance & energy efficiency across varying workloads. With technology scaling, both leakage power and core-to-core variations in frequency (Fmax) & leakage due to within-die device parameter variations have become significant, thus creating the need for per-core power gating and variation-aware DVFCS. Recently, variation-aware core mapping has been investigated using high level architectural simulations and statistical variation models.
{"title":"Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor","authors":"S. Dighe, S. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, K. Bowman, J. Howard, J. Tschanz, V. Erraguntla, N. Borkar, V. De, S. Borkar","doi":"10.1109/ISSCC.2010.5433997","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433997","url":null,"abstract":"Many-core processors with on-die network-on-chip (NoC) interconnects have emerged as viable architectures for Single-Instruction/Multiple-Data (SIMD) vector applications and parallel workloads, and have been implemented in 65nm CMOS with Dynamic Voltage-Frequency Scaling (DVFS). Chips with Single-Voltage/Single-Frequency (SVSF) for all cores running homogeneous threads as well as Multiple-Voltage/Multiple-Frequency (MVMF), running heterogeneous applications and using independent V/F control for each core, have been reported. Combination of DVFS with dynamic core-count scaling (or DVFCS) has been proposed to further improve performance & energy efficiency across varying workloads. With technology scaling, both leakage power and core-to-core variations in frequency (Fmax) & leakage due to within-die device parameter variations have become significant, thus creating the need for per-core power gating and variation-aware DVFCS. Recently, variation-aware core mapping has been investigated using high level architectural simulations and statistical variation models.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75733621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433972
Y. Greshishchev, J. Aguirre, M. Besson, R. Gibbins, C. Falt, Philip Flemke, Naim Ben-Hamida, D. Pollex, P. Schvan, Shing-Chi Wang
Progress in 40Gb/s optical dual- polarization (DP) QPSK systems inspired an idea of 100G transmission by optical frequency division multiplexing (FDM) of QPSK-modulated channels [1]. A practical solution suggests two 58Gb/s DP QPSK channels, spaced by 50GHz (Fig. 21.7.1). The challenge is in implementing a 6b ADC operating at sampling rate of 29Gs/s, as compared to 24Gs/s reported before [2]. The other challenge is reduction of ADC sampling jitter. In an interleaved architecture, jitter is limited by the timing mismatch between the clocks of T&H circuits. While initial timing error is compensated during ADC calibration, its spread over the input frequency range and drift may still impact jitter performance. This paper presents, to our knowledge for the first time, a 6b ADC operating up to 40Gs/s with power dissipation ≪ 1.5W. The 30% margin for the sampling rate reduces interleaved timing errors and therefore sampling jitter below 0.25ps-rms. The ADC also includes on-chip test signal synthesizer that generates a gigahertz range sinusoidal signal to simplify production testing.
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