Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434014
Ali Khaki-Firooz, K. Cheng, B. Jagannathan, P. Kulkarni, J. Sleight, D. Shahrjerdi, Josephine B. Chang, Sungjae Lee, Junjun Li, H. Bu, R. Gauthier, B. Doris, G. Shahidi
Extremely thin SOI (ETSOI) MOSFET is an attractive candidate for 22nm technology and beyond due to its excellent short channel control, low leakage current, and immunity to random dopant fluctuation [1–5]. Short channel effects are mainly controlled by channel thickness, so there is no need for aggressive scaling of the gate dielectric. Thus the gate leakage is reduced beyond what is achievable in high-k bulk technologies. Low-power operation is further enhanced by negligible GIDL current due to the undoped channel. In addition, ETSOI devices have inherently no junction leakage by the virtue of thin silicon channel. Higher gate voltage overdrive is achieved for a given supply voltage compared to bulk technologies due to smaller subthreshold slope. This enables low-VDD logic operation. Moreover, low-VDD SRAM functionality is supported by small VT- mismatch in undoped channel [5]. In conventional CMOS technologies, complete device redesign is needed if VT changes are required. In ETSOI, however, threshold voltage is tuned through gate workfunction modulation without change in the channel doping. Thus VT tuning is to a large extent decoupled from device scaling.
{"title":"Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond","authors":"Ali Khaki-Firooz, K. Cheng, B. Jagannathan, P. Kulkarni, J. Sleight, D. Shahrjerdi, Josephine B. Chang, Sungjae Lee, Junjun Li, H. Bu, R. Gauthier, B. Doris, G. Shahidi","doi":"10.1109/ISSCC.2010.5434014","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434014","url":null,"abstract":"Extremely thin SOI (ETSOI) MOSFET is an attractive candidate for 22nm technology and beyond due to its excellent short channel control, low leakage current, and immunity to random dopant fluctuation [1–5]. Short channel effects are mainly controlled by channel thickness, so there is no need for aggressive scaling of the gate dielectric. Thus the gate leakage is reduced beyond what is achievable in high-k bulk technologies. Low-power operation is further enhanced by negligible GIDL current due to the undoped channel. In addition, ETSOI devices have inherently no junction leakage by the virtue of thin silicon channel. Higher gate voltage overdrive is achieved for a given supply voltage compared to bulk technologies due to smaller subthreshold slope. This enables low-VDD logic operation. Moreover, low-VDD SRAM functionality is supported by small VT- mismatch in undoped channel [5]. In conventional CMOS technologies, complete device redesign is needed if VT changes are required. In ETSOI, however, threshold voltage is tuned through gate workfunction modulation without change in the channel doping. Thus VT tuning is to a large extent decoupled from device scaling.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"2015 1","pages":"152-153"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88949828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433942
D. Fischette, A. Loke, Michael M. Oshima, B. Doyle, Roland Bakalski, Richard Joseph DeSantis, Anand Thiruvengadam, C. L. Wang, G. Talbot, E. Fang
As processors emerge with multiple wireline interfaces for high-performance digital media, a common multi-protocol clock system is essential for cost and power reduction. We present a 45nm SOI-CMOS system that clocks an 8-lane processor I/O designed for PCI Express®, DisplayPort, and TMDS. Its ring-VCO PLL (RO-PLL) achieves 0.99ps rms jitter that can be reduced further to 0.55ps upon switching to its auxiliary LC-VCO PLL (LC-PLL). As seen in Fig. 13.2.1, the clock system contains the two independent frequency synthesizers, an arrangement of programmable dividers to provide the required frequencies, and clock distribution circuitry. Furthermore, design-for-test features are embedded to correct for PVT variation for optimum jitter performance and to monitor PLL bandwidth and jitter peaking.
{"title":"A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O","authors":"D. Fischette, A. Loke, Michael M. Oshima, B. Doyle, Roland Bakalski, Richard Joseph DeSantis, Anand Thiruvengadam, C. L. Wang, G. Talbot, E. Fang","doi":"10.1109/ISSCC.2010.5433942","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433942","url":null,"abstract":"As processors emerge with multiple wireline interfaces for high-performance digital media, a common multi-protocol clock system is essential for cost and power reduction. We present a 45nm SOI-CMOS system that clocks an 8-lane processor I/O designed for PCI Express®, DisplayPort, and TMDS. Its ring-VCO PLL (RO-PLL) achieves 0.99ps rms jitter that can be reduced further to 0.55ps upon switching to its auxiliary LC-VCO PLL (LC-PLL). As seen in Fig. 13.2.1, the clock system contains the two independent frequency synthesizers, an arrangement of programmable dividers to provide the required frequencies, and clock distribution circuitry. Furthermore, design-for-test features are embedded to correct for PVT variation for optimum jitter performance and to monitor PLL bandwidth and jitter peaking.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"65 1","pages":"246-247"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87151217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433852
A. Arbabian, B. Afshar, Jun-Chau Chien, Shinwon Kang, Steven Callender, E. Adabi, S. D. Toso, R. Pilard, D. Gloria, A. Niknejad
There is considerable interest in wideband pulse modulation at mm-Wave frequencies for application in radar and medical imaging systems [1,2]. Accuracy and resolution in these respective systems are determined by the minimum pulse width (PW). PWs down to 300ps have previously been reported for 24/79GHz carrier frequencies [1,3]. This paper presents the design of the first pulse-based transmitter with integrated antenna to achieve sub-100ps PWs at mm-Wave frequencies in silicon. The transmitter generates variable measured PWs in the range of 35 to 376ps. To obtain this performance, hybrid PA/antenna switching has been explored in combination with high-speed digital switching circuitry.
{"title":"A 90GHz-carrier 30GHz-bandwidth hybrid switching transmitter with integrated antenna","authors":"A. Arbabian, B. Afshar, Jun-Chau Chien, Shinwon Kang, Steven Callender, E. Adabi, S. D. Toso, R. Pilard, D. Gloria, A. Niknejad","doi":"10.1109/ISSCC.2010.5433852","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433852","url":null,"abstract":"There is considerable interest in wideband pulse modulation at mm-Wave frequencies for application in radar and medical imaging systems [1,2]. Accuracy and resolution in these respective systems are determined by the minimum pulse width (PW). PWs down to 300ps have previously been reported for 24/79GHz carrier frequencies [1,3]. This paper presents the design of the first pulse-based transmitter with integrated antenna to achieve sub-100ps PWs at mm-Wave frequencies in silicon. The transmitter generates variable measured PWs in the range of 35 to 376ps. To obtain this performance, hybrid PA/antenna switching has been explored in combination with high-speed digital switching circuitry.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"32 1","pages":"420-421"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82403844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434007
Masum Hossain, A. C. Carusone
High density multilink interfaces such as QPI and HyperTransport include a dedicated link to carry a synchronous clock from the transmitter to receiver and shared by 5 – 20 data transceivers. Sub-rate clocks ameliorate jitter amplification in lossy channels. The forwarded clock must be frequency-multiplied and aligned with the data at each receiver. Per pin deskewing is done at startup [1]; the optimum deskew setting is stored and the calibration circuitry turned off during normal operation. Jitter on the forwarded clock is correlated with jitter on the data because both are generated by the same transmitter. Hence, jitter tolerance is improved by retiming the data with a clock that tracks correlated jitter on the forwarded clock [2]. However, since the delay of the data and clock paths typically differ by several UI, very high frequency jitter will appear out-of-phase at the receiver and should not be tracked. For a delay mismatch of L UI between clock and data, jitter tolerance is improved by tracking jitter up to fbit /4L [2]. If the mismatch is 5UI, at 4Gb/s and 8Gb/s the clock path jitter tracking bandwidth (JTB) should be 200MHz and 400MHz respectively. In summary, the clock path in a clock forwarded transceiver should provide flexible clock multiplication, a controlled phase shift, and a JTB adjustable over 100's of MHz to accommodate different channel losses, bit rates, and path delay mismatches.
{"title":"A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS","authors":"Masum Hossain, A. C. Carusone","doi":"10.1109/ISSCC.2010.5434007","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434007","url":null,"abstract":"High density multilink interfaces such as QPI and HyperTransport include a dedicated link to carry a synchronous clock from the transmitter to receiver and shared by 5 – 20 data transceivers. Sub-rate clocks ameliorate jitter amplification in lossy channels. The forwarded clock must be frequency-multiplied and aligned with the data at each receiver. Per pin deskewing is done at startup [1]; the optimum deskew setting is stored and the calibration circuitry turned off during normal operation. Jitter on the forwarded clock is correlated with jitter on the data because both are generated by the same transmitter. Hence, jitter tolerance is improved by retiming the data with a clock that tracks correlated jitter on the forwarded clock [2]. However, since the delay of the data and clock paths typically differ by several UI, very high frequency jitter will appear out-of-phase at the receiver and should not be tracked. For a delay mismatch of L UI between clock and data, jitter tolerance is improved by tracking jitter up to fbit /4L [2]. If the mismatch is 5UI, at 4Gb/s and 8Gb/s the clock path jitter tracking bandwidth (JTB) should be 200MHz and 400MHz respectively. In summary, the clock path in a clock forwarded transceiver should provide flexible clock multiplication, a controlled phase shift, and a JTB adjustable over 100's of MHz to accommodate different channel losses, bit rates, and path delay mismatches.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"15 1","pages":"158-159"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89425627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433983
Pengfei Li, Lin Xue, Deepak Bhatia, R. Bashirullah
On-chip or on-package integration of step-up DC-DC converters in a low-voltage process can be attractive for smaller and lighter portable devices powered from single-cell batteries (i.e., NiMH, Fuel cells). To reduce the size of the off-chip components both high frequency (10 to 100s of MHz) [1, 2] and discontinuous-conduction-mode (DCM) switching have been proposed [3]. However, integration of DCM converters is challenging when the required blocking voltages across the switch and rectification stage is higher than the breakdown voltage of the standard devices. This is the case in both diode-connected MOS or CMOS controlled rectifiers for DCM boost converters [3]. Moreover, adaptive dead-time controllers are required for high-efficiency DCM operation. In this paper, we report two high-frequency DCM boost converter topologies with integrated Schottky Barrier Diodes (SBD) and a high voltage synchronous switch in a standard 0.13µm CMOS process. The SBDs are fabricated without additional processing steps to sustain ˜10V reverse voltage for high voltage operation, eliminating the need for dead-time controllers and power hungry high side drivers. The first DC-DC converter is a 100MHz digitally assisted 4-phase boost converter that delivers 240mW from a 1.2V supply with an output voltage range of 3 to 5V; and the second is a 45MHz hybrid boost converter delivering 20mW at 6-to-10V output from a 1.2V supply.
片上或封装集成升压DC-DC转换器在一个低电压过程中可以吸引更小和更轻的便携式设备由单电池供电(即，镍氢，燃料电池)。为了减小片外元件的尺寸，已经提出了高频(10到100兆赫兹)[1,2]和不连续导通模式(DCM)开关[3]。然而，当开关和整流级所需的阻塞电压高于标准器件的击穿电压时，DCM转换器的集成是具有挑战性的。这是在二极管连接MOS或CMOS控制整流器的DCM升压转换器[3]的情况下。此外，为了实现DCM的高效运行，还需要自适应死区时间控制器。在本文中，我们报告了两种高频DCM升压转换器拓扑结构，其中集成了肖特基势垒二极管(SBD)和一个标准0.13 μ m CMOS工艺中的高压同步开关。sdd的制造无需额外的处理步骤，以维持高压操作的~ 10V反向电压，从而消除了对死区时间控制器和耗电高侧驱动器的需求。第一个DC-DC转换器是一个100MHz数字辅助4相升压转换器，从1.2V电源输出240mW，输出电压范围为3至5V;第二个是45MHz混合升压转换器，从1.2V电源输出6到10v输出20mW。
{"title":"Digitally assisted discontinuous conduction mode 5V/100MHz and 10V/45MHz DC-DC boost converters with integrated Schottky diodes in standard 0.13µm CMOS","authors":"Pengfei Li, Lin Xue, Deepak Bhatia, R. Bashirullah","doi":"10.1109/ISSCC.2010.5433983","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433983","url":null,"abstract":"On-chip or on-package integration of step-up DC-DC converters in a low-voltage process can be attractive for smaller and lighter portable devices powered from single-cell batteries (i.e., NiMH, Fuel cells). To reduce the size of the off-chip components both high frequency (10 to 100s of MHz) [1, 2] and discontinuous-conduction-mode (DCM) switching have been proposed [3]. However, integration of DCM converters is challenging when the required blocking voltages across the switch and rectification stage is higher than the breakdown voltage of the standard devices. This is the case in both diode-connected MOS or CMOS controlled rectifiers for DCM boost converters [3]. Moreover, adaptive dead-time controllers are required for high-efficiency DCM operation. In this paper, we report two high-frequency DCM boost converter topologies with integrated Schottky Barrier Diodes (SBD) and a high voltage synchronous switch in a standard 0.13µm CMOS process. The SBDs are fabricated without additional processing steps to sustain ˜10V reverse voltage for high voltage operation, eliminating the need for dead-time controllers and power hungry high side drivers. The first DC-DC converter is a 100MHz digitally assisted 4-phase boost converter that delivers 240mW from a 1.2V supply with an output voltage range of 3 to 5V; and the second is a 45MHz hybrid boost converter delivering 20mW at 6-to-10V output from a 1.2V supply.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"13 1","pages":"206-207"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72726121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434033
N. Kurd, Subramani Bhamidipati, Christopher Mozak, Jeffrey L. Miller, T.M. Wilson, Mahadev Nemani, Muntaquim Chowdhury
The Westmere processor is implemented on a high-к metal-gate 32nm process technology [1] as a compaction of the Nehalem processor family [2]. Figure 5.1.1 shows the 6-core dual-socket server processor and the 2-core single-socket processor for mainstream client. This paper focuses on innovations and circuit optimizations made to the 6-core processor. The 6-core design has 1.17B transistors including the 12MB shared L3 Cache and fits in approximately the same die area as its 45nm 4-core 8MB-L3-cache Nehalem counterpart. The core supports new instructions for accelerating encryption/decryption algorithms, speeds up performance under virtualized environments, and contains a host of other targeted performance features.
{"title":"Westmere: A family of 32nm IA processors","authors":"N. Kurd, Subramani Bhamidipati, Christopher Mozak, Jeffrey L. Miller, T.M. Wilson, Mahadev Nemani, Muntaquim Chowdhury","doi":"10.1109/ISSCC.2010.5434033","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434033","url":null,"abstract":"The Westmere processor is implemented on a high-к metal-gate 32nm process technology [1] as a compaction of the Nehalem processor family [2]. Figure 5.1.1 shows the 6-core dual-socket server processor and the 2-core single-socket processor for mainstream client. This paper focuses on innovations and circuit optimizations made to the 6-core processor. The 6-core design has 1.17B transistors including the 12MB shared L3 Cache and fits in approximately the same die area as its 45nm 4-core 8MB-L3-cache Nehalem counterpart. The core supports new instructions for accelerating encryption/decryption algorithms, speeds up performance under virtualized environments, and contains a host of other targeted performance features.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"69 1","pages":"96-97"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79555280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434006
M. Pozzoni, S. Erba, D. Sanzogni, M. Ganzerli, P. Viola, D. Baldi, M. Repossi, Giorgio Spelgatti, F. Svelto
Backplane communications are rapidly moving beyond 10 Gb/s both in networking and in hard-disk drive interconnection. Decision Feedback Equalization (DFE) and Duobinary (DB) prove to be effective techniques assuring signal integrity in the presence of ISI, but with speed increase the accuracy of the timing recovery brings additional challenges. Half-rate clock DFEs by loop-unrolling are widely applied to avoid feeding back the decided bit within a 1-bit (UI) time, but the alternated eye opening that is created requires an increased circuit complexity to obtain the maximum accuracy in timing recovery [1][2][3]. DB alternative may suffer in the presence of long sequences of incoming toggle patterns (1010…). In fact, in DB the channel frequency response is pre-shaped into a target shape, but toggle patterns are converted into a constant level, thus not providing information to the timing loop [2][4].
{"title":"A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization","authors":"M. Pozzoni, S. Erba, D. Sanzogni, M. Ganzerli, P. Viola, D. Baldi, M. Repossi, Giorgio Spelgatti, F. Svelto","doi":"10.1109/ISSCC.2010.5434006","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434006","url":null,"abstract":"Backplane communications are rapidly moving beyond 10 Gb/s both in networking and in hard-disk drive interconnection. Decision Feedback Equalization (DFE) and Duobinary (DB) prove to be effective techniques assuring signal integrity in the presence of ISI, but with speed increase the accuracy of the timing recovery brings additional challenges. Half-rate clock DFEs by loop-unrolling are widely applied to avoid feeding back the decided bit within a 1-bit (UI) time, but the alternated eye opening that is created requires an increased circuit complexity to obtain the maximum accuracy in timing recovery [1][2][3]. DB alternative may suffer in the presence of long sequences of incoming toggle patterns (1010…). In fact, in DB the channel frequency response is pre-shaped into a target shape, but toggle patterns are converted into a constant level, thus not providing information to the timing loop [2][4].","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"116 1","pages":"164-165"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80795429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433966
J. Deguchi, D. Miyashita, Y. Ogasawara, Gaku Takemura, Masaomi Iwanaga, K. Sami, R. Ito, J. Wadatsumi, Y. Tsuda, S. Oda, S. Kawaguchi, N. Itoh, M. Hamada
Mobile WiMAX complying with the IEEE 802.16e standard is one of the emerging standards and is achieving world-wide penetration. Low-cost implementation is essential and single-chip implementation is a straightforward approach. However, there are many technical challenges such as floor-planning, signal integrity and scalability of analog/RF circuits in an SoC, as well as power reduction in scaled CMOS technologies. In this work, we have designed and fabricated a fully-integrated 2RX × 1TX dual-band direct-conversion transceiver having digital interfaces for a mWiMAX SoC in a 65nm pure CMOS technology. To cope with the constraints of floor-planning while maintaining the signal integrity, inductorless local oscillator (LO) distribution using compact dual-mode fractional dividers is introduced, leading to the reduction of die area. Total noise figure of 3.8dB is achieved by a novel noise-shaping transimpedance amplifier to mitigate the flicker noise of a scaled CMOS device.
{"title":"A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS","authors":"J. Deguchi, D. Miyashita, Y. Ogasawara, Gaku Takemura, Masaomi Iwanaga, K. Sami, R. Ito, J. Wadatsumi, Y. Tsuda, S. Oda, S. Kawaguchi, N. Itoh, M. Hamada","doi":"10.1109/ISSCC.2010.5433966","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433966","url":null,"abstract":"Mobile WiMAX complying with the IEEE 802.16e standard is one of the emerging standards and is achieving world-wide penetration. Low-cost implementation is essential and single-chip implementation is a straightforward approach. However, there are many technical challenges such as floor-planning, signal integrity and scalability of analog/RF circuits in an SoC, as well as power reduction in scaled CMOS technologies. In this work, we have designed and fabricated a fully-integrated 2RX × 1TX dual-band direct-conversion transceiver having digital interfaces for a mWiMAX SoC in a 65nm pure CMOS technology. To cope with the constraints of floor-planning while maintaining the signal integrity, inductorless local oscillator (LO) distribution using compact dual-mode fractional dividers is introduced, leading to the reduction of die area. Total noise figure of 3.8dB is achieved by a novel noise-shaping transimpedance amplifier to mitigate the flicker noise of a scaled CMOS device.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"84 1","pages":"456-457"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81063905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5434005
H. Sugita, K. Sunaga, Koichi Yamaguchi, M. Mizuno
Much effort has been made toward producing a high-speed multi-tap decision feedback equalizer (DFE), which would be a key component in removing inter-symbol interference (ISI) in high-speed chip-to-chip communication. A loop-unrolled approach is widely used in work toward the design of high-speed multi-tap DFEs. It eliminates the feedback operation in first post-cursor equalization [1–3], an operation that limits operational speed in conventional multi-tap DFEs. There are two problems, however, to its application to equalization of 16Gb/s signals. The first is that additional components in the feedback path, used for speculation on the basis of sampled data, increase 2nd-tap feedback delay, preventing high-speed operations. The second problem is that jitter increase in equalized waveforms prevents accurate clock timing recovery because the 1st tap ISI of the waveform is left un-equalized. In response to this situation, we have developed three techniques for achieving 16Gb/s communication: (1) an analog feedforward technique for high-speed 1st-tap ISI equalization, (2) an analog feedforward technique for jitter reduction in equalized edges, and (3) technique for employing bypass feedback and a voltage swing limiter in order to speed-up both 2ndtap and 3rd-tap equalization. We have applied these techniques to a 16Gb/s equalizer fabricated in a 90nm CMOS process, and their use helps achieve a 33% increase in operating speed over that with conventional multi-tap DFEs[3].
{"title":"A 16Gb/s 1st-Tap FFE and 3-Tap DFE in 90nm CMOS","authors":"H. Sugita, K. Sunaga, Koichi Yamaguchi, M. Mizuno","doi":"10.1109/ISSCC.2010.5434005","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434005","url":null,"abstract":"Much effort has been made toward producing a high-speed multi-tap decision feedback equalizer (DFE), which would be a key component in removing inter-symbol interference (ISI) in high-speed chip-to-chip communication. A loop-unrolled approach is widely used in work toward the design of high-speed multi-tap DFEs. It eliminates the feedback operation in first post-cursor equalization [1–3], an operation that limits operational speed in conventional multi-tap DFEs. There are two problems, however, to its application to equalization of 16Gb/s signals. The first is that additional components in the feedback path, used for speculation on the basis of sampled data, increase 2nd-tap feedback delay, preventing high-speed operations. The second problem is that jitter increase in equalized waveforms prevents accurate clock timing recovery because the 1st tap ISI of the waveform is left un-equalized. In response to this situation, we have developed three techniques for achieving 16Gb/s communication: (1) an analog feedforward technique for high-speed 1st-tap ISI equalization, (2) an analog feedforward technique for jitter reduction in equalized edges, and (3) technique for employing bypass feedback and a voltage swing limiter in order to speed-up both 2ndtap and 3rd-tap equalization. We have applied these techniques to a 16Gb/s equalizer fabricated in a 90nm CMOS process, and their use helps achieve a 33% increase in operating speed over that with conventional multi-tap DFEs[3].","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"28 1","pages":"162-163"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75555464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/ISSCC.2010.5433850
M. Jeong, Bonkee Kim, Youngho Cho, Yanggyun Kim, Seyeob Kim, Heeyong Yoo, Jung-Hwan Lee, Jae Kyung Lee, Kyungsoo Jung, Jeiyoung Lee, Junghun Lee, Huikwan Yang, Gerry Taylor, Boeun Kim
For a few years, new mobile broadcasting services were launched in Korea, Japan, Europe and China. The mobile broadcasting markets are maturing rapidly for applications such as mobile cellular phones, car navigation, PMP and so on. The market drives low-cost, low-power and small size significantly for mobile applications and drives multiple functionality and multiple bands [1]. To meet the market requirements, more integration of system blocks and functionality is needed. To achieve this goal, the 65nm CMOS and multistandard and multiband receiver SoC may be suitable solution.
{"title":"A 65nm CMOS low-power small-size multistandard, multiband mobile broadcasting receiver SoC","authors":"M. Jeong, Bonkee Kim, Youngho Cho, Yanggyun Kim, Seyeob Kim, Heeyong Yoo, Jung-Hwan Lee, Jae Kyung Lee, Kyungsoo Jung, Jeiyoung Lee, Junghun Lee, Huikwan Yang, Gerry Taylor, Boeun Kim","doi":"10.1109/ISSCC.2010.5433850","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433850","url":null,"abstract":"For a few years, new mobile broadcasting services were launched in Korea, Japan, Europe and China. The mobile broadcasting markets are maturing rapidly for applications such as mobile cellular phones, car navigation, PMP and so on. The market drives low-cost, low-power and small size significantly for mobile applications and drives multiple functionality and multiple bands [1]. To meet the market requirements, more integration of system blocks and functionality is needed. To achieve this goal, the 65nm CMOS and multistandard and multiband receiver SoC may be suitable solution.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"21 10 1","pages":"460-461"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75591396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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