Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856359
N. Harabech, R. Bouchakour, P. Canet, P. Pannier, J. Sorbier
The simulation of EEPROM memory characteristics is fundamental to the design and optimization of low-power non-volatile memory products. This paper presents a new method for extraction of Fowler-Nordheim parameters in a thin (polysilicon-gate) SiO/sub 2/ oxide. It consists of extraction of the oxide thickness from MOS capacitance characteristics including polysilicon-gate depletion. Then, we use the oxide thickness to estimate the electric field for the extraction of the FN current parameters.
{"title":"Extraction of Fowler-Nordheim parameters of thin SiO/sub 2/ oxide film including polysilicon gate depletion: validation with an EEPROM memory cell","authors":"N. Harabech, R. Bouchakour, P. Canet, P. Pannier, J. Sorbier","doi":"10.1109/ISCAS.2000.856359","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856359","url":null,"abstract":"The simulation of EEPROM memory characteristics is fundamental to the design and optimization of low-power non-volatile memory products. This paper presents a new method for extraction of Fowler-Nordheim parameters in a thin (polysilicon-gate) SiO/sub 2/ oxide. It consists of extraction of the oxide thickness from MOS capacitance characteristics including polysilicon-gate depletion. Then, we use the oxide thickness to estimate the electric field for the extraction of the FN current parameters.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83192806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857433
F. Marino, D. Gevorkian, J. Astola
In this paper, we propose two scalable architecture's (called Arc/sub J/ and Arc*/sub 2/) which perform the Discrete Wavelet Transform (DWT) of an N/sub 0/-sample sequence in only N/sub 0//2 clock cycles. Therefore, they are at least twice as fast as the known architectures. Also, their AT/sup 2/ parameter is approximately 1/2 of that of already existing devices. These results allow either a twice faster processing than that allowed by other architectures working at the same clock frequency (High-Speed utilization), or using a twice lower clock frequency, while reaching the same performance as other architectures. This second possibility permits reducing the power dissipation by a factor of 4 with respect to other architectures (Low-Power utilization). Finally, we shall show that an impressively efficient architecture can be defined as the synthesis of Arc/sub J/ and Arc*/sub 2/ (average efficiency=99.1%, minimum efficiency=93.8%).
{"title":"High-speed/low-power 1-D DWT architectures with high efficiency","authors":"F. Marino, D. Gevorkian, J. Astola","doi":"10.1109/ISCAS.2000.857433","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857433","url":null,"abstract":"In this paper, we propose two scalable architecture's (called Arc/sub J/ and Arc*/sub 2/) which perform the Discrete Wavelet Transform (DWT) of an N/sub 0/-sample sequence in only N/sub 0//2 clock cycles. Therefore, they are at least twice as fast as the known architectures. Also, their AT/sup 2/ parameter is approximately 1/2 of that of already existing devices. These results allow either a twice faster processing than that allowed by other architectures working at the same clock frequency (High-Speed utilization), or using a twice lower clock frequency, while reaching the same performance as other architectures. This second possibility permits reducing the power dissipation by a factor of 4 with respect to other architectures (Low-Power utilization). Finally, we shall show that an impressively efficient architecture can be defined as the synthesis of Arc/sub J/ and Arc*/sub 2/ (average efficiency=99.1%, minimum efficiency=93.8%).","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88586293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856332
Li-Hsun Chen, Wei-Lung Liu, O. Chen
The programmable FIR architectures using different radix numbers of the Booth algorithm are explored. Based on the radix-2' Booth algorithm, the modified transposed direct-form FIR architectures with and without programmable dynamic ranges of input data and filter coefficients are formulated. The complexities, throughput rates and complexities per throughput rate of the FIR architecture with and without various programmable dynamic data ranges are analyzed in different radix numbers of the Booth algorithm. According to our analyses: the radix-4 approach would be a good choice to achieve a low hardware complexity. For a high throughput rate, the radix 16 or higher radix number of the Booth algorithm should be considered. But if complexity per throughput rate is important, then the radix-8 and radix-16 approaches may be preferred in the FIR architecture without and with programmable dynamic data ranges: respectively. Therefore, users can apply our results to determine a suitable radix number of the Booth algorithm for designing the optimized FIR architecture with consideration of the chip area, speed, throughput rate, power consumption and so on.
{"title":"Determination of radix numbers of the Booth algorithm for the optimized programmable FIR architecture","authors":"Li-Hsun Chen, Wei-Lung Liu, O. Chen","doi":"10.1109/ISCAS.2000.856332","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856332","url":null,"abstract":"The programmable FIR architectures using different radix numbers of the Booth algorithm are explored. Based on the radix-2' Booth algorithm, the modified transposed direct-form FIR architectures with and without programmable dynamic ranges of input data and filter coefficients are formulated. The complexities, throughput rates and complexities per throughput rate of the FIR architecture with and without various programmable dynamic data ranges are analyzed in different radix numbers of the Booth algorithm. According to our analyses: the radix-4 approach would be a good choice to achieve a low hardware complexity. For a high throughput rate, the radix 16 or higher radix number of the Booth algorithm should be considered. But if complexity per throughput rate is important, then the radix-8 and radix-16 approaches may be preferred in the FIR architecture without and with programmable dynamic data ranges: respectively. Therefore, users can apply our results to determine a suitable radix number of the Booth algorithm for designing the optimized FIR architecture with consideration of the chip area, speed, throughput rate, power consumption and so on.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87247321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857066
A. Tefas, I. Pitas
A novel method for image authentication is proposed. A watermark signal is embedded in a grayscale or a color host image. The watermark key controls a set of parameters of a chaotic system used for the watermark generation. The use of chaotic mixing increases the security of the proposed method and provides the additional feature of imperceptible encryption of the image owner logo in the host image. The method succeeds in detecting any alteration made in a watermarked image. The proposed method is robust in high quality lossy image compression. It provides the user not only with a measure for the authenticity of the test image but also with an image map that highlights the unaltered image regions when selective tampering has been made.
{"title":"Image authentication using chaotic mixing systems","authors":"A. Tefas, I. Pitas","doi":"10.1109/ISCAS.2000.857066","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857066","url":null,"abstract":"A novel method for image authentication is proposed. A watermark signal is embedded in a grayscale or a color host image. The watermark key controls a set of parameters of a chaotic system used for the watermark generation. The use of chaotic mixing increases the security of the proposed method and provides the additional feature of imperceptible encryption of the image owner logo in the host image. The method succeeds in detecting any alteration made in a watermarked image. The proposed method is robust in high quality lossy image compression. It provides the user not only with a measure for the authenticity of the test image but also with an image map that highlights the unaltered image regions when selective tampering has been made.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87306774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856351
J. Hughes, A. Worapishet, C. Toumazou
A comparative study between switched-capacitors (SC) and switched-current (SI), using speed, power and signal-to-noise-ratio as performance vectors, is presented. To no one's surprise, the analysis suggests that SC outperforms SI considerably for the past and present technologies. However, as processing heads towards lower power supply voltages the performance of SC falls steadily while that of SI remains almost constant. Ultimately, there is a fundamental tendency for the performance gap between SC and SI to steadily reduce and SI performance is expected to match and surpass that of SC during the course of the next decade.
{"title":"Switched-capacitors versus switched-currents: a theoretical comparison [in CMOS]","authors":"J. Hughes, A. Worapishet, C. Toumazou","doi":"10.1109/ISCAS.2000.856351","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856351","url":null,"abstract":"A comparative study between switched-capacitors (SC) and switched-current (SI), using speed, power and signal-to-noise-ratio as performance vectors, is presented. To no one's surprise, the analysis suggests that SC outperforms SI considerably for the past and present technologies. However, as processing heads towards lower power supply voltages the performance of SC falls steadily while that of SI remains almost constant. Ultimately, there is a fundamental tendency for the performance gap between SC and SI to steadily reduce and SI performance is expected to match and surpass that of SC during the course of the next decade.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84823826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857437
M. Re, G. Cardarilli, A. D. Re, R. Lojacono
In this paper an extensive comparison among alternative algorithms for the implementation of a digital demultiplexer has been carried out. The computational complexity, the performances and the accuracy with respect to the quantization noise effects have been evaluated for the different algorithms. In particular, the digital architecture has been designed to replace an analog filter bank composed of six surface acoustic wave (SAW) devices. This implementation is used, at present, by Alenia Space Division in the Eutelsat Hot-Bird satellites. The obtained digital architecture has been mapped on six Altera Flex 10K-100 devices. The final test bed, that includes a complete interface to the Alenia demodulator, has been implemented on a four-layers PCB.
{"title":"FPGA implementation of a demux based on a multirate filter bank","authors":"M. Re, G. Cardarilli, A. D. Re, R. Lojacono","doi":"10.1109/ISCAS.2000.857437","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857437","url":null,"abstract":"In this paper an extensive comparison among alternative algorithms for the implementation of a digital demultiplexer has been carried out. The computational complexity, the performances and the accuracy with respect to the quantization noise effects have been evaluated for the different algorithms. In particular, the digital architecture has been designed to replace an analog filter bank composed of six surface acoustic wave (SAW) devices. This implementation is used, at present, by Alenia Space Division in the Eutelsat Hot-Bird satellites. The obtained digital architecture has been mapped on six Altera Flex 10K-100 devices. The final test bed, that includes a complete interface to the Alenia demodulator, has been implemented on a four-layers PCB.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90565961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857129
M. Casu, G. Masera, G. Piccinini, M. R. Roch, M. Zamboni
This paper presents a new model for CMOS structures delays estimation based on a deep analysis of complex gates behavior. This approach can supply a high level of accuracy. A complex structure is reduced first to series-connected MOS, then the delay equations are applied to that reduced rate. The model is based on a time piecewise linearization so that a strongly nonlinear circuit can he solved using well known linear techniques. The delay formulas involve model parameters as MOS width functions, therefore providing routines suitable for optimization algorithms. The high level of accuracy, the low CPU time and the high degree of scaling capability are proved in the paper. These features make the model attractive for deep submicron technologies.
{"title":"A high accuracy-low complexity model for CMOS delays","authors":"M. Casu, G. Masera, G. Piccinini, M. R. Roch, M. Zamboni","doi":"10.1109/ISCAS.2000.857129","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857129","url":null,"abstract":"This paper presents a new model for CMOS structures delays estimation based on a deep analysis of complex gates behavior. This approach can supply a high level of accuracy. A complex structure is reduced first to series-connected MOS, then the delay equations are applied to that reduced rate. The model is based on a time piecewise linearization so that a strongly nonlinear circuit can he solved using well known linear techniques. The delay formulas involve model parameters as MOS width functions, therefore providing routines suitable for optimization algorithms. The high level of accuracy, the low CPU time and the high degree of scaling capability are proved in the paper. These features make the model attractive for deep submicron technologies.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80710215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857355
Y. Kompatsiaris, George Mantzaras, M. Strintzis
In this paper a procedure is described for the segmentation and tracking of objects in color image sequences. For this purpose, we propose the novel procedure of K-Means with a connectivity constraint algorithm as a general segmentation algorithm combining several types of information including color, motion and compactness. In this algorithm, the use of spatiotemporal regions is introduced since a number of frames is analyzed simultaneously and as a result the same region is present in consequent frames. Experimental results in real image sequences evaluate the performance of the algorithm.
{"title":"Spatiotemporal segmentation and tracking of objects in color image sequences","authors":"Y. Kompatsiaris, George Mantzaras, M. Strintzis","doi":"10.1109/ISCAS.2000.857355","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857355","url":null,"abstract":"In this paper a procedure is described for the segmentation and tracking of objects in color image sequences. For this purpose, we propose the novel procedure of K-Means with a connectivity constraint algorithm as a general segmentation algorithm combining several types of information including color, motion and compactness. In this algorithm, the use of spatiotemporal regions is introduced since a number of frames is analyzed simultaneously and as a result the same region is present in consequent frames. Experimental results in real image sequences evaluate the performance of the algorithm.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88133265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857489
J. Ramírez-Angulo, R. Carvajal, J. Martinez-Heredia
A four quadrant analogue multiplier that operates with a 1.4 V single supply and 0.6 V peak-peak input signals on both inputs is presented. It is based on a new low-voltage class AB differential amplifier with quiescent current control. Current efficiency and random distortion are introduced as quality factors to evaluate the performance of the analog multiplier. The multiplier presented here is characterized by a high current efficiency (50%), high bandwidth (40 MHz) and a high linearity (<1% distortion). Experimental results of a test chip are shown that verify low-voltage, low distortion and wide swing operation. Post layout simulations are presented that verify its wide bandwidth characteristics.
{"title":"1.4 V supply, wide swing, high frequency CMOS analogue multiplier with high current efficiency","authors":"J. Ramírez-Angulo, R. Carvajal, J. Martinez-Heredia","doi":"10.1109/ISCAS.2000.857489","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857489","url":null,"abstract":"A four quadrant analogue multiplier that operates with a 1.4 V single supply and 0.6 V peak-peak input signals on both inputs is presented. It is based on a new low-voltage class AB differential amplifier with quiescent current control. Current efficiency and random distortion are introduced as quality factors to evaluate the performance of the analog multiplier. The multiplier presented here is characterized by a high current efficiency (50%), high bandwidth (40 MHz) and a high linearity (<1% distortion). Experimental results of a test chip are shown that verify low-voltage, low distortion and wide swing operation. Post layout simulations are presented that verify its wide bandwidth characteristics.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86963876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.857120
F. Diotalevi, M. Valle, G. M. Bo, E. Biglieri, D. Caviglia
In this paper we present the analog on-chip learning architecture of a gradient descent learning algorithm: the Weight Perturbation learning algorithm. From the circuit implementation point of view our approach is based on current mode and translinear operated circuits. The proposed architecture is very efficient in terms of speed, size, precision and power consumption; moreover it exhibits also high scalability and modularity.
{"title":"An analog on-chip learning circuit architecture of the weight perturbation algorithm","authors":"F. Diotalevi, M. Valle, G. M. Bo, E. Biglieri, D. Caviglia","doi":"10.1109/ISCAS.2000.857120","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.857120","url":null,"abstract":"In this paper we present the analog on-chip learning architecture of a gradient descent learning algorithm: the Weight Perturbation learning algorithm. From the circuit implementation point of view our approach is based on current mode and translinear operated circuits. The proposed architecture is very efficient in terms of speed, size, precision and power consumption; moreover it exhibits also high scalability and modularity.","PeriodicalId":6422,"journal":{"name":"2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86569793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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