Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573530
Jian Zhao, Xi Wang, Yang Zhao, G. Xia, A. Qiu, Yan Su, Y. Xu
This paper presents a silicon oscillating accelerometer (SOA) with CMOS readout circuit. To reduce the bias instability, a PLL is employed to sustain the oscillation instead of the conventional auto-amplitude-control (AAC) circuit. A sigma-delta frequency-to-digital converter (FDC) is built in the PLL to produce the digital output. The MEMS sensor and readout circuit are fabricated in 80 μm SOI and standard 0.35 μm CMOS process, respectively. The SOA achieves 0.23 μg bias instability and 1.6 μg/Hz1/2 resolution with ±30 g full-scale, which are equivalent to 4-ppb relative instability and 27-ppb/Hz1/2resolution. In addition, it only consumes 2.7 mW under a 1.5 V supply.
{"title":"A 0.23 µg bias instability and 1.6 µg/Hz1/2 resolution silicon oscillating accelerometer with build-in Σ-Δ frequency-to-digital converter","authors":"Jian Zhao, Xi Wang, Yang Zhao, G. Xia, A. Qiu, Yan Su, Y. Xu","doi":"10.1109/VLSIC.2016.7573530","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573530","url":null,"abstract":"This paper presents a silicon oscillating accelerometer (SOA) with CMOS readout circuit. To reduce the bias instability, a PLL is employed to sustain the oscillation instead of the conventional auto-amplitude-control (AAC) circuit. A sigma-delta frequency-to-digital converter (FDC) is built in the PLL to produce the digital output. The MEMS sensor and readout circuit are fabricated in 80 μm SOI and standard 0.35 μm CMOS process, respectively. The SOA achieves 0.23 μg bias instability and 1.6 μg/Hz1/2 resolution with ±30 g full-scale, which are equivalent to 4-ppb relative instability and 27-ppb/Hz1/2resolution. In addition, it only consumes 2.7 mW under a 1.5 V supply.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"12 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73184067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573511
Brent Bohnenstiehl, Aaron Stillmaker, J. Pimentel, Timothy Andreas, Bin Liu, A. Tran, E. Adeagbo, B. Baas
1000 programmable processors and 12 independent memory modules capable of simultaneously servicing both data and instruction requests are integrated onto a 32nm PD-SOI CMOS device. At 1.1 V, processors operate up to an average of 1.78 GHz yielding a maximum total chip computation rate of 1.78 trillion instructions/sec. At 0.84 V, 1000 cores execute 1 trillion instructions/sec while dissipating 13.1 W.
{"title":"A 5.8 pJ/Op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array","authors":"Brent Bohnenstiehl, Aaron Stillmaker, J. Pimentel, Timothy Andreas, Bin Liu, A. Tran, E. Adeagbo, B. Baas","doi":"10.1109/VLSIC.2016.7573511","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573511","url":null,"abstract":"1000 programmable processors and 12 independent memory modules capable of simultaneously servicing both data and instruction requests are integrated onto a 32nm PD-SOI CMOS device. At 1.1 V, processors operate up to an average of 1.78 GHz yielding a maximum total chip computation rate of 1.78 trillion instructions/sec. At 0.84 V, 1000 cores execute 1 trillion instructions/sec while dissipating 13.1 W.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"47 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81352590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573499
Sameet Ramakrishnan, Lucas Calderin, A. Puglielli, E. Alon, A. Niknejad, B. Nikolić
This paper presents an active transmitter (TX) cancellation scheme for FDD that synthesizes a replica of the TX current in shunt with the receiver (RX), virtually shorting out the TX signal for the RX while having minimal impact on TX insertion loss. The prototype in 65nm CMOS demonstrates >50dB cancellation of a +12.6dBm peak 20MHz modulated TX signal. A receiver integrated on the same prototype is able to down-convert the RX signal at 40MHz offset with <;4.3dB noise figure (NF) degradation in the presence of the residual TX.
{"title":"A 65nm CMOS transceiver with integrated active cancellation supporting FDD from 1GHz to 1.8GHz at +12.6dBm TX power leakage","authors":"Sameet Ramakrishnan, Lucas Calderin, A. Puglielli, E. Alon, A. Niknejad, B. Nikolić","doi":"10.1109/VLSIC.2016.7573499","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573499","url":null,"abstract":"This paper presents an active transmitter (TX) cancellation scheme for FDD that synthesizes a replica of the TX current in shunt with the receiver (RX), virtually shorting out the TX signal for the RX while having minimal impact on TX insertion loss. The prototype in 65nm CMOS demonstrates >50dB cancellation of a +12.6dBm peak 20MHz modulated TX signal. A receiver integrated on the same prototype is able to down-convert the RX signal at 40MHz offset with <;4.3dB noise figure (NF) degradation in the presence of the residual TX.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"74 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83498721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573492
Chul Kim, Jiwoong Park, Abraham Akinin, S. Ha, R. Kubendran, Hui Wang, P. Mercier, G. Cauwenberghs
An adaptive buck-boost resonant regulating rectifier (B2R3) with an integrated on-chip coil and low-loss H-Tree power/signal distribution is presented for efficient and robust wireless power transfer (WPT) over a wide range of input and load conditions. The B2R3 integrated on a 9 mm2 chip powers integrated neural interfacing circuits as a load, with a TX-load power conversion efficiency of 2.64 % at 10 mm distance, resulting in a WPT system efficiency FoM of 102.
{"title":"A fully integrated 144 MHz wireless-power-receiver-on-chip with an adaptive buck-boost regulating rectifier and low-loss H-Tree signal distribution","authors":"Chul Kim, Jiwoong Park, Abraham Akinin, S. Ha, R. Kubendran, Hui Wang, P. Mercier, G. Cauwenberghs","doi":"10.1109/VLSIC.2016.7573492","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573492","url":null,"abstract":"An adaptive buck-boost resonant regulating rectifier (B<sup>2</sup>R<sup>3</sup>) with an integrated on-chip coil and low-loss H-Tree power/signal distribution is presented for efficient and robust wireless power transfer (WPT) over a wide range of input and load conditions. The B<sup>2</sup>R<sup>3</sup> integrated on a 9 mm<sup>2</sup> chip powers integrated neural interfacing circuits as a load, with a TX-load power conversion efficiency of 2.64 % at 10 mm distance, resulting in a WPT system efficiency FoM of 102.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"2014 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73459755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573516
J. Nam, Mohsen Hassanpourghadi, Aoyang Zhang, M. Chen
A 12-bit SAR ADC architecture with dual reference shifting and interpolation technique has been proposed and implemented with 8-way time interleaving in 65nm CMOS. The proposed technique converts 4 bits per SAR conversion cycle with reduced overhead, which is a key to achieve both high speed and resolution while maintaining low power consumption. The measured peak SNDR is 72dB and remains above 65.3dB at 1-GHz input frequency at sample rate of 1.6 GS/s. It achieves a record power efficiency of 17.8fJ/conv-step among the recently published high-speed/resolution ADCs.
{"title":"A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS","authors":"J. Nam, Mohsen Hassanpourghadi, Aoyang Zhang, M. Chen","doi":"10.1109/VLSIC.2016.7573516","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573516","url":null,"abstract":"A 12-bit SAR ADC architecture with dual reference shifting and interpolation technique has been proposed and implemented with 8-way time interleaving in 65nm CMOS. The proposed technique converts 4 bits per SAR conversion cycle with reduced overhead, which is a key to achieve both high speed and resolution while maintaining low power consumption. The measured peak SNDR is 72dB and remains above 65.3dB at 1-GHz input frequency at sample rate of 1.6 GS/s. It achieves a record power efficiency of 17.8fJ/conv-step among the recently published high-speed/resolution ADCs.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"117 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77590998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573553
Yiqun Zhang, Kaiyuan Yang, Mehdi Saligane, D. Blaauw, D. Sylvester
An AES hardware accelerator targeting energy efficient, low cost mobile and IoT applications is fabricated in 40nm CMOS. The proposed design eliminates the ShiftRow stage in conventional AES implementations and replaces flip-flops in data and key storage with latches using re-timing, saving 25% area and 69% power. Along with a 2-stage Sbox in native GF(24)2 composite-field computation and glitch reduction techniques, this results in a compact 2228 gate design achieving 446 Gbps/W and 46.2 Mbps throughput at 0.47V.
{"title":"A compact 446 Gbps/W AES accelerator for mobile SoC and IoT in 40nm","authors":"Yiqun Zhang, Kaiyuan Yang, Mehdi Saligane, D. Blaauw, D. Sylvester","doi":"10.1109/VLSIC.2016.7573553","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573553","url":null,"abstract":"An AES hardware accelerator targeting energy efficient, low cost mobile and IoT applications is fabricated in 40nm CMOS. The proposed design eliminates the ShiftRow stage in conventional AES implementations and replaces flip-flops in data and key storage with latches using re-timing, saving 25% area and 69% power. Along with a 2-stage Sbox in native GF(24)2 composite-field computation and glitch reduction techniques, this results in a compact 2228 gate design achieving 446 Gbps/W and 46.2 Mbps throughput at 0.47V.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83530181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573468
Zhewei Jiang, J. P. Cerqueira, Seongjong Kim, Qi Wang, Mingoo Seok
This paper presents algorithm/hardware co-design for real-time unsupervised spike sorting hardware for reducing power and improving sorting accuracy. We devise an algorithm based on Bayesian decision, which enables high accuracy while using noisy and simple time-domain features. Those simple features significantly reduce computation complexity, memory requirement, and thus the required number of cycles per sorting. The latter, coupled with the sparsity of spikes in time, makes the hardware idle for most of time, and thus we employ aggressive power gating and balloon latches to sleep most of the circuits and wake them up only when a spike is detected for maximal power savings. The hardware prototyped in a 65nm achieves higher accuracy at lower power than the existing arts.
{"title":"1.74-µW/ch, 95.3%-accurate spike-sorting hardware based on Bayesian decision","authors":"Zhewei Jiang, J. P. Cerqueira, Seongjong Kim, Qi Wang, Mingoo Seok","doi":"10.1109/VLSIC.2016.7573468","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573468","url":null,"abstract":"This paper presents algorithm/hardware co-design for real-time unsupervised spike sorting hardware for reducing power and improving sorting accuracy. We devise an algorithm based on Bayesian decision, which enables high accuracy while using noisy and simple time-domain features. Those simple features significantly reduce computation complexity, memory requirement, and thus the required number of cycles per sorting. The latter, coupled with the sparsity of spikes in time, makes the hardware idle for most of time, and thus we employ aggressive power gating and balloon latches to sleep most of the circuits and wake them up only when a spike is detected for maximal power savings. The hardware prototyped in a 65nm achieves higher accuracy at lower power than the existing arts.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"23 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90729444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573507
Yang Xu, Spencer Leuenberger, Praveen Kumar Venkatachala, U. Moon
A highly compact low-pass filter (LPF) using self-coupled source follower based biquads is presented. The biquad cell synthesizes a 2nd-order low-pass transfer function in a single branch, using only two capacitors and a source follower with embedded local feedback for excellent linearity. A 4th-order Chebyshev LPF prototype is designed with a cascade of two biquads in 0.18μm CMOS, and occupies an active area of 0.1mm2. A cut-off frequency of 31MHz is measured with a stop-band rejection of 76dB. The prototype filter draws only 0.46mA current from a 1.35V supply, and achieves an in-band IIP3 of +29dBm. The averaged in-band input-referred noise is 22.8nV/√Hz, resulting in a dynamic range of 71dB.
{"title":"A 0.6mW 31MHz 4th-order low-pass filter with +29dBm IIP3 using self-coupled source follower based biquads in 0.18µm CMOS","authors":"Yang Xu, Spencer Leuenberger, Praveen Kumar Venkatachala, U. Moon","doi":"10.1109/VLSIC.2016.7573507","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573507","url":null,"abstract":"A highly compact low-pass filter (LPF) using self-coupled source follower based biquads is presented. The biquad cell synthesizes a 2nd-order low-pass transfer function in a single branch, using only two capacitors and a source follower with embedded local feedback for excellent linearity. A 4th-order Chebyshev LPF prototype is designed with a cascade of two biquads in 0.18μm CMOS, and occupies an active area of 0.1mm2. A cut-off frequency of 31MHz is measured with a stop-band rejection of 76dB. The prototype filter draws only 0.46mA current from a 1.35V supply, and achieves an in-band IIP3 of +29dBm. The averaged in-band input-referred noise is 22.8nV/√Hz, resulting in a dynamic range of 71dB.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"54 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80606552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573547
A. Li, Y. Chao, Xuan Chen, Liang Wu, H. Luong
Utilizing a novel phase-averaging filtering technique capable of wide-band spur-and-phase-noise suppression of up to 20dB, a 1.2-GHz inductor-less fractional-N injection-locked PLL achieves phase noise as low as -146dBc/Hz at 30MHz offset with 2MHz resolution allowing for inductor-less alternatives to LC-based PLLs in wireless applications. The 65nm CMOS prototype improves 10-MHz phase noise from -115 to -135dBc/Hz, injection spurs from -40.5dB to -57dB, and integrated jitter from 3.57ps to 1.48ps while occupying an area of 0.6mm2 and consuming 19.8mW from a 0.85V supply resulting in FoM and FoMJitter of -163dB and -223.6dB respectively.
{"title":"An inductor-less fractional-N injection-locked PLL with a spur-and-phase-noise filtering technique","authors":"A. Li, Y. Chao, Xuan Chen, Liang Wu, H. Luong","doi":"10.1109/VLSIC.2016.7573547","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573547","url":null,"abstract":"Utilizing a novel phase-averaging filtering technique capable of wide-band spur-and-phase-noise suppression of up to 20dB, a 1.2-GHz inductor-less fractional-N injection-locked PLL achieves phase noise as low as -146dBc/Hz at 30MHz offset with 2MHz resolution allowing for inductor-less alternatives to LC-based PLLs in wireless applications. The 65nm CMOS prototype improves 10-MHz phase noise from -115 to -135dBc/Hz, injection spurs from -40.5dB to -57dB, and integrated jitter from 3.57ps to 1.48ps while occupying an area of 0.6mm2 and consuming 19.8mW from a 0.85V supply resulting in FoM and FoMJitter of -163dB and -223.6dB respectively.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"40 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85276600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573513
A. Bhavnagarwala, Imran Iqbal, A. Nguyen, David Ondricek, V. Chandra, R. Aitken
We propose and demonstrate in silicon simple, new circuit solutions using a standard 1-1-2 fin 0.09 um2 6T SRAM commercial bitcell in a 16nm FinFET CMOS process to enable a 400mV active VMIN, 200mV retention VMIN SRAM in a 64Kb CMOS array with 128b/BL. Active VMIN is enabled with a self-triggered feedback on an under-driven BL with faster and more robust signal development on the BL at lower voltages - providing dual read assist, and also a 2X tighter offset voltage distribution when compared to conventional differential voltage sensing. 200mV retention VMIN is enabled by reusing write assist circuit overhead while engaging two key observations: insensitivity of bitcell stability to systematic variations and sensitivity of bitcell data to noise on the power grid in the subthreshold/near threshold region. Average FMAX of 140MHz and 2.8GHz are measured across all chips for VDD at 0.4V and 0.9V respectively.
{"title":"A 400mV active VMIN, 200mV retention VMIN, 2.8 GHz 64Kb SRAM with a 0.09 um2 6T bitcell in a 16nm FinFET CMOS process","authors":"A. Bhavnagarwala, Imran Iqbal, A. Nguyen, David Ondricek, V. Chandra, R. Aitken","doi":"10.1109/VLSIC.2016.7573513","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573513","url":null,"abstract":"We propose and demonstrate in silicon simple, new circuit solutions using a standard 1-1-2 fin 0.09 um2 6T SRAM commercial bitcell in a 16nm FinFET CMOS process to enable a 400mV active VMIN, 200mV retention VMIN SRAM in a 64Kb CMOS array with 128b/BL. Active VMIN is enabled with a self-triggered feedback on an under-driven BL with faster and more robust signal development on the BL at lower voltages - providing dual read assist, and also a 2X tighter offset voltage distribution when compared to conventional differential voltage sensing. 200mV retention VMIN is enabled by reusing write assist circuit overhead while engaging two key observations: insensitivity of bitcell stability to systematic variations and sensitivity of bitcell data to noise on the power grid in the subthreshold/near threshold region. Average FMAX of 140MHz and 2.8GHz are measured across all chips for VDD at 0.4V and 0.9V respectively.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"75 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86302586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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