Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573515
S. C. Song, J. Xu, D. Yang, K. Rim, P. Feng, Jerry Bao, J. Zhu, J. Wang, G. Nallapati, M. Badaroglu, P. Narayanasetti, B. Bucki, J. Fischer, G. Yeap
We propose complete technology-design-system co-optimization method in which power, performance, thermal, area and cost metrics are all simultaneously optimized from transistor to mobile SOC system level. This novel method, Unified Technology Optimization Platform using Integrated Analysis (UTOPIA), incorporates thermally limited performance, wafer process complexity and die area scaling model in addition to author's previous transistor-interconnect optimization method. Thermal model in UTOPIA evaluates/optimizes device and technology parameters not only for peak frequency but also for sustained performance after thermal throttling. Optimum N7 technology is selected using proposed UTOPIA method, showing significant overall gain over N10 technology.
{"title":"Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes","authors":"S. C. Song, J. Xu, D. Yang, K. Rim, P. Feng, Jerry Bao, J. Zhu, J. Wang, G. Nallapati, M. Badaroglu, P. Narayanasetti, B. Bucki, J. Fischer, G. Yeap","doi":"10.1109/VLSIC.2016.7573515","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573515","url":null,"abstract":"We propose complete technology-design-system co-optimization method in which power, performance, thermal, area and cost metrics are all simultaneously optimized from transistor to mobile SOC system level. This novel method, Unified Technology Optimization Platform using Integrated Analysis (UTOPIA), incorporates thermally limited performance, wafer process complexity and die area scaling model in addition to author's previous transistor-interconnect optimization method. Thermal model in UTOPIA evaluates/optimizes device and technology parameters not only for peak frequency but also for sustained performance after thermal throttling. Optimum N7 technology is selected using proposed UTOPIA method, showing significant overall gain over N10 technology.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88144112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573521
Bharath Raghavan, A. Varzaghani, L. Rao, Henry Park, Xiaochen Yang, Z. Huang, Yu Chen, R. Kattamuri, Chunhui Wu, Bo Zhang, Jun Cao, A. Momtaz, N. Kocaman
This paper describes an 8.5-11.5 Gb/s transceiver with a dual path receiver and a voltage-mode transmitter. The RX can operate either in ADC mode for complex loss channels such as optical multimode fiber or in DFE mode for copper-based backplane links. The ADC path implements a 2X interleaved 6-bit rectifying flash ADC using a programmable gain amplifier (PGA) with controlled bandwidth and peaking, comparator pipelining, and super-source follower circuit techniques. The LRM optical sensitivity requirements are met with a > 6 dB margin while achieving an ENOB of 4.59 bits at a 5 GHz input frequency. The TX/RX DFE path achieves copper channel loss compensation of 38 dB with BER <; 10-12 at 11.5 Gb/s consuming 46mW from a 0.9V supply. The TX/RX ADC path consumes 125 mW at 10.3125 Gb/s. The TX/RX occupies 0.56 mm2 in a 28nm standard CMOS process.
{"title":"A 125 mW 8.5–11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS","authors":"Bharath Raghavan, A. Varzaghani, L. Rao, Henry Park, Xiaochen Yang, Z. Huang, Yu Chen, R. Kattamuri, Chunhui Wu, Bo Zhang, Jun Cao, A. Momtaz, N. Kocaman","doi":"10.1109/VLSIC.2016.7573521","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573521","url":null,"abstract":"This paper describes an 8.5-11.5 Gb/s transceiver with a dual path receiver and a voltage-mode transmitter. The RX can operate either in ADC mode for complex loss channels such as optical multimode fiber or in DFE mode for copper-based backplane links. The ADC path implements a 2X interleaved 6-bit rectifying flash ADC using a programmable gain amplifier (PGA) with controlled bandwidth and peaking, comparator pipelining, and super-source follower circuit techniques. The LRM optical sensitivity requirements are met with a > 6 dB margin while achieving an ENOB of 4.59 bits at a 5 GHz input frequency. The TX/RX DFE path achieves copper channel loss compensation of 38 dB with BER <; 10-12 at 11.5 Gb/s consuming 46mW from a 0.9V supply. The TX/RX ADC path consumes 125 mW at 10.3125 Gb/s. The TX/RX occupies 0.56 mm2 in a 28nm standard CMOS process.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"77 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91187219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573466
Ankesh Jain, S. Pavan
We present a wideband single-bit CTΔΣM that uses a 2× time-interleaved quantizer and FIR DAC. Time interleaving reduces power dissipation and regeneration errors of the FIR DAC when compared to a full rate implementation. Fabricated in a low leakage 65nm CMOS, the prototype modulator operates at 6 GS/s and achieves 67.6/76 dB SNDR/DR in a 60 MHz bandwidth while consuming 13.3 mW. The FoM is 56.5 fJ/conv-step.
我们提出了一种宽带单比特CTΔΣM，它使用2倍时间交错量化器和FIR DAC。与全速率实现相比，时间交错减少了FIR DAC的功耗和再生错误。该原型调制器采用低漏65nm CMOS制造，工作速度为6 GS/s，在60 MHz带宽下实现67.6/76 dB SNDR/DR，功耗为13.3 mW。FoM为56.5 fJ/反步。
{"title":"A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback","authors":"Ankesh Jain, S. Pavan","doi":"10.1109/VLSIC.2016.7573466","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573466","url":null,"abstract":"We present a wideband single-bit CTΔΣM that uses a 2× time-interleaved quantizer and FIR DAC. Time interleaving reduces power dissipation and regeneration errors of the FIR DAC when compared to a full rate implementation. Fabricated in a low leakage 65nm CMOS, the prototype modulator operates at 6 GS/s and achieves 67.6/76 dB SNDR/DR in a 60 MHz bandwidth while consuming 13.3 mW. The FoM is 56.5 fJ/conv-step.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"50 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76499554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573512
R. Ranica, N. Planes, V. Huard, O. Weber, D. Noblet, D. Croain, F. Giner, S. Naudet, P. Mergault, S. Ibars, A. Villaret, M. Parra, S. Haendler, M. Quoirin, F. Cacho, C. Julien, F. Terrier, L. Ciampolini, D. Turgis, C. Lecocq, F. Arnaud
Vmin measurements in 28nm FDSOI technology on 128Mb SRAM bitcells from -40°C to 125°C are reported in this paper. Adding the silicon ageing behavior and the process variability, we have developed a complete model and demonstrated end-of-life SRAM Vmin of 0.6V and 0.5V on 20Mb with 0.120μm2 and 0.152μm2 bitcells, respectively. This is the first report of a such extensive SRAM Vmin assessment at the 28nm node. The construction of write limited bitcells, combined with write assist design technique, was found to be the most efficient way to achieve ultra low Vmin in 28nm FDSOI technology. In addition, Vmin retention below 0.4V is demonstrated in 0.120μm2 bitcells, leading to the enablement of ultra-low leakage bitcells with 2pA/cell in retention mode.
{"title":"28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications","authors":"R. Ranica, N. Planes, V. Huard, O. Weber, D. Noblet, D. Croain, F. Giner, S. Naudet, P. Mergault, S. Ibars, A. Villaret, M. Parra, S. Haendler, M. Quoirin, F. Cacho, C. Julien, F. Terrier, L. Ciampolini, D. Turgis, C. Lecocq, F. Arnaud","doi":"10.1109/VLSIC.2016.7573512","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573512","url":null,"abstract":"Vmin measurements in 28nm FDSOI technology on 128Mb SRAM bitcells from -40°C to 125°C are reported in this paper. Adding the silicon ageing behavior and the process variability, we have developed a complete model and demonstrated end-of-life SRAM Vmin of 0.6V and 0.5V on 20Mb with 0.120μm2 and 0.152μm2 bitcells, respectively. This is the first report of a such extensive SRAM Vmin assessment at the 28nm node. The construction of write limited bitcells, combined with write assist design technique, was found to be the most efficient way to achieve ultra low Vmin in 28nm FDSOI technology. In addition, Vmin retention below 0.4V is demonstrated in 0.120μm2 bitcells, leading to the enablement of ultra-low leakage bitcells with 2pA/cell in retention mode.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"142 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74563588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573495
A. Tessarolo
Motor Control may not be as trendy as say IoT, but it cannot be denied that the application areas of late have been much more interesting. The growing popularity of drones, electric vehicles such as the Tesla, mobility vehicles like electric bikes or the allure of hover-boards have seen an explosion of electric motors. But changes are also happening in the more traditional industrial sector of motor and servo drives. The demand for cost and energy efficiency is driving the need for new system topologies and greater integration levels. Devices now have to integrate communications with traditional control. Integrated Safety and Security are now part of the mix. The Motor Control device of today is vastly different then 10+ years ago and the challenges are much greater, requiring a broader set of design skills.
{"title":"Motor Control used to be boring","authors":"A. Tessarolo","doi":"10.1109/VLSIC.2016.7573495","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573495","url":null,"abstract":"Motor Control may not be as trendy as say IoT, but it cannot be denied that the application areas of late have been much more interesting. The growing popularity of drones, electric vehicles such as the Tesla, mobility vehicles like electric bikes or the allure of hover-boards have seen an explosion of electric motors. But changes are also happening in the more traditional industrial sector of motor and servo drives. The demand for cost and energy efficiency is driving the need for new system topologies and greater integration levels. Devices now have to integrate communications with traditional control. Integrated Safety and Security are now part of the mix. The Motor Control device of today is vastly different then 10+ years ago and the challenges are much greater, requiring a broader set of design skills.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90096347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573527
R. Dorrance, D. Markovic
A DSP for sparse-BLAS is realized in 40nm CMOS. Featuring an efficient data stream reordering scheme and an intelligent, CSC-aware memory controller, the DSP achieves a peak energy efficiency of 190 GFLOPS/W at 0.6V, 160MHz, and a peak performance of 4.12 GFLOPS at 1V, 515MHz showing more than 6,600×, 2,700×, 1,100×, and 450× higher energy efficiency than state-of-the-art CPU, GPU, DSP, and FPGA hardware designs, respectively.
{"title":"A 190GFLOPS/W DSP for energy-efficient sparse-BLAS in embedded IoT","authors":"R. Dorrance, D. Markovic","doi":"10.1109/VLSIC.2016.7573527","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573527","url":null,"abstract":"A DSP for sparse-BLAS is realized in 40nm CMOS. Featuring an efficient data stream reordering scheme and an intelligent, CSC-aware memory controller, the DSP achieves a peak energy efficiency of 190 GFLOPS/W at 0.6V, 160MHz, and a peak performance of 4.12 GFLOPS at 1V, 515MHz showing more than 6,600×, 2,700×, 1,100×, and 450× higher energy efficiency than state-of-the-art CPU, GPU, DSP, and FPGA hardware designs, respectively.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"67 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82117444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573498
A. Moscatelli
Smart Metering and Smart Grid applications are booming worldwide, requiring innovative integrated circuit solutions to specifically meet multiple and evolving system requirements in terms of connectivity capabilities, system flexibility, sensing accuracy, security, power consumption, system miniaturization and cost of ownership. This paper introduces novel and future-proof system on chip solutions specifically developed to meet these challenging requirements of modern Smart Grid ecosystems.
{"title":"Innovative system on chip platform for Smart Grids and internet of energy applications","authors":"A. Moscatelli","doi":"10.1109/VLSIC.2016.7573498","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573498","url":null,"abstract":"Smart Metering and Smart Grid applications are booming worldwide, requiring innovative integrated circuit solutions to specifically meet multiple and evolving system requirements in terms of connectivity capabilities, system flexibility, sensing accuracy, security, power consumption, system miniaturization and cost of ownership. This paper introduces novel and future-proof system on chip solutions specifically developed to meet these challenging requirements of modern Smart Grid ecosystems.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"13 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82649841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573537
Ahmed M. A. Ali, H. Dinç, Paritosh Bhoraskar, S. Puckett, Andrew S. Morgan, Ning Zhu, Q. Yu, C. Dillon, Bryce Gray, Jonathan Lanford, Matthew McShea, Ushma Mehta, S. Bardsley, Peter R. Derounian, R. Bunch, Ralph Moore, Gerry Taylor
We describe a 14-bit 2.5GS/s non-interleaved pipelined ADC that relies on correlation-based background calibrations to correct the inter-stage gain, settling (dynamic), kick-back and memory errors. A new technique is employed to inject a large dither signal on the input to dither the non-linear kick-back on the ADC driver, and another large dither signal is injected to dither any residual non-linearity in the pipeline. In order to correct the effect of aging on the comparators, a new background calibration technique is employed to correct the comparator offsets. The ADC is fabricated as a dual in a 28nm CMOS process. An optional interleaved mode is provided, where the two ADCs on chip are time-interleaved to obtain a single 14-bit 5GS/s ADC. Background calibration of offset and gain mismatch and fixed calibration of timing mismatch between the two channels are implemented on chip.
{"title":"A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither","authors":"Ahmed M. A. Ali, H. Dinç, Paritosh Bhoraskar, S. Puckett, Andrew S. Morgan, Ning Zhu, Q. Yu, C. Dillon, Bryce Gray, Jonathan Lanford, Matthew McShea, Ushma Mehta, S. Bardsley, Peter R. Derounian, R. Bunch, Ralph Moore, Gerry Taylor","doi":"10.1109/VLSIC.2016.7573537","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573537","url":null,"abstract":"We describe a 14-bit 2.5GS/s non-interleaved pipelined ADC that relies on correlation-based background calibrations to correct the inter-stage gain, settling (dynamic), kick-back and memory errors. A new technique is employed to inject a large dither signal on the input to dither the non-linear kick-back on the ADC driver, and another large dither signal is injected to dither any residual non-linearity in the pipeline. In order to correct the effect of aging on the comparators, a new background calibration technique is employed to correct the comparator offsets. The ADC is fabricated as a dual in a 28nm CMOS process. An optional interleaved mode is provided, where the two ADCs on chip are time-interleaved to obtain a single 14-bit 5GS/s ADC. Background calibration of offset and gain mismatch and fixed calibration of timing mismatch between the two channels are implemented on chip.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"81 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88917363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573505
A. Kobayashi, Tsukasa Tokutomi, K. Takeuchi
Versatile Triple-Level-Cell (TLC) NAND flash memory control with Read Hot/Cold Migration, Read Voltage Control and Edge Word Line Protection is proposed for data center application SSDs. Measured errors decrease by 85% and measured acceptable read cycles increase by 6.7-times.
{"title":"Versatile TLC NAND flash memory control to reduce read disturb errors by 85% and extend read cycles by 6.7-times of Read-Hot and Cold data for cloud data centers","authors":"A. Kobayashi, Tsukasa Tokutomi, K. Takeuchi","doi":"10.1109/VLSIC.2016.7573505","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573505","url":null,"abstract":"Versatile Triple-Level-Cell (TLC) NAND flash memory control with Read Hot/Cold Migration, Read Voltage Control and Edge Word Line Protection is proposed for data center application SSDs. Measured errors decrease by 85% and measured acceptable read cycles increase by 6.7-times.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"27 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84757564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573509
Fred N. Buhler, Adam E. Mendrela, Yong Lim, Jeffrey Fredenburg, M. Flynn
A 16-channel machine learning digitizing interface embeds Inner-Product calculation within a Delta-Sigma Modulator (IPDSM) array canceling quantization noise and noise shaping the multiplicand. The prototype, with 16 independent IPDSM channels occupies a core area of 0.95mm2 in 65 nm CMOS. Each channel performs up to 100M multiplications/s. The system is demonstrated with a standard machine learning scheme for image recognition. It achieves the same classification accuracy for the MNIST set of hand-written digits as with the same algorithm on floating point DSP.
{"title":"A 16-channel noise-shaping machine learning analog-digital interface","authors":"Fred N. Buhler, Adam E. Mendrela, Yong Lim, Jeffrey Fredenburg, M. Flynn","doi":"10.1109/VLSIC.2016.7573509","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573509","url":null,"abstract":"A 16-channel machine learning digitizing interface embeds Inner-Product calculation within a Delta-Sigma Modulator (IPDSM) array canceling quantization noise and noise shaping the multiplicand. The prototype, with 16 independent IPDSM channels occupies a core area of 0.95mm2 in 65 nm CMOS. Each channel performs up to 100M multiplications/s. The system is demonstrated with a standard machine learning scheme for image recognition. It achieves the same classification accuracy for the MNIST set of hand-written digits as with the same algorithm on floating point DSP.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"103 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91335769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：