Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510652
W. Chung, M. Si, P. Shrestha, J. Campbell, K. Cheung, P. Ye
In this work, ultrafast pulses with pulse widths ranging from 100 ps to seconds were applied on the gate of Ge ferroelectric (FE) nanowire (NW) pFETs with FE Hf0.5Zr0.5O2 (HZO) gate dielectric exhibiting steep subthreshold slope (SS) below 60 mV/dec bi-directionally. With applied gate bias pulses (VG = -1 to -10 V), high-mobility Ge drain current was monitored as a test vehicle to capture the polarization switching of HZO. It was found that HZO could switch its polarization directly by a single pulse with the minimum pulse width of 3.6 ns. The polarization switching triggered by pulse train with pulse width as short as 100 ps was demonstrated for the first time.
{"title":"First Direct Experimental Studies of Hf0.5Zr0.5O2 Ferroelectric Polarization Switching Down to 100-picosecond in Sub-60mV/dec Germanium Ferroelectric Nanowire FETs","authors":"W. Chung, M. Si, P. Shrestha, J. Campbell, K. Cheung, P. Ye","doi":"10.1109/VLSIT.2018.8510652","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510652","url":null,"abstract":"In this work, ultrafast pulses with pulse widths ranging from 100 ps to seconds were applied on the gate of Ge ferroelectric (FE) nanowire (NW) pFETs with FE Hf0.5Zr0.5O2 (HZO) gate dielectric exhibiting steep subthreshold slope (SS) below 60 mV/dec bi-directionally. With applied gate bias pulses (VG = -1 to -10 V), high-mobility Ge drain current was monitored as a test vehicle to capture the polarization switching of HZO. It was found that HZO could switch its polarization directly by a single pulse with the minimum pulse width of 3.6 ns. The polarization switching triggered by pulse train with pulse width as short as 100 ps was demonstrated for the first time.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"59 1","pages":"89-90"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84066426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510651
Rinus Lee, N. Petrov, J. Kassim, M. Gribelyuk, J. Yang, L. Cao, K. Yeap, T. Shen, ATIQAH NAJWA ZAINUDDIN, A. Chandrashekar, S. Ray, E. Ramanathan, A. S. Mahalingam, R. Chaudhuri, J. Mody, D. Damjanovic, Z. Sun, R. Sporer, T. J. Tang, H. Liu, J. Liu, B. Krishnan
Nanosecond laser-induced grain growth in Cu interconnects is demonstrated for the first time using 14nm FinFET technology. We achieved a 35% reduction in Cu interconnect resistance, which delivers a 15% improvement in RC and a gain of 2 – 5% in IDsat. Additionally, reliability was enhanced with an improvement in dielectric VBD and Cu EM performance without impacting the ULK mechanical integrity. Our results demonstrate a path to extending Cu interconnects for performance boost in 14nm FinFETs and beyond.
{"title":"Nanosecond Laser Anneal for BEOL Performance Boost in Advanced FinFETs","authors":"Rinus Lee, N. Petrov, J. Kassim, M. Gribelyuk, J. Yang, L. Cao, K. Yeap, T. Shen, ATIQAH NAJWA ZAINUDDIN, A. Chandrashekar, S. Ray, E. Ramanathan, A. S. Mahalingam, R. Chaudhuri, J. Mody, D. Damjanovic, Z. Sun, R. Sporer, T. J. Tang, H. Liu, J. Liu, B. Krishnan","doi":"10.1109/VLSIT.2018.8510651","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510651","url":null,"abstract":"Nanosecond laser-induced grain growth in Cu interconnects is demonstrated for the first time using 14nm FinFET technology. We achieved a 35% reduction in Cu interconnect resistance, which delivers a 15% improvement in RC and a gain of 2 – 5% in IDsat. Additionally, reliability was enhanced with an improvement in dielectric VBD and Cu EM performance without impacting the ULK mechanical integrity. Our results demonstrate a path to extending Cu interconnects for performance boost in 14nm FinFETs and beyond.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"47 1","pages":"61-62"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75073783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510692
T. Ernst, R. Guillemaud, P. Mailley, J. Polizzi, A. Koenig, S. Boisseau, E. Pauliac-Vaujour, C. Plantier, G. Delapierre, E. Saoutieff, R. Gerbelot-Barillon, E. Strinati, S. Hentz, É. Colinet, O. Thomas, P. Boisseau, P. Jallon
The evolutions of medicine covering genome to exposome (i.e. all types of environmental exposures) [1] opened new paths of development for electronics including low power sensors. Additionally, the frontiers for new generations of sensors between smart-living, environment and health are fading. In this paper, we will give examples based on our developments in emerging autonomous sensors and medical devices, and show how they can be included in our daily life.
{"title":"Sensors and related devices for IoT, medicine and s mart-living","authors":"T. Ernst, R. Guillemaud, P. Mailley, J. Polizzi, A. Koenig, S. Boisseau, E. Pauliac-Vaujour, C. Plantier, G. Delapierre, E. Saoutieff, R. Gerbelot-Barillon, E. Strinati, S. Hentz, É. Colinet, O. Thomas, P. Boisseau, P. Jallon","doi":"10.1109/VLSIT.2018.8510692","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510692","url":null,"abstract":"The evolutions of medicine covering genome to exposome (i.e. all types of environmental exposures) [1] opened new paths of development for electronics including low power sensors. Additionally, the frontiers for new generations of sensors between smart-living, environment and health are fading. In this paper, we will give examples based on our developments in emerging autonomous sensors and medical devices, and show how they can be included in our daily life.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"35-36"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72608704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510674
Jun Yuan, K. Rim, Ying Chen, M. Cai, Youseok Suh, Jihong Choi, Jie Deng, Jerry Bao, Zhimin Song, L. Ge, Hao Wang, Xiao-Yong Wang, Vicki Lin, C. Kuo, Sam Yang, Ashwin Rabindranath, S. Siva, Prasad Bhadri, Sungwon Kim, Kwon Lee, S. Cho, S. Kang, Saechoon Oh, S. Kwon, Xiangdong Chen, P. Pénzes, P. Agashe, W. Miller, P. Chidambaram
We report on Snapdragon™ SDM845 mobile SoC in mass production with a second-generation 10-nm finFET technology. SDM845 exhibits 30–40% CPU/GPU performance gain over SDM835 (first-generation 10-nm finFET process) together with ~10% battery life increase driven by new design features and technology improvements in both transistor performance and uniformity, enabling high performance and low power solution for both mobile and computing/AI applications. Extending the technology scaling further, ~15% logic circuit area scaling over 10 nm has been realized in an 8-nm node with gate and BEOL pitch scaling enabled by quadruple patterning (LE^4). Yield equivalence to 10 nm has been demonstrated in 8-nm IP chips.
{"title":"High Performance Mobile SoC Productization with Second-Generation 10-nm FinFET Technology and Extension to 8-nm Scaling","authors":"Jun Yuan, K. Rim, Ying Chen, M. Cai, Youseok Suh, Jihong Choi, Jie Deng, Jerry Bao, Zhimin Song, L. Ge, Hao Wang, Xiao-Yong Wang, Vicki Lin, C. Kuo, Sam Yang, Ashwin Rabindranath, S. Siva, Prasad Bhadri, Sungwon Kim, Kwon Lee, S. Cho, S. Kang, Saechoon Oh, S. Kwon, Xiangdong Chen, P. Pénzes, P. Agashe, W. Miller, P. Chidambaram","doi":"10.1109/VLSIT.2018.8510674","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510674","url":null,"abstract":"We report on Snapdragon™ SDM845 mobile SoC in mass production with a second-generation 10-nm finFET technology. SDM845 exhibits 30–40% CPU/GPU performance gain over SDM835 (first-generation 10-nm finFET process) together with ~10% battery life increase driven by new design features and technology improvements in both transistor performance and uniformity, enabling high performance and low power solution for both mobile and computing/AI applications. Extending the technology scaling further, ~15% logic circuit area scaling over 10 nm has been realized in an 8-nm node with gate and BEOL pitch scaling enabled by quadruple patterning (LE^4). Yield equivalence to 10 nm has been demonstrated in 8-nm IP chips.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"26 1","pages":"219-220"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76555471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510661
Ying Wu, Wei Wang, S. Masudy‐Panah, Yang Li, Kaizhen Han, L. He, Zheng Zhang, D. Lei, Shengqiang Xu, Yuye Kang, X. Gong, Y. Yeo
Ga and Sn surface-segregated p+-GeSn (Seg. p+-GeSn) was grown by molecular beam epitaxy (MBE) to achieve an average active Ga doping concentration of 3.4×1020 cm−3 and surface Sn composition of more than 8%. This enables the realization of record-low specific contact resistivity ρc down to 4.4×10−10 Ω-cm2. The average ρc extracted from 14 sets of Ti/Seg. p+-GeSn Nano-TLM test structures, a collection of more than 90 devices is 6.5×10−10 Ω-cm2. This is also the lowest ρc for non-laser-annealed contacts. Ti contacts to p+-GeSn films with and without Ga and Sn surface segregation were fabricated. It is shown that the segregation of Ga and Sn at the Ti/p+-GeSn interface leads to 50% reduction in ρc as compared with a sample without segregation.
{"title":"Metal/P-type GeSn Contacts with Specific Contact Resistivity down to 4.4×10−10 Ω-cm2","authors":"Ying Wu, Wei Wang, S. Masudy‐Panah, Yang Li, Kaizhen Han, L. He, Zheng Zhang, D. Lei, Shengqiang Xu, Yuye Kang, X. Gong, Y. Yeo","doi":"10.1109/VLSIT.2018.8510661","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510661","url":null,"abstract":"Ga and Sn surface-segregated p<sup>+</sup>-GeSn (Seg. p<sup>+</sup>-GeSn) was grown by molecular beam epitaxy (MBE) to achieve an average active Ga doping concentration of 3.4×10<sup>20</sup> cm<sup>−3</sup> and surface Sn composition of more than 8%. This enables the realization of record-low specific contact resistivity ρ<inf>c</inf> down to 4.4×10<sup>−10</sup> Ω-cm<sup>2</sup>. The average ρ<inf>c</inf> extracted from 14 sets of Ti/Seg. p<sup>+</sup>-GeSn Nano-TLM test structures, a collection of more than 90 devices is 6.5×10<sup>−10</sup> Ω-cm<sup>2</sup>. This is also the lowest ρ<inf>c</inf> for non-laser-annealed contacts. Ti contacts to p<sup>+</sup>-GeSn films with and without Ga and Sn surface segregation were fabricated. It is shown that the segregation of Ga and Sn at the Ti/p<sup>+</sup>-GeSn interface leads to 50% reduction in ρ<inf>c</inf> as compared with a sample without segregation.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"87 1","pages":"77-78"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84116278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510640
C. Fan, Chun‐Hu Cheng, C. Tu, Chien Liu, Wan-Hsin Chen, Tun-Jen Chang, Chun-Yen Chang
For the first time, we successfully demonstrated that the 4-nm-thick dopant-free HfO2 NCFETs using gate strain can implement an energy-efficient switch of a low gate overdrive voltage and a nearly hysteresis-free sub-40 mV/dec swing. The gate strain favorably rearranges oxygen vacancies and boosts orthorhombic phase transition. Furthermore, the dopant-free HfO2 NCFET can be further improved by in-situ nitridation process. The 4-nm-thick nitrided HfO2 NCFETs achieve a steep symmetric sub-35 mV/dec switch, a sustained sub-40 mV/dec SS distribution, and excellent stress immunity during NC switch. The high-scalability and dopant-free NCFET shows the great potential for the application of future highly-scaled 3D CMOS technology.
{"title":"Achieving High-Scalability Negative Capacitance FETs with Uniform Sub-35 mV/dec Switch Using Dopant-Free Hafnium Oxide and Gate Strain","authors":"C. Fan, Chun‐Hu Cheng, C. Tu, Chien Liu, Wan-Hsin Chen, Tun-Jen Chang, Chun-Yen Chang","doi":"10.1109/VLSIT.2018.8510640","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510640","url":null,"abstract":"For the first time, we successfully demonstrated that the 4-nm-thick dopant-free HfO2 NCFETs using gate strain can implement an energy-efficient switch of a low gate overdrive voltage and a nearly hysteresis-free sub-40 mV/dec swing. The gate strain favorably rearranges oxygen vacancies and boosts orthorhombic phase transition. Furthermore, the dopant-free HfO2 NCFET can be further improved by in-situ nitridation process. The 4-nm-thick nitrided HfO2 NCFETs achieve a steep symmetric sub-35 mV/dec switch, a sustained sub-40 mV/dec SS distribution, and excellent stress immunity during NC switch. The high-scalability and dopant-free NCFET shows the great potential for the application of future highly-scaled 3D CMOS technology.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"64 1","pages":"139-140"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80188924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510704
Daeyeon Kim, J. Wiedemer, P. Kolar, Ayushi Shrivastava, Jinal Shah, Satyanand Nalam, Gwanghyeon Baek, Xiaofei Wang, Z. Guo, E. Karl
Exceptionally low minimum operating voltage (VMIN) SRAM arrays have been demonstrated on 22nm FinFET low power technology (22FFL) [1]. By optimizing an undoped SRAM transistor and applying industry standard write assist techniques, 16Mb array of 0.087μm2 high-density bitcell (HDC) and 32Mb array of 0.107μm2 high-current bitcell (HCC) achieve the 95th percentile VMIN of 505mV and 450mV respectively across a temperature range of -10°C to 95°C. A self-induced collapse (SIC) write assist integrated into the 6-T HDC SRAM bitcell array enables 110mV VMIN reduction relative to an unassisted array at the 95th percentile with negligible power overhead.
{"title":"Sub-550mV SRAM Design in 22nm FinFET Low Power (22FFL) Technology with Self-Induced Collapse Write Assist","authors":"Daeyeon Kim, J. Wiedemer, P. Kolar, Ayushi Shrivastava, Jinal Shah, Satyanand Nalam, Gwanghyeon Baek, Xiaofei Wang, Z. Guo, E. Karl","doi":"10.1109/VLSIT.2018.8510704","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510704","url":null,"abstract":"Exceptionally low minimum operating voltage (V<inf>MIN</inf>) SRAM arrays have been demonstrated on 22nm FinFET low power technology (22FFL) [1]. By optimizing an undoped SRAM transistor and applying industry standard write assist techniques, 16Mb array of 0.087μm<sup>2</sup> high-density bitcell (HDC) and 32Mb array of 0.107μm<sup>2</sup> high-current bitcell (HCC) achieve the 95<sup>th</sup> percentile V<inf>MIN</inf> of 505mV and 450mV respectively across a temperature range of -10°C to 95°C. A self-induced collapse (SIC) write assist integrated into the 6-T HDC SRAM bitcell array enables 110mV V<inf>MIN</inf> reduction relative to an unassisted array at the 95<sup>th</sup> percentile with negligible power overhead.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"2 1","pages":"151-152"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87284784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Stimulating specific brain regions has been found useful for treating neural disorders, such as the Parkinson’s disease, epilepsy, depression, etc. However, how electrical stimulation modulates neural activities remains not fully understood. As animal models provide the advantage of recording and stimulating different disease-related regions simultaneously, this paper introduces the latest development of a multisite, closed-loop-controlled microsystem for investigating novel treatments on neural degenerative diseases with freely-moving rats. The algorithms for recognizing pathological neural activities automatically are also developed and realized in hardware, so as to control the stimulation in a closed loop and in real time. The pilot studies on the efficacy of treating the Parkinson’s disease with closed-loop-controlled stimulation will be presented and discussed. Finally, the feasibility of modelling and probing how neural dynamics and connectivity are modulated by stimulation will be an important topic for future research.
{"title":"Development of a Multisite, Closed-loop Neuromodulator for the Theranosis of Neural Degenerative Diseases","authors":"Hsin Chen, Yen-Chung Chang, S. Yeh, C. Hsieh, K. Tang, Ping-Hsuan Hsieh, Y. Liao, Ramesh Perumel, Ji-Feng Chuang, Ching-Chih Chang, Yu-Chieh Chen, Shih-Hsin Chen, Sung-En Hsieh, Yen-Peng Chen, Ye-Ting Chen, Tzu-Hao Liu, Yu-Ming Chang, Wei-Chih Lai, Chuan-Yi Wu, Yu-Hsin Chen, Ying Weng","doi":"10.1109/VLSIT.2018.8510647","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510647","url":null,"abstract":"Stimulating specific brain regions has been found useful for treating neural disorders, such as the Parkinson’s disease, epilepsy, depression, etc. However, how electrical stimulation modulates neural activities remains not fully understood. As animal models provide the advantage of recording and stimulating different disease-related regions simultaneously, this paper introduces the latest development of a multisite, closed-loop-controlled microsystem for investigating novel treatments on neural degenerative diseases with freely-moving rats. The algorithms for recognizing pathological neural activities automatically are also developed and realized in hardware, so as to control the stimulation in a closed loop and in real time. The pilot studies on the efficacy of treating the Parkinson’s disease with closed-loop-controlled stimulation will be presented and discussed. Finally, the feasibility of modelling and probing how neural dynamics and connectivity are modulated by stimulation will be an important topic for future research.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"13 1","pages":"37-38"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79625353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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