Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510686
G. Ayele, S. Monfray, S. Ecoffey, F. Boeuf, R. Bon, J. Cloarec, D. Drouin, A. Souifi
The industrialization of ion-sensitive field-effect transistors (ISFETs) has been constrained due mainly to the limited sensitivity, and inclusion of bulky reference electrode. With this paper, we report an ultrahigh-sensitive and CMOS compatible ISFET in which the need for the reference electrode is eliminated. Based on an industrial UTBB FDSOI device in BEOL, we obtained an ultrahigh sensitivity of 730 mV/pH which is 12-times higher than the Nernst limit. Integrating the sensing area and the control gate in the BEOL of UTBB FDSOI transistors with a capacitive divider circuit, and using the back biasing feature of such devices, we could eliminate the necessity of the reference electrode making our sensor highly scalable and ideal for the IoT. This is the first demonstration of an integrated pH sensor in the BEOL of FDSOI platform. The measurements on fabricated sensors have also been validated by modeling and simulation.
{"title":"Ultrahigh-Sensitive and CMOS Compatible ISFET Developed in BEOL of Industrial UTBB FDSOI","authors":"G. Ayele, S. Monfray, S. Ecoffey, F. Boeuf, R. Bon, J. Cloarec, D. Drouin, A. Souifi","doi":"10.1109/VLSIT.2018.8510686","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510686","url":null,"abstract":"The industrialization of ion-sensitive field-effect transistors (ISFETs) has been constrained due mainly to the limited sensitivity, and inclusion of bulky reference electrode. With this paper, we report an ultrahigh-sensitive and CMOS compatible ISFET in which the need for the reference electrode is eliminated. Based on an industrial UTBB FDSOI device in BEOL, we obtained an ultrahigh sensitivity of 730 mV/pH which is 12-times higher than the Nernst limit. Integrating the sensing area and the control gate in the BEOL of UTBB FDSOI transistors with a capacitive divider circuit, and using the back biasing feature of such devices, we could eliminate the necessity of the reference electrode making our sensor highly scalable and ideal for the IoT. This is the first demonstration of an integrated pH sensor in the BEOL of FDSOI platform. The measurements on fabricated sensors have also been validated by modeling and simulation.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"66 1","pages":"97-98"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80369764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510670
Y. Ban, Xuelian Zhu, J. Petykiewicz, J. Zeng
This paper presents improvements in performance, power, and area (PPA) obtained by optimizing the gear ratio (GR) between the Gate and vertical metal layer pitches in standard cells in sub-10nm node CMOS SoC designs. Changing the GR from 1:1 to 3:2 leads to better pin accessibility, routability, and higher cell density. This in turn enables a gate pitch relaxation and associated improvements in cell delay. Implementation of 3:2 GR ultra-dense cells in an SoC CPU block results in up to 17% higher performance, 4% smaller logic size, and 8% lower dynamic power at typical PVT conditions.
{"title":"Improving Performance, Power, and Area by Optimizing Gear Ratio of Gate-Metal Pitches in Sub-10nm Node CMOS Designs","authors":"Y. Ban, Xuelian Zhu, J. Petykiewicz, J. Zeng","doi":"10.1109/VLSIT.2018.8510670","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510670","url":null,"abstract":"This paper presents improvements in performance, power, and area (PPA) obtained by optimizing the gear ratio (GR) between the Gate and vertical metal layer pitches in standard cells in sub-10nm node CMOS SoC designs. Changing the GR from 1:1 to 3:2 leads to better pin accessibility, routability, and higher cell density. This in turn enables a gate pitch relaxation and associated improvements in cell delay. Implementation of 3:2 GR ultra-dense cells in an SoC CPU block results in up to 17% higher performance, 4% smaller logic size, and 8% lower dynamic power at typical PVT conditions.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"77 1","pages":"137-138"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90442182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510654
G. Hellings, H. Mertens, A. Subirats, E. Simoen, T. Schram, L. Ragnarsson, Marko Simicic, S.-H. Chen, B. Parvais, D. Boudier, B. Crețu, J. Machillot, V. Peña, S. Sun, N. Yoshida, N. Kim, A. Mocuta, D. Linten, N. Horiguchi
This work presents Si/SiGe superlattice finFETs (FF) for 1.8V/2.5V I/O applications in vertically-stacked Gate-All-Around horizontal nanowire technology (hNW) technology. Superlattice FF have a higher ION than I/O hNW reference devices and can be more easily integrated into a GAA hNW technology than Si I/O FF. These novel I/O FET structures exhibit competitive analog performance and are superior as ESD protection devices.
{"title":"Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology","authors":"G. Hellings, H. Mertens, A. Subirats, E. Simoen, T. Schram, L. Ragnarsson, Marko Simicic, S.-H. Chen, B. Parvais, D. Boudier, B. Crețu, J. Machillot, V. Peña, S. Sun, N. Yoshida, N. Kim, A. Mocuta, D. Linten, N. Horiguchi","doi":"10.1109/VLSIT.2018.8510654","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510654","url":null,"abstract":"This work presents Si/SiGe superlattice finFETs (FF) for 1.8V/2.5V I/O applications in vertically-stacked Gate-All-Around horizontal nanowire technology (hNW) technology. Superlattice FF have a higher ION than I/O hNW reference devices and can be more easily integrated into a GAA hNW technology than Si I/O FF. These novel I/O FET structures exhibit competitive analog performance and are superior as ESD protection devices.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"17 1","pages":"85-86"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87198422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510698
H. Sumi, H. Takehara, Shunsuke Miyazaki, Daiki Shirahige, K. Sasagawa, T. Tokuda, Yoshihiro Watanabe, N. Kishi, J. Ohta, M. Ishikawa
This paper presents a near-infrared (NIR) multi-spectral imaging system, which can be applied to a CMOS image sensor with fine pixels. Using the multi-spectral technology, NIR1: near 800 nm, NIR2: 870 nm, and NIR3: 940 nm in the NIR wavelength were acquired for a target image. Using this image sensor and imaging system and with the application of interpolation and color correction processing, a color image is reproduced by only multi-NIR signal without visible light (0 lx). We also developed a next-generation fundus camera, which employed this multi-spectral imaging system with a multi-NIR LED illuminator. This multi-NIR LED illumination system, which was also developed, is designed to emit light with high efficiency despite its size of 2.3 mm square in size. We applied this NIR multi-spectral camera module with the multi-NIR LED illuminator to the next-generation fundus camera; the retinal pigment appears progressively more transparent, revealing the underlying choroid.
{"title":"Next-generation Fundus Camera with Full Color Image Acquisition in 0-lx Visible Light by 1.12-micron Square Pixel, 4K, 30-fps BSI CMOS Image Sensor with Advanced NIR Multi-spectral Imaging System","authors":"H. Sumi, H. Takehara, Shunsuke Miyazaki, Daiki Shirahige, K. Sasagawa, T. Tokuda, Yoshihiro Watanabe, N. Kishi, J. Ohta, M. Ishikawa","doi":"10.1109/VLSIT.2018.8510698","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510698","url":null,"abstract":"This paper presents a near-infrared (NIR) multi-spectral imaging system, which can be applied to a CMOS image sensor with fine pixels. Using the multi-spectral technology, NIR1: near 800 nm, NIR2: 870 nm, and NIR3: 940 nm in the NIR wavelength were acquired for a target image. Using this image sensor and imaging system and with the application of interpolation and color correction processing, a color image is reproduced by only multi-NIR signal without visible light (0 lx). We also developed a next-generation fundus camera, which employed this multi-spectral imaging system with a multi-NIR LED illuminator. This multi-NIR LED illumination system, which was also developed, is designed to emit light with high efficiency despite its size of 2.3 mm square in size. We applied this NIR multi-spectral camera module with the multi-NIR LED illuminator to the next-generation fundus camera; the retinal pigment appears progressively more transparent, revealing the underlying choroid.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"275 1","pages":"163-164"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84555025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510623
Yong Kyu Lee, Yoonjong Song, Joochan Kim, Sechung Oh, B. Bae, SangHumn Lee, Junghyuk Lee, U. Pi, B. Seo, H. Jung, Kilho Lee, Hyunchul Shin, H. Jung, Mark Pyo, A. Antonyan, Daesop Lee, Sohee Hwang, D. Jang, Yongsung Ji, Seungbae Lee, Jung-Pil Lim, K. Koh, K. Hwang, H. Hong, K. Park, G. Jeong, J. Yoon, E. Jung
We demonstrate, for the first time, 28-nm embedded STT-MRAM operating at full industrial temperature range (−40~125°C) with >1E+6 endurance and >10 year retention for high speed MCU/IoT application. Robust cell operation is also demonstrated after solder reflow (260°C, 90 second) and during external magnetic disturbance (550-Oe under writing). It is built on 28-nm FDSOI technology in modular format for IP reuse and has great potential to serve wide variety of applications such as IoT, and high performance MCU.
{"title":"Embedded STT-MRAM in 28-nm FDSOI Logic Process for Industrial MCU/IoT Application","authors":"Yong Kyu Lee, Yoonjong Song, Joochan Kim, Sechung Oh, B. Bae, SangHumn Lee, Junghyuk Lee, U. Pi, B. Seo, H. Jung, Kilho Lee, Hyunchul Shin, H. Jung, Mark Pyo, A. Antonyan, Daesop Lee, Sohee Hwang, D. Jang, Yongsung Ji, Seungbae Lee, Jung-Pil Lim, K. Koh, K. Hwang, H. Hong, K. Park, G. Jeong, J. Yoon, E. Jung","doi":"10.1109/VLSIT.2018.8510623","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510623","url":null,"abstract":"We demonstrate, for the first time, 28-nm embedded STT-MRAM operating at full industrial temperature range (−40~125°C) with >1E+6 endurance and >10 year retention for high speed MCU/IoT application. Robust cell operation is also demonstrated after solder reflow (260°C, 90 second) and during external magnetic disturbance (550-Oe under writing). It is built on 28-nm FDSOI technology in modular format for IP reuse and has great potential to serve wide variety of applications such as IoT, and high performance MCU.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"10 1","pages":"181-182"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81406589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510702
Yida Li, A. Alian, Li Huang, K. Ang, D. Lin, D. Mocuta, N. Collaert, A. Thean
We demonstrate an InGaAs nanomembrane field-effect phototransistor with wide-band spectral response tunability, from the visible to near-infrared light. The ultra-thin InGaAs channel (15nm) device, enabled by epitaxial lift-off of InGaAs-on-InP MOSHEMT, is integrated with a fully exposed channel for photosensitivity enhancement. The photocurrent is tunable >5 orders for a gate bias range of 6 V. On-state photo-responsivities of 380 A/W to 15 A/W for 660 nm to 1877 nm light is measured, >2× more sensitive than existing silicon and III-V photodetectors [1]–[3]. The device shows no performance degradation when flexed down to 10-cm radius, showing suitability for conformal surface sensor applications.
{"title":"A Near- & Short-Wave IR Tunable InGaAs Nanomembrane PhotoFET on Flexible Substrate for Lightweight and Wide-Angle Imaging Applications","authors":"Yida Li, A. Alian, Li Huang, K. Ang, D. Lin, D. Mocuta, N. Collaert, A. Thean","doi":"10.1109/VLSIT.2018.8510702","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510702","url":null,"abstract":"We demonstrate an InGaAs nanomembrane field-effect phototransistor with wide-band spectral response tunability, from the visible to near-infrared light. The ultra-thin InGaAs channel (15nm) device, enabled by epitaxial lift-off of InGaAs-on-InP MOSHEMT, is integrated with a fully exposed channel for photosensitivity enhancement. The photocurrent is tunable >5 orders for a gate bias range of 6 V. On-state photo-responsivities of 380 A/W to 15 A/W for 660 nm to 1877 nm light is measured, >2× more sensitive than existing silicon and III-V photodetectors [1]–[3]. The device shows no performance degradation when flexed down to 10-cm radius, showing suitability for conformal surface sensor applications.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"12 1","pages":"159-160"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85611469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510677
P. Coudrain, J. Colonna, L. Collin, R. Prieto, L. Fréchette, J. Barrau, G. Savelli, P. Vivet, Q. Struss, J. Widiez, K. Vladimirova, K. Triantopoulos, H. Beckrich-Ros, M. Vilarrubí, G. Laguna, H. Azarkish, M. Shirazi, J. Michailos
This paper describes evolutions of circuit environment to face an ever-increasing thermal challenge, from early design stage down to the final package. To illustrate this critical concern we give a portrayal of innovative technologies and concepts studied for efficient thermal management from low to high power electronics, with an emphasis on hot spot management.
{"title":"Shaping circuit environment to face the thermal challenge Innovative technologies from low to high power electronics","authors":"P. Coudrain, J. Colonna, L. Collin, R. Prieto, L. Fréchette, J. Barrau, G. Savelli, P. Vivet, Q. Struss, J. Widiez, K. Vladimirova, K. Triantopoulos, H. Beckrich-Ros, M. Vilarrubí, G. Laguna, H. Azarkish, M. Shirazi, J. Michailos","doi":"10.1109/VLSIT.2018.8510677","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510677","url":null,"abstract":"This paper describes evolutions of circuit environment to face an ever-increasing thermal challenge, from early design stage down to the final package. To illustrate this critical concern we give a portrayal of innovative technologies and concepts studied for efficient thermal management from low to high power electronics, with an emphasis on hot spot management.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"65 1","pages":"15-16"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74730110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510626
D. Kwon, Y. Liao, Yen-Kai Lin, J. Duarte, K. Chatterjee, A. Tan, A. Yadav, C. Hu, Z. Krivokapic, S. Salahuddin
We report on the measurement of a 101-stage ring oscillator (RO) consisting of state-of-the-art 14 nm FinFET devices with a ferroelectric gate layer that exhibits negative capacitance. We show that the gate stage delay as a function of applied voltage can be directly modeled from DC characteristics of the individual NC-nFET and NC-pFET devices that constitute the RO, thereby demonstrating that there is no slowdown of the NC effect at the highest speed tested - per-stage delay as small as 7.2 ps.
{"title":"Response Speed of Negative Capacitance FinFETs","authors":"D. Kwon, Y. Liao, Yen-Kai Lin, J. Duarte, K. Chatterjee, A. Tan, A. Yadav, C. Hu, Z. Krivokapic, S. Salahuddin","doi":"10.1109/VLSIT.2018.8510626","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510626","url":null,"abstract":"We report on the measurement of a 101-stage ring oscillator (RO) consisting of state-of-the-art 14 nm FinFET devices with a ferroelectric gate layer that exhibits negative capacitance. We show that the gate stage delay as a function of applied voltage can be directly modeled from DC characteristics of the individual NC-nFET and NC-pFET devices that constitute the RO, thereby demonstrating that there is no slowdown of the NC effect at the highest speed tested - per-stage delay as small as 7.2 ps.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"16 1","pages":"49-50"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77101622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510673
H. Rhee, Ilryong Kim, Jaehun Jeong, Nakjin Son, Heebum Hong, Sungil Cho, Yongsoon Park, Dongwoo Kim, Yunki Choi, Jeonghoon Ahn, S. Kang, K. Yeo, Jungtae Kim, Euncheol Lee, J. Youn, J. Yoon
8LPP logic platform technology supports mobile and high-performance and lower power application especially for mobile, artificial intelligence (AI), and cryptocurrency devices. 8LPP is employing the evolutionary generation of bulk FinFET FEOL and 44nm EUV-less multi-patterning BEOL process, resulting in 7% power reduction and ~15% area scaling compared with the previous 10LPP. The cost-effective high volume manufacturing is achieved with the minimum additional critical layers and the comparable process steps over the current high volume 10nm production.
{"title":"8LPP Logic Platform Technology for Cost-Effective High Volume Manufacturing","authors":"H. Rhee, Ilryong Kim, Jaehun Jeong, Nakjin Son, Heebum Hong, Sungil Cho, Yongsoon Park, Dongwoo Kim, Yunki Choi, Jeonghoon Ahn, S. Kang, K. Yeo, Jungtae Kim, Euncheol Lee, J. Youn, J. Yoon","doi":"10.1109/VLSIT.2018.8510673","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510673","url":null,"abstract":"8LPP logic platform technology supports mobile and high-performance and lower power application especially for mobile, artificial intelligence (AI), and cryptocurrency devices. 8LPP is employing the evolutionary generation of bulk FinFET FEOL and 44nm EUV-less multi-patterning BEOL process, resulting in 7% power reduction and ~15% area scaling compared with the previous 10LPP. The cost-effective high volume manufacturing is achieved with the minimum additional critical layers and the comparable process steps over the current high volume 10nm production.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"21 1","pages":"217-218"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77190581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510706
J. L. Kuo, H. W. Chen, E. Hsieh, S. Chung, T. P. Chen, S. A. Huang, J. Chen, O. Cheng
A pure logic 14nm FinFET with capabilities of linearly tunable Vth and excellent retention has been implemented as synapses in neuromorphic system. For the first time, a Field Programmable Synapse Array (FPSA) has been adopted to replace conventional R-based memory Synapse Array (RSA). Thanks to the wide range of Vt-tuning ability, 200X on/off ratio, and the ultra-small variability, 12%, results showed that the training power and SN ratio of FPSA are 10 times and 50 times smaller than those of the RSA, respectively. Two applications were demonstrated on FPSA array for one-shot learning applications. First, FPSA is used to detect handwritten digits of MNIST dataset. "Learned it by once" can be achieved in this task. Furthermore, FPSA has been applied to recognize goldfish in Cifar 100 dataset after learned the other 4 fish species. With the assistance from one-shot learning, results show the machine learned it faster and better on EDGE. This demonstrates the feasibility of FPSA for low-power and cost-effective synapse-based one-shot learning applications in the AIoT era.
{"title":"An Energy Efficient FinFET-based Field Programmable Synapse Array (FPSA) Feasible for One-shot Learning on EDGE AI","authors":"J. L. Kuo, H. W. Chen, E. Hsieh, S. Chung, T. P. Chen, S. A. Huang, J. Chen, O. Cheng","doi":"10.1109/VLSIT.2018.8510706","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510706","url":null,"abstract":"A pure logic 14nm FinFET with capabilities of linearly tunable Vth and excellent retention has been implemented as synapses in neuromorphic system. For the first time, a Field Programmable Synapse Array (FPSA) has been adopted to replace conventional R-based memory Synapse Array (RSA). Thanks to the wide range of Vt-tuning ability, 200X on/off ratio, and the ultra-small variability, 12%, results showed that the training power and SN ratio of FPSA are 10 times and 50 times smaller than those of the RSA, respectively. Two applications were demonstrated on FPSA array for one-shot learning applications. First, FPSA is used to detect handwritten digits of MNIST dataset. \"Learned it by once\" can be achieved in this task. Furthermore, FPSA has been applied to recognize goldfish in Cifar 100 dataset after learned the other 4 fish species. With the assistance from one-shot learning, results show the machine learned it faster and better on EDGE. This demonstrates the feasibility of FPSA for low-power and cost-effective synapse-based one-shot learning applications in the AIoT era.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"69 1-3 1","pages":"29-30"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77934584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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