Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510706
J. L. Kuo, H. W. Chen, E. Hsieh, S. Chung, T. P. Chen, S. A. Huang, J. Chen, O. Cheng
A pure logic 14nm FinFET with capabilities of linearly tunable Vth and excellent retention has been implemented as synapses in neuromorphic system. For the first time, a Field Programmable Synapse Array (FPSA) has been adopted to replace conventional R-based memory Synapse Array (RSA). Thanks to the wide range of Vt-tuning ability, 200X on/off ratio, and the ultra-small variability, 12%, results showed that the training power and SN ratio of FPSA are 10 times and 50 times smaller than those of the RSA, respectively. Two applications were demonstrated on FPSA array for one-shot learning applications. First, FPSA is used to detect handwritten digits of MNIST dataset. "Learned it by once" can be achieved in this task. Furthermore, FPSA has been applied to recognize goldfish in Cifar 100 dataset after learned the other 4 fish species. With the assistance from one-shot learning, results show the machine learned it faster and better on EDGE. This demonstrates the feasibility of FPSA for low-power and cost-effective synapse-based one-shot learning applications in the AIoT era.
{"title":"An Energy Efficient FinFET-based Field Programmable Synapse Array (FPSA) Feasible for One-shot Learning on EDGE AI","authors":"J. L. Kuo, H. W. Chen, E. Hsieh, S. Chung, T. P. Chen, S. A. Huang, J. Chen, O. Cheng","doi":"10.1109/VLSIT.2018.8510706","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510706","url":null,"abstract":"A pure logic 14nm FinFET with capabilities of linearly tunable Vth and excellent retention has been implemented as synapses in neuromorphic system. For the first time, a Field Programmable Synapse Array (FPSA) has been adopted to replace conventional R-based memory Synapse Array (RSA). Thanks to the wide range of Vt-tuning ability, 200X on/off ratio, and the ultra-small variability, 12%, results showed that the training power and SN ratio of FPSA are 10 times and 50 times smaller than those of the RSA, respectively. Two applications were demonstrated on FPSA array for one-shot learning applications. First, FPSA is used to detect handwritten digits of MNIST dataset. \"Learned it by once\" can be achieved in this task. Furthermore, FPSA has been applied to recognize goldfish in Cifar 100 dataset after learned the other 4 fish species. With the assistance from one-shot learning, results show the machine learned it faster and better on EDGE. This demonstrates the feasibility of FPSA for low-power and cost-effective synapse-based one-shot learning applications in the AIoT era.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"69 1-3 1","pages":"29-30"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77934584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510671
James Brown, R. Gao, Z. Ji, Jiezhi Chen, Jixuan Wu, Jianfu Zhang, Bo Zhou, Q. Shi, Jacob Crowford, Weidong Zhang
A novel True Random Number Generator (TRNG), using random telegraph noise (RTN) as the entropy source, is proposed to address speed, design area, power and cost simultaneously. For the first time, the proposed design breaks the inherent speed limitation and generates true random numbers up to 3Mbps with ultra-low power. This is over 10 times faster than the state-of-the-art RTN-TRNG [6]. Moreover, the new design does not require selection of devices and thus avoids the use of large transistor array and laborious post-selection process. This reduces the circuit area and the cost. The proposed TRNG has been successfully validated on three different processes and they all passed the National Institute of Standards and Technology (NIST) tests, making it a suitable candidate for future cryptographically secured applications in the internet of things (IoT).
{"title":"A low-power and high-speed True Random Number Generator using generated RTN","authors":"James Brown, R. Gao, Z. Ji, Jiezhi Chen, Jixuan Wu, Jianfu Zhang, Bo Zhou, Q. Shi, Jacob Crowford, Weidong Zhang","doi":"10.1109/VLSIT.2018.8510671","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510671","url":null,"abstract":"A novel True Random Number Generator (TRNG), using random telegraph noise (RTN) as the entropy source, is proposed to address speed, design area, power and cost simultaneously. For the first time, the proposed design breaks the inherent speed limitation and generates true random numbers up to 3Mbps with ultra-low power. This is over 10 times faster than the state-of-the-art RTN-TRNG [6]. Moreover, the new design does not require selection of devices and thus avoids the use of large transistor array and laborious post-selection process. This reduces the circuit area and the cost. The proposed TRNG has been successfully validated on three different processes and they all passed the National Institute of Standards and Technology (NIST) tests, making it a suitable candidate for future cryptographically secured applications in the internet of things (IoT).","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"26 1","pages":"95-96"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82047693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510655
K. Lee, K. Yamane, S. Noh, V. B. Naik, H. Yang, S. Jang, J. Kwon, B. Behin-Aein, R. Chao, J. H. Lim, K. S., K. W. Gan, D. Zeng, N. Thiyagarajah, L. C. Goh, B. Liu, E. Toh, B. Jung, T. L. Wee, T. Ling, T. Chan, N. Chung, J. W. Ting, S. Lakshmipathi, J. Son, J. Hwang, L. Zhang, R. Low, R. Krishnan, T. Kitamura, Y. You, C. Seet, H. Cong, D. Shum, J. Wong, S. Woo, J. Lam, E. Quek, A. See, S. Siah
We demonstrate a fully functional embedded MRAM (eMRAM) macro integrated into a 22-nm FD-SOI CMOS platform. This macro combined with eFlash-flavor MTJ film stacks shows median-die bit error rate (BER) < 1 ppm after 5× solder reflows. It also meets the automotive grade-1 data retention requirement and shows intrinsic stand-by magnetic immunity of 1.4 kOe (BER criteria = 1 ppm) after 1-hr exposure at 25 °C. The results reveal that eMRAM is capable of serving a broad spectrum of eFlash applications at 22 nm or beyond.
我们展示了一个全功能嵌入式MRAM (eMRAM)宏集成到一个22纳米FD-SOI CMOS平台。该宏与eflash风格的MTJ薄膜堆栈相结合，在5次焊料回流后，中芯误码率(BER) < 1ppm。它还符合汽车一级数据保留要求，并在25°C下暴露1小时后显示出1.4 kOe (BER标准= 1 ppm)的固有待机磁抗扰度。结果表明，eMRAM能够在22纳米或更高的范围内服务于广泛的eFlash应用。
{"title":"22-nm FD-SOI Embedded MRAM with Full Solder Reflow Compatibility and Enhanced Magnetic Immunity","authors":"K. Lee, K. Yamane, S. Noh, V. B. Naik, H. Yang, S. Jang, J. Kwon, B. Behin-Aein, R. Chao, J. H. Lim, K. S., K. W. Gan, D. Zeng, N. Thiyagarajah, L. C. Goh, B. Liu, E. Toh, B. Jung, T. L. Wee, T. Ling, T. Chan, N. Chung, J. W. Ting, S. Lakshmipathi, J. Son, J. Hwang, L. Zhang, R. Low, R. Krishnan, T. Kitamura, Y. You, C. Seet, H. Cong, D. Shum, J. Wong, S. Woo, J. Lam, E. Quek, A. See, S. Siah","doi":"10.1109/VLSIT.2018.8510655","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510655","url":null,"abstract":"We demonstrate a fully functional embedded MRAM (eMRAM) macro integrated into a 22-nm FD-SOI CMOS platform. This macro combined with eFlash-flavor MTJ film stacks shows median-die bit error rate (BER) < 1 ppm after 5× solder reflows. It also meets the automotive grade-1 data retention requirement and shows intrinsic stand-by magnetic immunity of 1.4 kOe (BER criteria = 1 ppm) after 1-hr exposure at 25 °C. The results reveal that eMRAM is capable of serving a broad spectrum of eFlash applications at 22 nm or beyond.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"236 1","pages":"183-184"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76840642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510626
D. Kwon, Y. Liao, Yen-Kai Lin, J. Duarte, K. Chatterjee, A. Tan, A. Yadav, C. Hu, Z. Krivokapic, S. Salahuddin
We report on the measurement of a 101-stage ring oscillator (RO) consisting of state-of-the-art 14 nm FinFET devices with a ferroelectric gate layer that exhibits negative capacitance. We show that the gate stage delay as a function of applied voltage can be directly modeled from DC characteristics of the individual NC-nFET and NC-pFET devices that constitute the RO, thereby demonstrating that there is no slowdown of the NC effect at the highest speed tested - per-stage delay as small as 7.2 ps.
{"title":"Response Speed of Negative Capacitance FinFETs","authors":"D. Kwon, Y. Liao, Yen-Kai Lin, J. Duarte, K. Chatterjee, A. Tan, A. Yadav, C. Hu, Z. Krivokapic, S. Salahuddin","doi":"10.1109/VLSIT.2018.8510626","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510626","url":null,"abstract":"We report on the measurement of a 101-stage ring oscillator (RO) consisting of state-of-the-art 14 nm FinFET devices with a ferroelectric gate layer that exhibits negative capacitance. We show that the gate stage delay as a function of applied voltage can be directly modeled from DC characteristics of the individual NC-nFET and NC-pFET devices that constitute the RO, thereby demonstrating that there is no slowdown of the NC effect at the highest speed tested - per-stage delay as small as 7.2 ps.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"16 1","pages":"49-50"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77101622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510696
Y. Tang, C. Su, Y.-S. Wang, K. Kao, T.-L. Wu, P. Sung, F. Hou, C. Wang, M. Yeh, Y. Lee, W. Wu, G. Huang, J. Shieh, W. Yeh, Y. Wang
The impact of a realistic representation of gate-oxide granularity on negative-capacitance (NC) FETs at sub-5nm node is studied by a newly developed thermodynamic energy model based on the first principle calculation (FPC). For the first time, the calculation fully couples the Landau-Khalatnikov (L-K) equation with grain-size effect equation in NC-FETs. It explains the experimental results in phase transition and reveals excellent immunity against depolarization in ferroelectric (FE) layer owing to dopant concentration and stress in thin films. A sub-5nm node (LG=10nm) NC-FET with thin FE layer (TFE~2nm) is integrated to achieve low subthreshold slope (SS) of 52mV/dec via a 1.9GPa-tensor stressed interfacial layer (IL) and 12% Zr-doped HfO2.
{"title":"A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5 nm Node","authors":"Y. Tang, C. Su, Y.-S. Wang, K. Kao, T.-L. Wu, P. Sung, F. Hou, C. Wang, M. Yeh, Y. Lee, W. Wu, G. Huang, J. Shieh, W. Yeh, Y. Wang","doi":"10.1109/VLSIT.2018.8510696","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510696","url":null,"abstract":"The impact of a realistic representation of gate-oxide granularity on negative-capacitance (NC) FETs at sub-5nm node is studied by a newly developed thermodynamic energy model based on the first principle calculation (FPC). For the first time, the calculation fully couples the Landau-Khalatnikov (L-K) equation with grain-size effect equation in NC-FETs. It explains the experimental results in phase transition and reveals excellent immunity against depolarization in ferroelectric (FE) layer owing to dopant concentration and stress in thin films. A sub-5nm node (LG=10nm) NC-FET with thin FE layer (TFE~2nm) is integrated to achieve low subthreshold slope (SS) of 52mV/dec via a 1.9GPa-tensor stressed interfacial layer (IL) and 12% Zr-doped HfO2.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"16 1","pages":"45-46"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72712127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510677
P. Coudrain, J. Colonna, L. Collin, R. Prieto, L. Fréchette, J. Barrau, G. Savelli, P. Vivet, Q. Struss, J. Widiez, K. Vladimirova, K. Triantopoulos, H. Beckrich-Ros, M. Vilarrubí, G. Laguna, H. Azarkish, M. Shirazi, J. Michailos
This paper describes evolutions of circuit environment to face an ever-increasing thermal challenge, from early design stage down to the final package. To illustrate this critical concern we give a portrayal of innovative technologies and concepts studied for efficient thermal management from low to high power electronics, with an emphasis on hot spot management.
{"title":"Shaping circuit environment to face the thermal challenge Innovative technologies from low to high power electronics","authors":"P. Coudrain, J. Colonna, L. Collin, R. Prieto, L. Fréchette, J. Barrau, G. Savelli, P. Vivet, Q. Struss, J. Widiez, K. Vladimirova, K. Triantopoulos, H. Beckrich-Ros, M. Vilarrubí, G. Laguna, H. Azarkish, M. Shirazi, J. Michailos","doi":"10.1109/VLSIT.2018.8510677","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510677","url":null,"abstract":"This paper describes evolutions of circuit environment to face an ever-increasing thermal challenge, from early design stage down to the final package. To illustrate this critical concern we give a portrayal of innovative technologies and concepts studied for efficient thermal management from low to high power electronics, with an emphasis on hot spot management.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"65 1","pages":"15-16"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74730110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510683
A. Mocuta, P. Weckx, S. Demuynck, D. Radisic, Y. Oniki, J. Ryckaert
We look at several scaling boosters necessary to accomplish CMOS area scaling towards the 2nm node. We consider aspects of standard cell area scaling, transistor architecture, SRAM, and BEOL. We also demonstrate integrated flows and hardware feasibility for such scaling boosters.
{"title":"Enabling CMOS Scaling Towards 3nm and Beyond","authors":"A. Mocuta, P. Weckx, S. Demuynck, D. Radisic, Y. Oniki, J. Ryckaert","doi":"10.1109/VLSIT.2018.8510683","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510683","url":null,"abstract":"We look at several scaling boosters necessary to accomplish CMOS area scaling towards the 2nm node. We consider aspects of standard cell area scaling, transistor architecture, SRAM, and BEOL. We also demonstrate integrated flows and hardware feasibility for such scaling boosters.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"53 369 1","pages":"147-148"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83747559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510688
H. Lue, Wei-Chen Chen, Hung-Sheng Chang, Keh-Chung Wang, Chih-Yuan Lu
An AND-type stackable 3D NVM architecture is proposed to provide an ultra-high density AI computing memory with low power. The advantages are: (1) All memory transistors in the 3D array are connected in parallel, thus enable the sum-of-product operation. (2) The 3D NAND like architecture is possible to stack to > 64 layers, thus provides ultra-high density (>128Gb) AI memory. (3) Many bit lines (>1KB) can operate in parallel for high bandwidth. (4) Uses low-power +/− FN programming/erasing which allows high parallelism, and is bit-alterable thus is ideal for training or transfer learning. (5) Excellent linearity of output current with respect to bitline bias, thus enabling ideal analog computation. (6) Adequate sensing current of the summed product thus permits fast access read for inference device. The proposed memory architecture can achieve TOPS/W>10, which is 10X greater than the conventional von Neumann architecture.
{"title":"A Novel 3D AND-type NVM Architecture Capable of High-density, Low-power In-Memory Sum-of-Product Computation for Artificial Intelligence Application","authors":"H. Lue, Wei-Chen Chen, Hung-Sheng Chang, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.1109/VLSIT.2018.8510688","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510688","url":null,"abstract":"An AND-type stackable 3D NVM architecture is proposed to provide an ultra-high density AI computing memory with low power. The advantages are: (1) All memory transistors in the 3D array are connected in parallel, thus enable the sum-of-product operation. (2) The 3D NAND like architecture is possible to stack to > 64 layers, thus provides ultra-high density (>128Gb) AI memory. (3) Many bit lines (>1KB) can operate in parallel for high bandwidth. (4) Uses low-power +/− FN programming/erasing which allows high parallelism, and is bit-alterable thus is ideal for training or transfer learning. (5) Excellent linearity of output current with respect to bitline bias, thus enabling ideal analog computation. (6) Adequate sensing current of the summed product thus permits fast access read for inference device. The proposed memory architecture can achieve TOPS/W>10, which is 10X greater than the conventional von Neumann architecture.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"9 1","pages":"177-178"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85227032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510681
Jongmyung Yoo, Y. Koo, Solomon Amsalu Chekol, Jaehyuk Park, Jeonghwan Song, H. Hwang
We have investigated various Te-based binary materials for Ovonic Threshold Switch (OTS) selector application. We found that both Te composition and difference in atomic radius of elements composing the telluride film are the key control parameters to maximize the OTS characteristics such as low leakage current (<5 nA for device area of 30 nm2), good switching endurance (108), and thermal stability (450°C).
{"title":"Te-based binary OTS selectors with excellent selectivity (>105), endurance (>108) and thermal stability (>450°C)","authors":"Jongmyung Yoo, Y. Koo, Solomon Amsalu Chekol, Jaehyuk Park, Jeonghwan Song, H. Hwang","doi":"10.1109/VLSIT.2018.8510681","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510681","url":null,"abstract":"We have investigated various Te-based binary materials for Ovonic Threshold Switch (OTS) selector application. We found that both Te composition and difference in atomic radius of elements composing the telluride film are the key control parameters to maximize the OTS characteristics such as low leakage current (<5 nA for device area of 30 nm2), good switching endurance (108), and thermal stability (450°C).","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"16 1","pages":"207-208"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84375183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510691
Hong Zhou, D. Kwon, A. Sachid, Y. Liao, K. Chatterjee, A. Tan, A. Yadav, C. Hu, S. Salahuddin
We report on negative capacitance (NC) FinFETs with ferroelectric Hf0.5Zr0.5O2 (HZO) as gate dielectric on fully depleted silicon on insulator (FDSOI) substrate with various channel length (LCH) of 450 nm to 30 nm and multiple fin widths (WFIN) of 200 nm to 30 nm. We demonstrate all signature characteristics expected from NCFET: nearly hysteresis free operation (~3 mV), <60 mV/decade subthreshold swing (SS) with an average SS of 54.5 mV/dec for ~2 orders of ID and to the best of our knowledge, for the first time in Si MOSFETs, negative Drain Induced Barrier Lowering (DIBL) and Negative Differential Resistance (NDR). Remarkably, we observe significant improvement in the short channel effect compared to control FinFETs: both SS and DIBL are substantially lower for the NCFET for the same Lch/WFin ratio. Importantly, these benefits become increasingly larger for shorter channel lengths.
{"title":"Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect","authors":"Hong Zhou, D. Kwon, A. Sachid, Y. Liao, K. Chatterjee, A. Tan, A. Yadav, C. Hu, S. Salahuddin","doi":"10.1109/VLSIT.2018.8510691","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510691","url":null,"abstract":"We report on negative capacitance (NC) FinFETs with ferroelectric Hf0.5Zr0.5O2 (HZO) as gate dielectric on fully depleted silicon on insulator (FDSOI) substrate with various channel length (LCH) of 450 nm to 30 nm and multiple fin widths (WFIN) of 200 nm to 30 nm. We demonstrate all signature characteristics expected from NCFET: nearly hysteresis free operation (~3 mV), <60 mV/decade subthreshold swing (SS) with an average SS of 54.5 mV/dec for ~2 orders of ID and to the best of our knowledge, for the first time in Si MOSFETs, negative Drain Induced Barrier Lowering (DIBL) and Negative Differential Resistance (NDR). Remarkably, we observe significant improvement in the short channel effect compared to control FinFETs: both SS and DIBL are substantially lower for the NCFET for the same Lch/WFin ratio. Importantly, these benefits become increasingly larger for shorter channel lengths.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"19 1","pages":"53-54"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89967734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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