Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510655
K. Lee, K. Yamane, S. Noh, V. B. Naik, H. Yang, S. Jang, J. Kwon, B. Behin-Aein, R. Chao, J. H. Lim, K. S., K. W. Gan, D. Zeng, N. Thiyagarajah, L. C. Goh, B. Liu, E. Toh, B. Jung, T. L. Wee, T. Ling, T. Chan, N. Chung, J. W. Ting, S. Lakshmipathi, J. Son, J. Hwang, L. Zhang, R. Low, R. Krishnan, T. Kitamura, Y. You, C. Seet, H. Cong, D. Shum, J. Wong, S. Woo, J. Lam, E. Quek, A. See, S. Siah
We demonstrate a fully functional embedded MRAM (eMRAM) macro integrated into a 22-nm FD-SOI CMOS platform. This macro combined with eFlash-flavor MTJ film stacks shows median-die bit error rate (BER) < 1 ppm after 5× solder reflows. It also meets the automotive grade-1 data retention requirement and shows intrinsic stand-by magnetic immunity of 1.4 kOe (BER criteria = 1 ppm) after 1-hr exposure at 25 °C. The results reveal that eMRAM is capable of serving a broad spectrum of eFlash applications at 22 nm or beyond.
我们展示了一个全功能嵌入式MRAM (eMRAM)宏集成到一个22纳米FD-SOI CMOS平台。该宏与eflash风格的MTJ薄膜堆栈相结合，在5次焊料回流后，中芯误码率(BER) < 1ppm。它还符合汽车一级数据保留要求，并在25°C下暴露1小时后显示出1.4 kOe (BER标准= 1 ppm)的固有待机磁抗扰度。结果表明，eMRAM能够在22纳米或更高的范围内服务于广泛的eFlash应用。
{"title":"22-nm FD-SOI Embedded MRAM with Full Solder Reflow Compatibility and Enhanced Magnetic Immunity","authors":"K. Lee, K. Yamane, S. Noh, V. B. Naik, H. Yang, S. Jang, J. Kwon, B. Behin-Aein, R. Chao, J. H. Lim, K. S., K. W. Gan, D. Zeng, N. Thiyagarajah, L. C. Goh, B. Liu, E. Toh, B. Jung, T. L. Wee, T. Ling, T. Chan, N. Chung, J. W. Ting, S. Lakshmipathi, J. Son, J. Hwang, L. Zhang, R. Low, R. Krishnan, T. Kitamura, Y. You, C. Seet, H. Cong, D. Shum, J. Wong, S. Woo, J. Lam, E. Quek, A. See, S. Siah","doi":"10.1109/VLSIT.2018.8510655","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510655","url":null,"abstract":"We demonstrate a fully functional embedded MRAM (eMRAM) macro integrated into a 22-nm FD-SOI CMOS platform. This macro combined with eFlash-flavor MTJ film stacks shows median-die bit error rate (BER) < 1 ppm after 5× solder reflows. It also meets the automotive grade-1 data retention requirement and shows intrinsic stand-by magnetic immunity of 1.4 kOe (BER criteria = 1 ppm) after 1-hr exposure at 25 °C. The results reveal that eMRAM is capable of serving a broad spectrum of eFlash applications at 22 nm or beyond.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"236 1","pages":"183-184"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76840642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510658
Li Huang, B. Dong, Xin Guo, Yuhua Chang, N. Chen, Xingzhen Huang, Hong Wang, Chengkuo Lee, K. Ang
We demonstrate the first black phosphorus phototransistor integrated with Si photonics waveguide system towards mid-infrared (MIR) sensing. At a wavelength of 3.78 µm, the black phosphorus phototransistor achieves a high responsivity of 0.7 A/W under a small drain bias of −1 V at room-temperature. Additionally, the device offers gate and drain bias tunability to suppress dark current while simultaneously optimize photo-response performance. Our results reveal the potential of black phosphorus for MIR detection to enable the realization of integrated on-chip systems for MIR sensing applications.
我们展示了第一个集成了硅光子波导系统的黑磷光电晶体管，用于中红外(MIR)传感。在3.78µm波长下，在- 1 V的漏极偏置下，黑磷光电晶体管的响应率高达0.7 a /W。此外，该器件提供栅极和漏极偏置可调性，以抑制暗电流，同时优化光响应性能。我们的研究结果揭示了黑磷在MIR检测中的潜力，使MIR传感应用的集成片上系统得以实现。
{"title":"Integration of 2D Black Phosphorus Phototransistor and Silicon Photonics Waveguide System Towards Mid-Infrared On-Chip Sensing Applications","authors":"Li Huang, B. Dong, Xin Guo, Yuhua Chang, N. Chen, Xingzhen Huang, Hong Wang, Chengkuo Lee, K. Ang","doi":"10.1109/VLSIT.2018.8510658","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510658","url":null,"abstract":"We demonstrate the first black phosphorus phototransistor integrated with Si photonics waveguide system towards mid-infrared (MIR) sensing. At a wavelength of 3.78 µm, the black phosphorus phototransistor achieves a high responsivity of 0.7 A/W under a small drain bias of −1 V at room-temperature. Additionally, the device offers gate and drain bias tunability to suppress dark current while simultaneously optimize photo-response performance. Our results reveal the potential of black phosphorus for MIR detection to enable the realization of integrated on-chip systems for MIR sensing applications.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"44 1","pages":"161-162"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81276745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510634
Yan Liao, Huaqiang Wu, W. Wan, Wenqiang Zhang, B. Gao, H. Philip Wong, H. Qian
Resistive cross-point array can be used to implement vector-matrix multiplication in analog fashion. However, the output is in the form of analog current, and thus requires A/D conversion prior to digital storage. This paper develops and demonstrates a novel in-memory matrix-matrix multiplication method (M2M) that can compute and store the result directly inside the memory itself without requiring A/D conversion. Compared with the conventional approach, M2M provides >10 × improvement in energy and area efficiency, and another 2 orders improvement when matrices are low-rank and sparse.
{"title":"Novel In-Memory Matrix-Matrix Multiplication with Resistive Cross-Point Arrays","authors":"Yan Liao, Huaqiang Wu, W. Wan, Wenqiang Zhang, B. Gao, H. Philip Wong, H. Qian","doi":"10.1109/VLSIT.2018.8510634","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510634","url":null,"abstract":"Resistive cross-point array can be used to implement vector-matrix multiplication in analog fashion. However, the output is in the form of analog current, and thus requires A/D conversion prior to digital storage. This paper develops and demonstrates a novel in-memory matrix-matrix multiplication method (M2M) that can compute and store the result directly inside the memory itself without requiring A/D conversion. Compared with the conventional approach, M2M provides >10 × improvement in energy and area efficiency, and another 2 orders improvement when matrices are low-rank and sparse.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"41 1","pages":"31-32"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85905565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510707
S. DeBoer
Roughly 300 billion gigabytes (GB) of semiconductor memory will be produced this year (2018) — 40GB for every person on the planet – with projections to double every two years for the foreseeable future. As user demand for large amounts of instantly accessible data continues to increase, memory is becoming both a solution and a bottleneck, spurring the industry to redefine how memory is used in systems and to innovate for new types of memory. This paper discusses the scaling roadmap for NAND and DRAM memories, the introduction of new emerging memories to supplement NAND and DRAM, and opportunities for changes in system architectures to exploit the inherent capabilities of memory.
{"title":"Memory Technology: The Core to Enable Future Computing Systems","authors":"S. DeBoer","doi":"10.1109/VLSIT.2018.8510707","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510707","url":null,"abstract":"Roughly 300 billion gigabytes (GB) of semiconductor memory will be produced this year (2018) — 40GB for every person on the planet – with projections to double every two years for the foreseeable future. As user demand for large amounts of instantly accessible data continues to increase, memory is becoming both a solution and a bottleneck, spurring the industry to redefine how memory is used in systems and to innovate for new types of memory. This paper discusses the scaling roadmap for NAND and DRAM memories, the introduction of new emerging memories to supplement NAND and DRAM, and opportunities for changes in system architectures to exploit the inherent capabilities of memory.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"25 3-4 1","pages":"3-6"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85944371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510683
A. Mocuta, P. Weckx, S. Demuynck, D. Radisic, Y. Oniki, J. Ryckaert
We look at several scaling boosters necessary to accomplish CMOS area scaling towards the 2nm node. We consider aspects of standard cell area scaling, transistor architecture, SRAM, and BEOL. We also demonstrate integrated flows and hardware feasibility for such scaling boosters.
{"title":"Enabling CMOS Scaling Towards 3nm and Beyond","authors":"A. Mocuta, P. Weckx, S. Demuynck, D. Radisic, Y. Oniki, J. Ryckaert","doi":"10.1109/VLSIT.2018.8510683","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510683","url":null,"abstract":"We look at several scaling boosters necessary to accomplish CMOS area scaling towards the 2nm node. We consider aspects of standard cell area scaling, transistor architecture, SRAM, and BEOL. We also demonstrate integrated flows and hardware feasibility for such scaling boosters.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"53 369 1","pages":"147-148"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83747559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510696
Y. Tang, C. Su, Y.-S. Wang, K. Kao, T.-L. Wu, P. Sung, F. Hou, C. Wang, M. Yeh, Y. Lee, W. Wu, G. Huang, J. Shieh, W. Yeh, Y. Wang
The impact of a realistic representation of gate-oxide granularity on negative-capacitance (NC) FETs at sub-5nm node is studied by a newly developed thermodynamic energy model based on the first principle calculation (FPC). For the first time, the calculation fully couples the Landau-Khalatnikov (L-K) equation with grain-size effect equation in NC-FETs. It explains the experimental results in phase transition and reveals excellent immunity against depolarization in ferroelectric (FE) layer owing to dopant concentration and stress in thin films. A sub-5nm node (LG=10nm) NC-FET with thin FE layer (TFE~2nm) is integrated to achieve low subthreshold slope (SS) of 52mV/dec via a 1.9GPa-tensor stressed interfacial layer (IL) and 12% Zr-doped HfO2.
{"title":"A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5 nm Node","authors":"Y. Tang, C. Su, Y.-S. Wang, K. Kao, T.-L. Wu, P. Sung, F. Hou, C. Wang, M. Yeh, Y. Lee, W. Wu, G. Huang, J. Shieh, W. Yeh, Y. Wang","doi":"10.1109/VLSIT.2018.8510696","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510696","url":null,"abstract":"The impact of a realistic representation of gate-oxide granularity on negative-capacitance (NC) FETs at sub-5nm node is studied by a newly developed thermodynamic energy model based on the first principle calculation (FPC). For the first time, the calculation fully couples the Landau-Khalatnikov (L-K) equation with grain-size effect equation in NC-FETs. It explains the experimental results in phase transition and reveals excellent immunity against depolarization in ferroelectric (FE) layer owing to dopant concentration and stress in thin films. A sub-5nm node (LG=10nm) NC-FET with thin FE layer (TFE~2nm) is integrated to achieve low subthreshold slope (SS) of 52mV/dec via a 1.9GPa-tensor stressed interfacial layer (IL) and 12% Zr-doped HfO2.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"16 1","pages":"45-46"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72712127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510671
James Brown, R. Gao, Z. Ji, Jiezhi Chen, Jixuan Wu, Jianfu Zhang, Bo Zhou, Q. Shi, Jacob Crowford, Weidong Zhang
A novel True Random Number Generator (TRNG), using random telegraph noise (RTN) as the entropy source, is proposed to address speed, design area, power and cost simultaneously. For the first time, the proposed design breaks the inherent speed limitation and generates true random numbers up to 3Mbps with ultra-low power. This is over 10 times faster than the state-of-the-art RTN-TRNG [6]. Moreover, the new design does not require selection of devices and thus avoids the use of large transistor array and laborious post-selection process. This reduces the circuit area and the cost. The proposed TRNG has been successfully validated on three different processes and they all passed the National Institute of Standards and Technology (NIST) tests, making it a suitable candidate for future cryptographically secured applications in the internet of things (IoT).
{"title":"A low-power and high-speed True Random Number Generator using generated RTN","authors":"James Brown, R. Gao, Z. Ji, Jiezhi Chen, Jixuan Wu, Jianfu Zhang, Bo Zhou, Q. Shi, Jacob Crowford, Weidong Zhang","doi":"10.1109/VLSIT.2018.8510671","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510671","url":null,"abstract":"A novel True Random Number Generator (TRNG), using random telegraph noise (RTN) as the entropy source, is proposed to address speed, design area, power and cost simultaneously. For the first time, the proposed design breaks the inherent speed limitation and generates true random numbers up to 3Mbps with ultra-low power. This is over 10 times faster than the state-of-the-art RTN-TRNG [6]. Moreover, the new design does not require selection of devices and thus avoids the use of large transistor array and laborious post-selection process. This reduces the circuit area and the cost. The proposed TRNG has been successfully validated on three different processes and they all passed the National Institute of Standards and Technology (NIST) tests, making it a suitable candidate for future cryptographically secured applications in the internet of things (IoT).","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"26 1","pages":"95-96"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82047693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510688
H. Lue, Wei-Chen Chen, Hung-Sheng Chang, Keh-Chung Wang, Chih-Yuan Lu
An AND-type stackable 3D NVM architecture is proposed to provide an ultra-high density AI computing memory with low power. The advantages are: (1) All memory transistors in the 3D array are connected in parallel, thus enable the sum-of-product operation. (2) The 3D NAND like architecture is possible to stack to > 64 layers, thus provides ultra-high density (>128Gb) AI memory. (3) Many bit lines (>1KB) can operate in parallel for high bandwidth. (4) Uses low-power +/− FN programming/erasing which allows high parallelism, and is bit-alterable thus is ideal for training or transfer learning. (5) Excellent linearity of output current with respect to bitline bias, thus enabling ideal analog computation. (6) Adequate sensing current of the summed product thus permits fast access read for inference device. The proposed memory architecture can achieve TOPS/W>10, which is 10X greater than the conventional von Neumann architecture.
{"title":"A Novel 3D AND-type NVM Architecture Capable of High-density, Low-power In-Memory Sum-of-Product Computation for Artificial Intelligence Application","authors":"H. Lue, Wei-Chen Chen, Hung-Sheng Chang, Keh-Chung Wang, Chih-Yuan Lu","doi":"10.1109/VLSIT.2018.8510688","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510688","url":null,"abstract":"An AND-type stackable 3D NVM architecture is proposed to provide an ultra-high density AI computing memory with low power. The advantages are: (1) All memory transistors in the 3D array are connected in parallel, thus enable the sum-of-product operation. (2) The 3D NAND like architecture is possible to stack to > 64 layers, thus provides ultra-high density (>128Gb) AI memory. (3) Many bit lines (>1KB) can operate in parallel for high bandwidth. (4) Uses low-power +/− FN programming/erasing which allows high parallelism, and is bit-alterable thus is ideal for training or transfer learning. (5) Excellent linearity of output current with respect to bitline bias, thus enabling ideal analog computation. (6) Adequate sensing current of the summed product thus permits fast access read for inference device. The proposed memory architecture can achieve TOPS/W>10, which is 10X greater than the conventional von Neumann architecture.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"9 1","pages":"177-178"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85227032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510681
Jongmyung Yoo, Y. Koo, Solomon Amsalu Chekol, Jaehyuk Park, Jeonghwan Song, H. Hwang
We have investigated various Te-based binary materials for Ovonic Threshold Switch (OTS) selector application. We found that both Te composition and difference in atomic radius of elements composing the telluride film are the key control parameters to maximize the OTS characteristics such as low leakage current (<5 nA for device area of 30 nm2), good switching endurance (108), and thermal stability (450°C).
{"title":"Te-based binary OTS selectors with excellent selectivity (>105), endurance (>108) and thermal stability (>450°C)","authors":"Jongmyung Yoo, Y. Koo, Solomon Amsalu Chekol, Jaehyuk Park, Jeonghwan Song, H. Hwang","doi":"10.1109/VLSIT.2018.8510681","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510681","url":null,"abstract":"We have investigated various Te-based binary materials for Ovonic Threshold Switch (OTS) selector application. We found that both Te composition and difference in atomic radius of elements composing the telluride film are the key control parameters to maximize the OTS characteristics such as low leakage current (<5 nA for device area of 30 nm2), good switching endurance (108), and thermal stability (450°C).","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"16 1","pages":"207-208"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84375183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510691
Hong Zhou, D. Kwon, A. Sachid, Y. Liao, K. Chatterjee, A. Tan, A. Yadav, C. Hu, S. Salahuddin
We report on negative capacitance (NC) FinFETs with ferroelectric Hf0.5Zr0.5O2 (HZO) as gate dielectric on fully depleted silicon on insulator (FDSOI) substrate with various channel length (LCH) of 450 nm to 30 nm and multiple fin widths (WFIN) of 200 nm to 30 nm. We demonstrate all signature characteristics expected from NCFET: nearly hysteresis free operation (~3 mV), <60 mV/decade subthreshold swing (SS) with an average SS of 54.5 mV/dec for ~2 orders of ID and to the best of our knowledge, for the first time in Si MOSFETs, negative Drain Induced Barrier Lowering (DIBL) and Negative Differential Resistance (NDR). Remarkably, we observe significant improvement in the short channel effect compared to control FinFETs: both SS and DIBL are substantially lower for the NCFET for the same Lch/WFin ratio. Importantly, these benefits become increasingly larger for shorter channel lengths.
{"title":"Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect","authors":"Hong Zhou, D. Kwon, A. Sachid, Y. Liao, K. Chatterjee, A. Tan, A. Yadav, C. Hu, S. Salahuddin","doi":"10.1109/VLSIT.2018.8510691","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510691","url":null,"abstract":"We report on negative capacitance (NC) FinFETs with ferroelectric Hf0.5Zr0.5O2 (HZO) as gate dielectric on fully depleted silicon on insulator (FDSOI) substrate with various channel length (LCH) of 450 nm to 30 nm and multiple fin widths (WFIN) of 200 nm to 30 nm. We demonstrate all signature characteristics expected from NCFET: nearly hysteresis free operation (~3 mV), <60 mV/decade subthreshold swing (SS) with an average SS of 54.5 mV/dec for ~2 orders of ID and to the best of our knowledge, for the first time in Si MOSFETs, negative Drain Induced Barrier Lowering (DIBL) and Negative Differential Resistance (NDR). Remarkably, we observe significant improvement in the short channel effect compared to control FinFETs: both SS and DIBL are substantially lower for the NCFET for the same Lch/WFin ratio. Importantly, these benefits become increasingly larger for shorter channel lengths.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"19 1","pages":"53-54"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89967734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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