Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510656
Yi Zhang, Bing Chen, Wenfeng Dong, Wei Liu, Shun Xu, R. Cheng, Shiuh-Wuu Lee, Yi Zhao
We propose and demonstrate the world-first ternary content ternary addressable memory (TCAM) cell using only two MOS diodes. The diodes are with simple HfO2/Al2O3/GeOx/Ge-sub structure and could be fabricated by fully CMOS compatible process. Owing to the adoption of a very thin GeOx interfacial layer, the diodes show both excellent resistive switching and rectifying characteristics. Furthermore, TCAM cell and array are built with two diodes connected back-to-back. Finally, a well-functioning 8×16 HfO2/Al2O3/GeOx/Ge-sub TCAM array for parallel multi-data search is demonstrated. This novel diode-based cell structure is very promising for future energy and area efficient TCAM applications.
{"title":"Non-Volatile Ternary Content Addressable Memory (TCAM) with Two HfO2/Al2O3/GeOx/Ge MOS Diodes","authors":"Yi Zhang, Bing Chen, Wenfeng Dong, Wei Liu, Shun Xu, R. Cheng, Shiuh-Wuu Lee, Yi Zhao","doi":"10.1109/VLSIT.2018.8510656","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510656","url":null,"abstract":"We propose and demonstrate the world-first ternary content ternary addressable memory (TCAM) cell using only two MOS diodes. The diodes are with simple HfO<inf>2</inf>/Al<inf>2</inf>O<inf>3</inf>/GeO<inf>x</inf>/Ge-sub structure and could be fabricated by fully CMOS compatible process. Owing to the adoption of a very thin GeO<inf>x</inf> interfacial layer, the diodes show both excellent resistive switching and rectifying characteristics. Furthermore, TCAM cell and array are built with two diodes connected back-to-back. Finally, a well-functioning 8×16 HfO<inf>2</inf>/Al<inf>2</inf>O<inf>3</inf>/GeO<inf>x</inf>/Ge-sub TCAM array for parallel multi-data search is demonstrated. This novel diode-based cell structure is very promising for future energy and area efficient TCAM applications.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"11 1","pages":"105-106"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82273422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510676
R. Mochida, K. Kouno, Y. Hayata, M. Nakayama, T. Ono, Hitoshi Suwa, R. Yasuhara, K. Katayama, T. Mikawa, Y. Gohou
This paper presents low-power neural-network (NN) processor using ReRAM to store weights as analog resistance for future AI computing. We propose ReRAM perceptron circuit for realizing large scale integration, highly accurate cell current controlled writing scheme, and flexible network architecture (FNA) in which any NNs can be configured. Fabricated 180nm test chip shows well-controlled analog cell current with linear 30μA dynamic range and 0.59μA variation of 1 sigma, results in 90.8% MNIST numerical recognition rate. Furthermore, 4M synapses integrated 40nm test chip achieves lower analog cell current and 66.5 TOPS/W power efficiency.
{"title":"A 4M Synapses integrated Analog ReRAM based 66.5 TOPS/W Neural-Network Processor with Cell Current Controlled Writing and Flexible Network Architecture","authors":"R. Mochida, K. Kouno, Y. Hayata, M. Nakayama, T. Ono, Hitoshi Suwa, R. Yasuhara, K. Katayama, T. Mikawa, Y. Gohou","doi":"10.1109/VLSIT.2018.8510676","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510676","url":null,"abstract":"This paper presents low-power neural-network (NN) processor using ReRAM to store weights as analog resistance for future AI computing. We propose ReRAM perceptron circuit for realizing large scale integration, highly accurate cell current controlled writing scheme, and flexible network architecture (FNA) in which any NNs can be configured. Fabricated 180nm test chip shows well-controlled analog cell current with linear 30μA dynamic range and 0.59μA variation of 1 sigma, results in 90.8% MNIST numerical recognition rate. Furthermore, 4M synapses integrated 40nm test chip achieves lower analog cell current and 66.5 TOPS/W power efficiency.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"4 1","pages":"175-176"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79542681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510690
Wei Wu, Huaqiang Wu, B. Gao, Peng Yao, Xiaodong Zhang, Xiaochen Peng, Shimeng Yu, H. Qian
The conductance tuning linearity is an important parameter of analog RRAM for neuromorphic computing. This work presents a novel methodology to improve the conductance tuning linearity of the filamentary RRAM. An electro-thermal modulation layer is designed and introduced to control the distribution of electric field and temperature in the filament region. For the first time, a HfOx based RRAM is demonstrated with linear analog SET, linear analog RESET, 50ns speed, 10× analog tuning window, 100kΩ on-state resistance, and high temperature retention for multilevel states. The excellent performances of the analog RRAM devices enable high accuracy online learning in a neural network.
{"title":"A Methodology to Improve Linearity of Analog RRAM for Neuromorphic Computing","authors":"Wei Wu, Huaqiang Wu, B. Gao, Peng Yao, Xiaodong Zhang, Xiaochen Peng, Shimeng Yu, H. Qian","doi":"10.1109/VLSIT.2018.8510690","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510690","url":null,"abstract":"The conductance tuning linearity is an important parameter of analog RRAM for neuromorphic computing. This work presents a novel methodology to improve the conductance tuning linearity of the filamentary RRAM. An electro-thermal modulation layer is designed and introduced to control the distribution of electric field and temperature in the filament region. For the first time, a HfOx based RRAM is demonstrated with linear analog SET, linear analog RESET, 50ns speed, 10× analog tuning window, 100kΩ on-state resistance, and high temperature retention for multilevel states. The excellent performances of the analog RRAM devices enable high accuracy online learning in a neural network.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"17 1","pages":"103-104"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79545753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510669
Y. Yamaga, Yoshiaki Deguchi, S. Fukuyama, K. Takeuchi
Highly reliable Approximate-ReRAM (A-ReRAM) with Pixel-to-Pixel Data Matching (P2P-DM) and Inter-Pixel error-correcting code (IP-ECC) is proposed to recognize the image accurately by deep neural network (DNN). By specializing for the image recognition applications and modulating the image data based on pixel-to-pixel features and ReRAM error characteristics, data-retention time and endurance of ReRAM increases by 5x and 3.3x, respectively.
{"title":"5x Reliability Enhanced 40nm TaOx Approximate-ReRAM with Domain-Specific Computing for Real-time Image Recognition of IoT Edge Devices","authors":"Y. Yamaga, Yoshiaki Deguchi, S. Fukuyama, K. Takeuchi","doi":"10.1109/VLSIT.2018.8510669","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510669","url":null,"abstract":"Highly reliable Approximate-ReRAM (A-ReRAM) with Pixel-to-Pixel Data Matching (P2P-DM) and Inter-Pixel error-correcting code (IP-ECC) is proposed to recognize the image accurately by deep neural network (DNN). By specializing for the image recognition applications and modulating the image data based on pixel-to-pixel features and ReRAM error characteristics, data-retention time and endurance of ReRAM increases by 5x and 3.3x, respectively.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"26 1","pages":"109-110"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75482853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510667
Sungtae Lee, Suhwan Lim, Nagyong Choi, J. Bae, Chul-Heung Kim, Soochang Lee, Dong Hwan Lee, Tackhwi Lee, Sungyong Chung, Byung-Gook Park, Jong-Ho Lee
Four synaptic devices are introduced for spiking neural networks (SNNs) and deep neural networks (DNNs). Unsupervised learning is successfully demonstrated by applying the STDP learning rule reflecting the LTP/LTD characteristics of the fabricated TFT-type NOR flash memory cells. Gated Schottky diode (GSD) and vertical NAND flash cell are proposed as synaptic device for DNNs. Using matched simulation, we obtained higher learning accuracy with GSD and NAND synaptic devices compared to that with a memristor-based synapse. Measured synaptic properties of the vertical NAND cells are reported for the first time.
{"title":"Neuromorphic Technology Based on Charge Storage Memory Devices","authors":"Sungtae Lee, Suhwan Lim, Nagyong Choi, J. Bae, Chul-Heung Kim, Soochang Lee, Dong Hwan Lee, Tackhwi Lee, Sungyong Chung, Byung-Gook Park, Jong-Ho Lee","doi":"10.1109/VLSIT.2018.8510667","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510667","url":null,"abstract":"Four synaptic devices are introduced for spiking neural networks (SNNs) and deep neural networks (DNNs). Unsupervised learning is successfully demonstrated by applying the STDP learning rule reflecting the LTP/LTD characteristics of the fabricated TFT-type NOR flash memory cells. Gated Schottky diode (GSD) and vertical NAND flash cell are proposed as synaptic device for DNNs. Using matched simulation, we obtained higher learning accuracy with GSD and NAND synaptic devices compared to that with a memristor-based synapse. Measured synaptic properties of the vertical NAND cells are reported for the first time.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"7 1","pages":"169-170"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73181840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510703
R. Nebashi, N. Banno, M. Miyamura, Y. Tsuji, A. Morioka, X. Bai, K. Okamoto, N. Iguchi, H. Numata, H. Hada, T. Sugibayashi, T. Sakamoto, M. Tada
Key device/circuit technologies for realizing a 28nm-node atom switch programmable logic (AS-PL) have been developed. An advanced polymer solid-electrolyte (PSE) reduces set voltage down to 1.6 V while ensuring ON-state and OFF-state reliabilities under current and voltage stress at 125°C. A fine-grain redundancy in a cross-bar array also contributes to reduce supply voltage by 6%. A routing-based wear leveling improves programming cycles by nine times. The developed technologies allow us to design the 28nm-node AS-PL with a 32% higher performance and 11% lower power.
{"title":"High-Density and Fault-Tolerant Cu Atom Switch Technology Toward 28nm-node Nonvolatile Programmable Logic","authors":"R. Nebashi, N. Banno, M. Miyamura, Y. Tsuji, A. Morioka, X. Bai, K. Okamoto, N. Iguchi, H. Numata, H. Hada, T. Sugibayashi, T. Sakamoto, M. Tada","doi":"10.1109/VLSIT.2018.8510703","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510703","url":null,"abstract":"Key device/circuit technologies for realizing a 28nm-node atom switch programmable logic (AS-PL) have been developed. An advanced polymer solid-electrolyte (PSE) reduces set voltage down to 1.6 V while ensuring ON-state and OFF-state reliabilities under current and voltage stress at 125°C. A fine-grain redundancy in a cross-bar array also contributes to reduce supply voltage by 6%. A routing-based wear leveling improves programming cycles by nine times. The developed technologies allow us to design the 28nm-node AS-PL with a 32% higher performance and 11% lower power.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"38 1","pages":"127-128"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81948100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510644
Q. Luc, C. Fan-Chiang, S. Huynh, P. Huang, H. Do, M. Ha, Y. D. Jin, T. Nguyen, K. Y. Zhang, H. C. Wang, Y. K. Lin, Y. Lin, C. Hu, H. Iwai, E. Chang
We demonstrate, for the first time, the negative capacitance (NC) In0.53Ga0.47As nMOSFET with 8-nm Hf0.5Zr0.5O2 (HZO) as ferroelectric (FE) dielectric for sub-60 mV/dec subthreshold swing (SS). The impact of annealing treatments on the FE properties and electrical characteristics of NC InGaAs nMOSFETs are investigated. Optimized annealing condition results in NC effects at the HZO/Al2O3/InGaAs nMOSFETs with steep SS property (~ 11 mV/dec).
{"title":"First Experimental Demonstration of Negative Capacitance InGaAs MOSFETs With Hf0.5Zr0.5O2 Ferroelectric Gate Stack","authors":"Q. Luc, C. Fan-Chiang, S. Huynh, P. Huang, H. Do, M. Ha, Y. D. Jin, T. Nguyen, K. Y. Zhang, H. C. Wang, Y. K. Lin, Y. Lin, C. Hu, H. Iwai, E. Chang","doi":"10.1109/VLSIT.2018.8510644","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510644","url":null,"abstract":"We demonstrate, for the first time, the negative capacitance (NC) In<inf>0.53</inf>Ga<inf>0.47</inf>As nMOSFET with 8-nm Hf<inf>0.5</inf>Zr<inf>0.5</inf>O<inf>2</inf> (HZO) as ferroelectric (FE) dielectric for sub-60 mV/dec subthreshold swing (SS). The impact of annealing treatments on the FE properties and electrical characteristics of NC InGaAs nMOSFETs are investigated. Optimized annealing condition results in NC effects at the HZO/Al<inf>2</inf>O<inf>3</inf>/InGaAs nMOSFETs with steep SS property (~ 11 mV/dec).","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"38 1","pages":"47-48"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88155282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510678
K. Jung, Chi Zhang, Tanya Liu, M. Asheghi, K. Goodson
Thermal management is critical for electronic systems ranging from servers and smartphones to radar HEMTs and hybrid vehicle converters. Rapid research progress is being achieved both on-chip and in packaging through new materials and microfluidics. One very promising area is thermal metamaterials, which offer unusual combinations of thermal, mechanical, fluidic, and other properties by means of micro- or nanoscale heterogeneity, porosity, and/or layering. Another area is the upscaling of the performance and efficiency of fluidic systems – both capillary-based and pumped, which remove heat to an external heat rejector. This talk summarizes progress and highlights collaborations with the semiconductor industry, US defense companies and the NSF center on power electronics (POETS).
{"title":"Thermal Management Research – from Power Electronics to Portables","authors":"K. Jung, Chi Zhang, Tanya Liu, M. Asheghi, K. Goodson","doi":"10.1109/VLSIT.2018.8510678","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510678","url":null,"abstract":"Thermal management is critical for electronic systems ranging from servers and smartphones to radar HEMTs and hybrid vehicle converters. Rapid research progress is being achieved both on-chip and in packaging through new materials and microfluidics. One very promising area is thermal metamaterials, which offer unusual combinations of thermal, mechanical, fluidic, and other properties by means of micro- or nanoscale heterogeneity, porosity, and/or layering. Another area is the upscaling of the performance and efficiency of fluidic systems – both capillary-based and pumped, which remove heat to an external heat rejector. This talk summarizes progress and highlights collaborations with the semiconductor industry, US defense companies and the NSF center on power electronics (POETS).","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"25 1","pages":"17-18"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89701730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Emerging nonvolatile memory (eNVM) have aroused extensive attention due to their low power and high speed. Recent advances have further moved eNVM to the forefront as key enablers of nonvolatile logics (nvLogics) for IoT devices and computing-in-memory (CIM) for AI chips. In this paper, we firstly examine the circuit-device-interaction (CDI) issues to implement high-performance memory macro. Then we review examples of emerging eNVM-based nvLogics for nonvolatile processors and CIM macro for AI chips with an emphasis on the challenges required CDI.
{"title":"Nonvolatile Circuits-Devices Interaction for Memory, Logic and Artificial Intelligence","authors":"C. Dou, Wei-Hao Chen, Cheng-Xin Xue, Wei-Yu Lin, Wei-En Lin, Jun-Yi Li, Huan-Ting Lin, Meng-Fan Chang","doi":"10.1109/VLSIT.2018.8510627","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510627","url":null,"abstract":"Emerging nonvolatile memory (eNVM) have aroused extensive attention due to their low power and high speed. Recent advances have further moved eNVM to the forefront as key enablers of nonvolatile logics (nvLogics) for IoT devices and computing-in-memory (CIM) for AI chips. In this paper, we firstly examine the circuit-device-interaction (CDI) issues to implement high-performance memory macro. Then we review examples of emerging eNVM-based nvLogics for nonvolatile processors and CIM macro for AI chips with an emphasis on the challenges required CDI.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"49 1","pages":"171-172"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77430169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510697
Zhiqiang Wei, K. Homma, K. Katayama, K. Kawai, S. Fujii, Y. Naitoh, H. Shima, H. Akinaga, S. Ito, S. Yoneda
We have fabricated a novel hydrogen sensor using optimized 0.18-μm ReRAM process. Our ReHsensor (Resistive Hydrogen Sensor) conforms with the ISO26142 standard in that it exhibits exceptional sensing capabilities, including high sensitivity, wide hydrogen concentration range (up to 4 vol.%) in air and N2 ambient, high gas selectivity (no reaction with CH4, CO, CO2, CH3OH, and CH3COCH3) and is immune to poisoning by SO2 and hexamethyl disiloxane (HMDS). As it does not require a heater, the power consumption of the ReHsensor is very low, at 0.35 mW. We used this hydrogen sensor device to develop a battery-powered all-in-one wireless hydrogen sensor unit for IoT applications.
{"title":"From Memory to Sensor: ultra-Low Power and High Selectivity Hydrogen Sensor Based on ReRAM Technology","authors":"Zhiqiang Wei, K. Homma, K. Katayama, K. Kawai, S. Fujii, Y. Naitoh, H. Shima, H. Akinaga, S. Ito, S. Yoneda","doi":"10.1109/VLSIT.2018.8510697","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510697","url":null,"abstract":"We have fabricated a novel hydrogen sensor using optimized 0.18-μm ReRAM process. Our ReHsensor (Resistive Hydrogen Sensor) conforms with the ISO26142 standard in that it exhibits exceptional sensing capabilities, including high sensitivity, wide hydrogen concentration range (up to 4 vol.%) in air and N<inf>2</inf> ambient, high gas selectivity (no reaction with CH<inf>4</inf>, CO, CO<inf>2</inf>, CH<inf>3</inf>OH, and CH<inf>3</inf>COCH<inf>3</inf>) and is immune to poisoning by SO<inf>2</inf> and hexamethyl disiloxane (HMDS). As it does not require a heater, the power consumption of the ReHsensor is very low, at 0.35 mW. We used this hydrogen sensor device to develop a battery-powered all-in-one wireless hydrogen sensor unit for IoT applications.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"9 1","pages":"63-64"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82585455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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