Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510620
Hideyuki Tomizawa, Y. Kurui, I. Akita, Akira Fujimoto, Tomohiro Saito, A. Kojima, H. Shibata
In this paper, for the first time we demonstrate the material benefits of SiGe for MEMS applications based on the results of fabricated devices. To achieve SiGe inertial MEMS, we develop the deposition process for thick, low-temperature poly-SiGe film with which film stress is controlled precisely, and fabricate SiGe accelerometers having 20µm thickness. We clarify that the SiGe accelerometer shows higher sensor sensitivity and lower power consumption compared to Si one and is thus suitable for future ultra-low-power sensors.
{"title":"High-sensitivity and low-power inertial MEMS-on-CMOS sensors using low-temperature-deposited poly-SiGe film for the IoT era","authors":"Hideyuki Tomizawa, Y. Kurui, I. Akita, Akira Fujimoto, Tomohiro Saito, A. Kojima, H. Shibata","doi":"10.1109/VLSIT.2018.8510620","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510620","url":null,"abstract":"In this paper, for the first time we demonstrate the material benefits of SiGe for MEMS applications based on the results of fabricated devices. To achieve SiGe inertial MEMS, we develop the deposition process for thick, low-temperature poly-SiGe film with which film stress is controlled precisely, and fabricate SiGe accelerometers having 20µm thickness. We clarify that the SiGe accelerometer shows higher sensor sensitivity and lower power consumption compared to Si one and is thus suitable for future ultra-low-power sensors.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"221 1","pages":"41-42"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86178757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510631
C. Zota, C. Convertino, V. Deshpande, T. Merkle, M. Sousa, D. Caimi, L. Czomomaz
We demonstrate scaled InGaAs-on-insulator FinFETs and planar MOSFETs on Si substrate for low power logic and RF applications. This Si-CMOS compatible technology implements SiNx source-drain spacers and doped extensions for reduced overlap capacitances. FinFETs with performance for logic applications matching state-of-the-art are demonstrated. Simultaneously, ft and fmax of 400 and 100 GHz are achieved respectively, the highest reported ft for a III-V MOSFET on Si. Finally, we explore the use of an extended gate line to reduce gate resistance, offering balanced ft/fmax of 215/300 GHz, the first report of III-V RF devices on Si matching state of the art Si-CMOS.
{"title":"InGaAs-on-Insulator MOSFETs Featuring Scaled Logic Devices and Record RF Performance","authors":"C. Zota, C. Convertino, V. Deshpande, T. Merkle, M. Sousa, D. Caimi, L. Czomomaz","doi":"10.1109/VLSIT.2018.8510631","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510631","url":null,"abstract":"We demonstrate scaled InGaAs-on-insulator FinFETs and planar MOSFETs on Si substrate for low power logic and RF applications. This Si-CMOS compatible technology implements SiNx source-drain spacers and doped extensions for reduced overlap capacitances. FinFETs with performance for logic applications matching state-of-the-art are demonstrated. Simultaneously, ft and fmax of 400 and 100 GHz are achieved respectively, the highest reported ft for a III-V MOSFET on Si. Finally, we explore the use of an extended gate line to reduce gate resistance, offering balanced ft/fmax of 215/300 GHz, the first report of III-V RF devices on Si matching state of the art Si-CMOS.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"165-166"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73117548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510689
Zizhen Jiang, S. Qin, Haitong Li, S. Fujii, Dongjin Lee, S. Wong, H. Wong
Selector requirements for tera-bit class, ultra-high-density 3D vertical resistive random access memory (VRRAM) are presented, including practical design considerations such as array efficiency (AE), pillar driver transistors (pillar drivers), and wire/metal plane resistances. We design a novel chip architecture that is different from 3D NAND: (a) separated, square and large wordplane (WP) connected by global wordplane connections (WPC) within a block to minimize influence of leakage currents, (b) compact staircase. An accurate, computationally efficient resistor network is developed to model the parasitic resistances of the architecture. Through the resistor network simulations, selector requirements for 3D VRRAM are examined. To achieve tera-bit class 3D VRRAM with density higher than the most advanced 3D NAND flash (> 4.3 Gb/mm2), selector nonlinearity (NL) ≥ 102 is required.
{"title":"Selector Requirements for Tera-Bit Ultra-High-Density 3D Vertical RRAM","authors":"Zizhen Jiang, S. Qin, Haitong Li, S. Fujii, Dongjin Lee, S. Wong, H. Wong","doi":"10.1109/VLSIT.2018.8510689","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510689","url":null,"abstract":"Selector requirements for tera-bit class, ultra-high-density 3D vertical resistive random access memory (VRRAM) are presented, including practical design considerations such as array efficiency (AE), pillar driver transistors (pillar drivers), and wire/metal plane resistances. We design a novel chip architecture that is different from 3D NAND: (a) separated, square and large wordplane (WP) connected by global wordplane connections (WPC) within a block to minimize influence of leakage currents, (b) compact staircase. An accurate, computationally efficient resistor network is developed to model the parasitic resistances of the architecture. Through the resistor network simulations, selector requirements for 3D VRRAM are examined. To achieve tera-bit class 3D VRRAM with density higher than the most advanced 3D NAND flash (> 4.3 Gb/mm2), selector nonlinearity (NL) ≥ 102 is required.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"31 1","pages":"107-108"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75004821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510684
P. Kuo, Chien-Min Chang, Po-Tsun Liu
Amorphous indium tungsten oxide (a-IWO) nano-sheet (NS) junctionless (JL) transistors (a-IWO NS-JLTs) have been successfully fabricated and demonstrated in the category of indium oxide based thin film transistors (TFTs). We have scaled down thickness of a-IWO channel to 4nm. The proposed a-IWO NS-JLTs with low operation voltages exhibit good electrical characteristics: near ideal peak subthreshold swing (S.S.) ~ 63mV/dec., high field-effect mobility (μFE) ~ 25.3 cm2/V-s. The novel a-IWO NS-JLTs with low temperature processes are promising candidates for monolithic three-dimensional integrated circuits (3-D ICs), vertical stacked (VS) hybrid CMOS technology, and large-scale integration (LSI) applications in the future.
{"title":"Low Thermal Budget Amorphous Indium Tungsten Oxide Nano-Sheet Junctionless Transistors with Near Ideal Subthreshold Swing","authors":"P. Kuo, Chien-Min Chang, Po-Tsun Liu","doi":"10.1109/VLSIT.2018.8510684","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510684","url":null,"abstract":"Amorphous indium tungsten oxide (a-IWO) nano-sheet (NS) junctionless (JL) transistors (a-IWO NS-JLTs) have been successfully fabricated and demonstrated in the category of indium oxide based thin film transistors (TFTs). We have scaled down thickness of a-IWO channel to 4nm. The proposed a-IWO NS-JLTs with low operation voltages exhibit good electrical characteristics: near ideal peak subthreshold swing (S.S.) ~ 63mV/dec., high field-effect mobility (μFE) ~ 25.3 cm2/V-s. The novel a-IWO NS-JLTs with low temperature processes are promising candidates for monolithic three-dimensional integrated circuits (3-D ICs), vertical stacked (VS) hybrid CMOS technology, and large-scale integration (LSI) applications in the future.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"31 1","pages":"21-22"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74440027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510630
Seong Jun Yoon, Kwanyong Pak, Hyun Jun Ahn, A. Yoon, S. Im, Byung Jin Cho
A selective pore-sealing of highly porous ultralow-k (pULK) dielectrics by a cyclic initiated CVD (iCVD) process has been successfully developed. A negligible increase of the pULK thickness and the k value was achieved even after the hermetic pore-sealing. The pore-sealed pULK films show low leakage current and excellent dielectric reliability, comparable to the commercialized low-k dielectric. The selective pore-sealing process does not deposit the pore-sealing layer on Cu surface. The porosity difference between pULK and Cu surfaces is attributed to the origin of the selectivity in the cyclic iCVD process.
{"title":"Selective Pore-Sealing of Highly Porous Ultralow-k dielectrics for ULSI Interconnects by Cyclic Initiated Chemical Vapor Deposition Process","authors":"Seong Jun Yoon, Kwanyong Pak, Hyun Jun Ahn, A. Yoon, S. Im, Byung Jin Cho","doi":"10.1109/VLSIT.2018.8510630","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510630","url":null,"abstract":"A selective pore-sealing of highly porous ultralow-k (pULK) dielectrics by a cyclic initiated CVD (iCVD) process has been successfully developed. A negligible increase of the pULK thickness and the k value was achieved even after the hermetic pore-sealing. The pore-sealed pULK films show low leakage current and excellent dielectric reliability, comparable to the commercialized low-k dielectric. The selective pore-sealing process does not deposit the pore-sealing layer on Cu surface. The porosity difference between pULK and Cu surfaces is attributed to the origin of the selectivity in the cyclic iCVD process.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"16 1","pages":"73-74"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81317086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510660
Ho-Jung Kang, Nagyong Choi, Dong Hwan Lee, Tackhwi Lee, Sungyong Chung, J. Bae, Byung-Gook Park, Jong-Ho Lee
A new space program (PGM) scheme is proposed to achieve reliable triple-level-cell (TLC) 3-D NAND flash memory. Considering the lateral diffusion issue of stored electrons in the nitride storage layer, the proposed scheme stores electrons in the nitride layer of the space region between adjacent cells to suppress the lateral movement of trapped electrons in the programmed target cells. The effect of the space PGM can be sustained until 104 s at 90 °C and up to 1k read cycles at 25 °C. The programmed space region of the nitride layer improves the retention characteristics of the cells in the PGM state by 40% and remarkably reduces the Vth redistribution.
{"title":"Space Program Scheme for 3-D NAND Flash Memory Specialized for the TLC Design","authors":"Ho-Jung Kang, Nagyong Choi, Dong Hwan Lee, Tackhwi Lee, Sungyong Chung, J. Bae, Byung-Gook Park, Jong-Ho Lee","doi":"10.1109/VLSIT.2018.8510660","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510660","url":null,"abstract":"A new space program (PGM) scheme is proposed to achieve reliable triple-level-cell (TLC) 3-D NAND flash memory. Considering the lateral diffusion issue of stored electrons in the nitride storage layer, the proposed scheme stores electrons in the nitride layer of the space region between adjacent cells to suppress the lateral movement of trapped electrons in the programmed target cells. The effect of the space PGM can be sustained until 104 s at 90 °C and up to 1k read cycles at 25 °C. The programmed space region of the nitride layer improves the retention characteristics of the cells in the PGM state by 40% and remarkably reduces the Vth redistribution.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"14 1","pages":"201-202"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81711966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510639
G. Tsutsui, C. Durfee, Miaomiao Wang, A. Konar, Heng Wu, S. Mochizuki, R. Bao, S. Bedell, Juntao Li, Huimei Zhou, D. Schmidt, Chun Ju Yang, J. Kelly, Koji Watanabe, T. Levin, W. Kleemeier, D. Guo, D. Sadana, D. Gupta, A. Knorr, H. Bu
Leakage in Si/SiGe CMOS FinFET is examined. Si cap passivation effectively improves SiGe pFET Dit, subthreshold slope, and mobility, which improves pFET DC performance by 20%. SiGe GIDL is higher than Si by a factor of 9, though GIDL is limited to 50pA/um. SiGe GIDL reduction knobs to meet Si counterpart are demonstrated. The results open the door to the next stage of Si/SiGe CMOS FinFET such as low power and low leakage applications.
研究了Si/SiGe CMOS FinFET的泄漏。Si帽钝化有效地改善了SiGe pet Dit、亚阈值斜率和迁移率，使pet直流性能提高了20%。SiGe GIDL比Si高9倍，但GIDL限制在50pA/um。SiGe GIDL减少旋钮，以满足Si对应的演示。该结果为Si/SiGe CMOS FinFET的下一阶段打开了大门，例如低功耗和低泄漏应用。
{"title":"Leakage aware Si/SiGe CMOS FinFET for low power applications","authors":"G. Tsutsui, C. Durfee, Miaomiao Wang, A. Konar, Heng Wu, S. Mochizuki, R. Bao, S. Bedell, Juntao Li, Huimei Zhou, D. Schmidt, Chun Ju Yang, J. Kelly, Koji Watanabe, T. Levin, W. Kleemeier, D. Guo, D. Sadana, D. Gupta, A. Knorr, H. Bu","doi":"10.1109/VLSIT.2018.8510639","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510639","url":null,"abstract":"Leakage in Si/SiGe CMOS FinFET is examined. Si cap passivation effectively improves SiGe pFET Dit, subthreshold slope, and mobility, which improves pFET DC performance by 20%. SiGe GIDL is higher than Si by a factor of 9, though GIDL is limited to 50pA/um. SiGe GIDL reduction knobs to meet Si counterpart are demonstrated. The results open the door to the next stage of Si/SiGe CMOS FinFET such as low power and low leakage applications.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"9 1","pages":"87-88"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90140335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510659
M. Tomita, S. Oba, Y. Himeda, R. Yamato, K. Shima, T. Kumada, M. Xu, H. Takezawa, K. Mesaki, K. Tsuda, S. Hashimoto, T. Zhan, H. Zhang, Y. Kamakura, Y. Suzuki, H. Inokawa, H. Ikeda, T. Matsukawa, T. Matsuki, T. Watanabe
A best benchmark of Si-nanowire (NW) thermoelectric (TE) power generator has been achieved by our proposed planar device architecture compatible with CMOS process technology. The TE power density corresponds to 12 μW/cm2, which is recorded at an externally applied temperature difference of only 5 K. The demonstration opens up a pathway to cost effective autonomous internet of things (IoT) application utilizing environmental and body heats.
{"title":"10μW/cm2-Class High Power Density Planar Si-Nanowire Thermoelectric Energy Harvester Compatible with CMOS-VLSI Technology","authors":"M. Tomita, S. Oba, Y. Himeda, R. Yamato, K. Shima, T. Kumada, M. Xu, H. Takezawa, K. Mesaki, K. Tsuda, S. Hashimoto, T. Zhan, H. Zhang, Y. Kamakura, Y. Suzuki, H. Inokawa, H. Ikeda, T. Matsukawa, T. Matsuki, T. Watanabe","doi":"10.1109/VLSIT.2018.8510659","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510659","url":null,"abstract":"A best benchmark of Si-nanowire (NW) thermoelectric (TE) power generator has been achieved by our proposed planar device architecture compatible with CMOS process technology. The TE power density corresponds to 12 μW/cm2, which is recorded at an externally applied temperature difference of only 5 K. The demonstration opens up a pathway to cost effective autonomous internet of things (IoT) application utilizing environmental and body heats.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"7 1","pages":"93-94"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88829257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510664
W. Chang, T. Irisawa, H. Ishii, H. Hattori, N. Uchida, T. Maeda
Advanced channel formation technologies, such as precise control of GeOI body thickness (Tbody), surface roughness and interfacial quality, utilizing Si-passivation/Ge-channel/SiGe hetero-epitaxy and Ge digital etching (DE) techniques were implemented for UTB GeOI structure. Si passivation for Ge/BOX interface has been verified to suppress Coulomb scattering owing to better interfacial quality. Insertion of SiGe etching stop (ES) layer and dozens DE (DDE) were found to be quite effective to reduce Tbody fluctuation as well as surface roughness, resulting in the significant improvement of mobility. As a result, we have demonstrated record high hole mobility of ~200 cm2/Vs in UTB GeOI pMOSFETs without the strain technology, which outperforms Si universal mobility by 2 times even under Tbody of 9 nm.
{"title":"Significant Performance Enhancement of UTB GeOI pMOSFETs by Advanced Channel Formation Technologies","authors":"W. Chang, T. Irisawa, H. Ishii, H. Hattori, N. Uchida, T. Maeda","doi":"10.1109/VLSIT.2018.8510664","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510664","url":null,"abstract":"Advanced channel formation technologies, such as precise control of GeOI body thickness (Tbody), surface roughness and interfacial quality, utilizing Si-passivation/Ge-channel/SiGe hetero-epitaxy and Ge digital etching (DE) techniques were implemented for UTB GeOI structure. Si passivation for Ge/BOX interface has been verified to suppress Coulomb scattering owing to better interfacial quality. Insertion of SiGe etching stop (ES) layer and dozens DE (DDE) were found to be quite effective to reduce Tbody fluctuation as well as surface roughness, resulting in the significant improvement of mobility. As a result, we have demonstrated record high hole mobility of ~200 cm2/Vs in UTB GeOI pMOSFETs without the strain technology, which outperforms Si universal mobility by 2 times even under Tbody of 9 nm.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"191-192"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91515532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
TiN/ferroelectric-HfZrOx (HZO)/epi-SiGe (MFS) structure was employed as the platform to investigate the dependence of Ge content on reliability performance and the mechanism behind it. As compared to Si counterpart, HZO on Si0.56Ge0.44 exhibits not only enhanced remnant polarization (Pr) by 58 % but much improved reliability in terms of negligible Pr degradation up to 109 cycles under ±4 V/100k Hz bipolar AC stress, desirable retention at pristine and cycled state up to 104 sec, and smaller imprint effect against time at 85 °C. The Ge content-dependent reliability performance is mainly due to the thinner sub-oxide interfacial layer (IL) with better quality since it is too thin to trap charges while less vulnerable to defect generation due to stronger bonding (fewer Vo). IL with higher κ value is also helpful to suppress E-field across it, beneficial to enhance reliability. The results suggest that as the technology advances into SiGe platform, it is more viable for MFS-based memory as the reliability issues for Si will be greatly mitigated.
{"title":"Dependence of Reliability of Ferroelectric HfZrOx on Epitaxial SiGe Film with Various Ge Content","authors":"Kuen-Yi Chen, Yen-Hua Huang, Ruei-Wen Kao, Yan-Xiao Lin, Yung-Hsien Wu","doi":"10.1109/VLSIT.2018.8510643","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510643","url":null,"abstract":"TiN/ferroelectric-HfZrOx (HZO)/epi-SiGe (MFS) structure was employed as the platform to investigate the dependence of Ge content on reliability performance and the mechanism behind it. As compared to Si counterpart, HZO on Si0.56Ge0.44 exhibits not only enhanced remnant polarization (Pr) by 58 % but much improved reliability in terms of negligible Pr degradation up to 109 cycles under ±4 V/100k Hz bipolar AC stress, desirable retention at pristine and cycled state up to 104 sec, and smaller imprint effect against time at 85 °C. The Ge content-dependent reliability performance is mainly due to the thinner sub-oxide interfacial layer (IL) with better quality since it is too thin to trap charges while less vulnerable to defect generation due to stronger bonding (fewer Vo). IL with higher κ value is also helpful to suppress E-field across it, beneficial to enhance reliability. The results suggest that as the technology advances into SiGe platform, it is more viable for MFS-based memory as the reliability issues for Si will be greatly mitigated.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"338 1","pages":"119-120"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74983271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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