Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510701
Jhih-Yang Yan, Chia-Che Chung, Sun-Rong Jan, H. H. Lin, W. K. Wan, M. Yang, C. Liu
Thermal SPICE modeling with distributed Rth-Cth network is proposed to provide more accurate AC self-heating (SH) results than two τc and one τc models. The thermal time constant of the hotspot (τhotspot) in FinFETs is frequency dependent, not a constant. The severe SH by boundary/alloy scattering and interfacial thermal resistance (ITR) is included in our SPICE. The modularized components of fins, metals, and IMDs provide device and routing flexibility, without additional FEM simulation. ITR of Si80Ge20/Si1-xGex is calculated by AMM model as the lower bound for SiGe FinFETs. The intrinsic electromigration (EM) improvement of Co interconnect (5X) is countervailed (5X→2.44X) by the increasing Tmetal due to the low thermal conductivity of Co. Different V2 placements on the power line of a ring oscillator (RO) are proposed to lower both the Tj (FinFET) and Tmetal. The predicted EM MTTF of Co interconnect with the additional heat dissipation by V2 insertion is ~5.65X of W/Cu interconnect.
{"title":"Comprehensive Thermal SPICE Modeling of FinFETs and BEOL with Layout Flexibility Considering Frequency Dependent Thermal Time Constant, 3D Heat Flows, Boundary/Alloy Scattering, and Interfacial Thermal Resistance with Circuit Level Reliability Evaluation","authors":"Jhih-Yang Yan, Chia-Che Chung, Sun-Rong Jan, H. H. Lin, W. K. Wan, M. Yang, C. Liu","doi":"10.1109/VLSIT.2018.8510701","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510701","url":null,"abstract":"Thermal SPICE modeling with distributed R<inf>th</inf>-C<inf>th</inf> network is proposed to provide more accurate AC self-heating (SH) results than two τ<inf>c</inf> and one τ<inf>c</inf> models. The thermal time constant of the hotspot (τhotspot) in FinFETs is frequency dependent, not a constant. The severe SH by boundary/alloy scattering and interfacial thermal resistance (ITR) is included in our SPICE. The modularized components of fins, metals, and IMDs provide device and routing flexibility, without additional FEM simulation. ITR of Si<inf>80</inf>Ge<inf>20</inf>/Si<inf>1-</inf>xGe<inf>x</inf> is calculated by AMM model as the lower bound for SiGe FinFETs. The intrinsic electromigration (EM) improvement of Co interconnect (5X) is countervailed (5X→2.44X) by the increasing T<inf>metal</inf> due to the low thermal conductivity of Co. Different V2 placements on the power line of a ring oscillator (RO) are proposed to lower both the T<inf>j</inf> (FinFET) and T<inf>metal</inf>. The predicted EM MTTF of Co interconnect with the additional heat dissipation by V2 insertion is ~5.65X of W/Cu interconnect.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"54 1","pages":"113-114"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80046459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510642
L. Xue, C. Ching, A. Kontos, Jaesoo Ahn, Xiaodong Wang, R. Whig, H. Tseng, J. Howarth, S. Hassan, Hao Chen, M. Bangar, S. Liang, Rongjun Wang, M. Pakala
This paper demonstrates systematic process optimization of perpendicular magnetic tunnel junction (pMTJ) by hardware, unit-process, and material stack design. TMR of 200% at RA 5 Ohm•µm2, HSAF ~ 8 kOe, and 10-time tunability of Hc were achieved at the film level. After patterning, 10−6 write error rate was reached at 0.4 pJ, VBD was as high as 1600 mV at 20 ns pulse width, and excellent device stability against 400°C BEOL baking was demonstrated. The device performance along with the process capability to make MTJ array at 88 nm pitch provides opportunities for LLC applications.
{"title":"Process Optimization of Perpendicular Magnetic Tunnel Junction Arrays for Last-Level Cache beyond 7 nm Node","authors":"L. Xue, C. Ching, A. Kontos, Jaesoo Ahn, Xiaodong Wang, R. Whig, H. Tseng, J. Howarth, S. Hassan, Hao Chen, M. Bangar, S. Liang, Rongjun Wang, M. Pakala","doi":"10.1109/VLSIT.2018.8510642","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510642","url":null,"abstract":"This paper demonstrates systematic process optimization of perpendicular magnetic tunnel junction (pMTJ) by hardware, unit-process, and material stack design. TMR of 200% at RA 5 Ohm•µm<sup>2</sup>, H<inf>SAF</inf> ~ 8 kOe, and 10-time tunability of Hc were achieved at the film level. After patterning, 10<sup>−6</sup> write error rate was reached at 0.4 pJ, V<inf>BD</inf> was as high as 1600 mV at 20 ns pulse width, and excellent device stability against 400°C BEOL baking was demonstrated. The device performance along with the process capability to make MTJ array at 88 nm pitch provides opportunities for LLC applications.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"127 1","pages":"117-118"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90279782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510699
S. Miyano
We are running a cancer clinical sequence system based on whole genome/exome, RNA sequence and epigenome as research. When focused on hematology/oncology, it takes currently four days for a patient from signing informed consent (IC) to diagnosis. This process consists of IC, specimen collection, next-generation sequencer analysis, data analysis, interpretation/translation of mutations, determining the diagnosis combined with all pathological/clinical data and returning the result to the patient. Therapies are not only drugs but also hematopoietic stem cell transplantation. A pipeline Genomon for analyzing cancer genomes and RNA sequences by next-generation sequencers plays one of the key roles. It is running on the supercomputer system at Human Genome Center. The bottleneck of interpretation/translation was drastically resolved by employing IBM Watson for Genomics in harmony with our in-house human curation pipeline. We report how our system works as a conglomerate of oncologists, cancer biologists, bioinformatics experts augmented with Watson and Genomon.
我们正在运行一个基于全基因组/外显子组、RNA序列和表观基因组的癌症临床序列系统作为研究。在血液学/肿瘤学方面，目前患者从签署知情同意(IC)到诊断需要4天时间。该过程包括IC，标本收集，下一代测序仪分析，数据分析，突变解释/翻译，结合所有病理/临床数据确定诊断并将结果返回给患者。治疗方法不仅是药物，还包括造血干细胞移植。通过下一代测序仪分析癌症基因组和RNA序列的Genomon流水线发挥了关键作用之一。它在人类基因组中心的超级计算机系统上运行。通过采用IBM Watson for Genomics与我们内部的人工管理管道相协调，口译/翻译的瓶颈得到了彻底解决。我们报告我们的系统是如何工作的，作为一个由肿瘤学家、癌症生物学家、生物信息学专家组成的集团，辅以沃森和Genomon。
{"title":"Revolutionizing Cancer Genomic Medicine by AI and Supercomputer with Big Data","authors":"S. Miyano","doi":"10.1109/VLSIT.2018.8510699","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510699","url":null,"abstract":"We are running a cancer clinical sequence system based on whole genome/exome, RNA sequence and epigenome as research. When focused on hematology/oncology, it takes currently four days for a patient from signing informed consent (IC) to diagnosis. This process consists of IC, specimen collection, next-generation sequencer analysis, data analysis, interpretation/translation of mutations, determining the diagnosis combined with all pathological/clinical data and returning the result to the patient. Therapies are not only drugs but also hematopoietic stem cell transplantation. A pipeline Genomon for analyzing cancer genomes and RNA sequences by next-generation sequencers plays one of the key roles. It is running on the supercomputer system at Human Genome Center. The bottleneck of interpretation/translation was drastically resolved by employing IBM Watson for Genomics in harmony with our in-house human curation pipeline. We report how our system works as a conglomerate of oncologists, cancer biologists, bioinformatics experts augmented with Watson and Genomon.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"59 1","pages":"7-11"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91012251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510645
E. Capogreco, L. Witters, H. Arimura, F. Sebaai, C. Porret, A. Hikavyy, R. Loo, A. Milenin, G. Eneman, P. Favia, H. Bender, K. Wostyn, E. Litta, A. Schulze, C. Vrancken, A. Opdebeeck, J. Mitard, R. Langer, F. Holsteyns, N. Waldron, K. Barla, V. De Heyn, D. Mocuta, N. Collaert
This paper reports on strained p-type Ge Gate-All-Around (GAA) devices on 300mm SiGe Strain-Relaxed-Buffers (SRB) with improved performance as compared to our previous work. The Q factor is increased to 25, Ion=500μA/μm at Ioff=100nA/μm is achieved, approaching the best published results on Ge finFETs. Good NBTI reliability is also maintained. By using the process flow developed for the single nanowire (NW), vertically stacked strained Ge NWs featuring 8nm channel diameter are demonstrated for the first time. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs, demonstrating for the first time 1.7GPa uniaxial-stress along the Ge wire, which originates from the lattice mismatch between the Ge S/D and the Si0.3Ge0.7 SRB.
{"title":"First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs","authors":"E. Capogreco, L. Witters, H. Arimura, F. Sebaai, C. Porret, A. Hikavyy, R. Loo, A. Milenin, G. Eneman, P. Favia, H. Bender, K. Wostyn, E. Litta, A. Schulze, C. Vrancken, A. Opdebeeck, J. Mitard, R. Langer, F. Holsteyns, N. Waldron, K. Barla, V. De Heyn, D. Mocuta, N. Collaert","doi":"10.1109/VLSIT.2018.8510645","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510645","url":null,"abstract":"This paper reports on strained p-type Ge Gate-All-Around (GAA) devices on 300mm SiGe Strain-Relaxed-Buffers (SRB) with improved performance as compared to our previous work. The Q factor is increased to 25, Ion=500μA/μm at Ioff=100nA/μm is achieved, approaching the best published results on Ge finFETs. Good NBTI reliability is also maintained. By using the process flow developed for the single nanowire (NW), vertically stacked strained Ge NWs featuring 8nm channel diameter are demonstrated for the first time. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs, demonstrating for the first time 1.7GPa uniaxial-stress along the Ge wire, which originates from the lattice mismatch between the Ge S/D and the Si0.3Ge0.7 SRB.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"92 6 1","pages":"193-194"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83453261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510633
M. Bardon, Y. Sherazi, D. Jang, D. Yakimets, P. Schuddinck, R. Baert, H. Mertens, L. Mattii, B. Parvais, A. Mocuta, D. Verkest
In this paper, the performance of standard cells scaled down to 4.5 metal tracks based on Lateral NanoSheets is investigated for 3nm technology node targets using relevant logic benchmarks and power-aware metrics. The cell layout and parasitics in 4.5T cells set strong constraints on the NanoSheets geometry. The optimized NanoSheets could still outperform FinFETs by 9 to 20% frequency depending on circuit context, reaching 3nm node targets. An extra 21% performance improvement is expected with device level boosters enablement.
{"title":"Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells","authors":"M. Bardon, Y. Sherazi, D. Jang, D. Yakimets, P. Schuddinck, R. Baert, H. Mertens, L. Mattii, B. Parvais, A. Mocuta, D. Verkest","doi":"10.1109/VLSIT.2018.8510633","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510633","url":null,"abstract":"In this paper, the performance of standard cells scaled down to 4.5 metal tracks based on Lateral NanoSheets is investigated for 3nm technology node targets using relevant logic benchmarks and power-aware metrics. The cell layout and parasitics in 4.5T cells set strong constraints on the NanoSheets geometry. The optimized NanoSheets could still outperform FinFETs by 9 to 20% frequency depending on circuit context, reaching 3nm node targets. An extra 21% performance improvement is expected with device level boosters enablement.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"41 1","pages":"143-144"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89308073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510638
Chen Zhou, R. Wong, S. Wen, C. Kim
A 65nm test chip to study electromigration (EM) effects in power grids was taped-out and tested. A 9×9 grid was implemented using M3 and M4 metal layers which was stressed under constant current and constant voltage modes. On-chip poly heaters were employed to raise the die temperature to 350°C without damaging the chip package. A bank of transmission gates based on IO transistors were used to tap out the M3 and M4 voltages at each intersection point of the power grid. Using the test structure, we could observe for the first time, subtle behaviors of EM such as mechanical stress dependent failure locations and self-healing due to redundant current paths.
{"title":"Electromigration Effects in Power Grids Characterized Using an On-Chip Test Structure with Poly Heaters and Voltage Tapping Points","authors":"Chen Zhou, R. Wong, S. Wen, C. Kim","doi":"10.1109/VLSIT.2018.8510638","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510638","url":null,"abstract":"A 65nm test chip to study electromigration (EM) effects in power grids was taped-out and tested. A 9×9 grid was implemented using M3 and M4 metal layers which was stressed under constant current and constant voltage modes. On-chip poly heaters were employed to raise the die temperature to 350°C without damaging the chip package. A bank of transmission gates based on IO transistors were used to tap out the M3 and M4 voltages at each intersection point of the power grid. Using the test structure, we could observe for the first time, subtle behaviors of EM such as mechanical stress dependent failure locations and self-healing due to redundant current paths.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"17 1","pages":"19-20"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83366050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510705
A. Vandooren, J. Franco, B. Parvais, Z. Wu, L. Witters, A. Walke, W. Li, L. Peng, V. Desphande, F. M. Bufler, N. Rassoul, G. Hellings, G. Jamieson, F. Inoue, G. Verbinnen, K. Devriendt, L. Teugels, N. Heylen, E. Vecchio, T. Zheng, E. Rosseel, W. Vanherle, A. Hikavyy, B. Chan, R. Ritzenthaler, G. Besnard, W. Schwarzenbach, G. Gaudin, I. Radu, B. Nguyen, N. Waldron, V. D. Heyn, D. Mocuta, N. Collaert
3D sequential integration requires top MOSFETs processed at low thermal budget, which can impair the device reliability. In this work, top junction-less device are fabricated with a maximum processing temperature of 525°C. The devices feature high k /metal replacement gate and low temperature Si:P and SiGe:B 60% raised SD for NMOS and PMOS respectively. Device matching, analog and RF performance of the top tier devices are in-line with state-of-the-art Si technology processed at high temperature (>1000°C). The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding.
{"title":"3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability","authors":"A. Vandooren, J. Franco, B. Parvais, Z. Wu, L. Witters, A. Walke, W. Li, L. Peng, V. Desphande, F. M. Bufler, N. Rassoul, G. Hellings, G. Jamieson, F. Inoue, G. Verbinnen, K. Devriendt, L. Teugels, N. Heylen, E. Vecchio, T. Zheng, E. Rosseel, W. Vanherle, A. Hikavyy, B. Chan, R. Ritzenthaler, G. Besnard, W. Schwarzenbach, G. Gaudin, I. Radu, B. Nguyen, N. Waldron, V. D. Heyn, D. Mocuta, N. Collaert","doi":"10.1109/VLSIT.2018.8510705","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510705","url":null,"abstract":"3D sequential integration requires top MOSFETs processed at low thermal budget, which can impair the device reliability. In this work, top junction-less device are fabricated with a maximum processing temperature of 525°C. The devices feature high k /metal replacement gate and low temperature Si:P and SiGe:B 60% raised SD for NMOS and PMOS respectively. Device matching, analog and RF performance of the top tier devices are in-line with state-of-the-art Si technology processed at high temperature (>1000°C). The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"69-70"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84117308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-01-01DOI: 10.1109/VLSIT.2018.8510695
P. Liao, M. Kuo, C. Tien, Y. -. Chang, P. Hong, T. George, H. Lin, P. W. Li
We report the first-of-its-kind, self-organized gate stack of Ge nanosphere (NP) gate/SiO2/Si1-xGex channel fabricated in a single oxidation step. Process-controlled tunability of the Ge NP size (5–90nm), SiO2 thickness (2–4nm), and Ge content (x = 0.65–0.85) and strain engineering (εcomp = 1–3%) of the Si1-xGex are achieved. We demonstrated Ge junctionless (JL) n-FETs and photoMOSFETs (PTs) as amplifier and photodetector, respectively, for Ge receivers. LG of 75nm JL n-FETs feature ION/IOFF > 5×108, ION > 500µA/µm at VDS = 1V, T= 80K. Ge-PTs exhibit superior photoresponsivity >1,000A/W and current gain linearity ranging from nW–mW for 850nm illumination. Size-tunable photo-luminescence (PL) of 300–1600nm (NUV-NIR) are observed on 5–100nm Ge NPs. Our gate stack of Ge NP/SiO2/Si1-xGex enables a practically achievable building block for monolithically-integrated Ge electronic and photonic ICs (EPICs) on Si.
{"title":"Self-organized gate stack of Ge nanosphere/SiO2/Si1-xGex enables Ge-based monolithically-integrated electronics and photonics on Si platform","authors":"P. Liao, M. Kuo, C. Tien, Y. -. Chang, P. Hong, T. George, H. Lin, P. W. Li","doi":"10.1109/VLSIT.2018.8510695","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510695","url":null,"abstract":"We report the first-of-its-kind, self-organized gate stack of Ge nanosphere (NP) gate/SiO<inf>2</inf>/Si<inf>1-x</inf>Ge<inf>x</inf> channel fabricated in a single oxidation step. Process-controlled tunability of the Ge NP size (5–90nm), SiO<inf>2</inf> thickness (2–4nm), and Ge content (x = 0.65–0.85) and strain engineering (ε<inf>comp</inf> = 1–3%) of the Si<inf>1-x</inf>Ge<inf>x</inf> are achieved. We demonstrated Ge junctionless (JL) n-FETs and photoMOSFETs (PTs) as amplifier and photodetector, respectively, for Ge receivers. L<inf>G</inf> of 75nm JL n-FETs feature I<inf>ON</inf>/I<inf>OFF</inf> > 5×10<sup>8</sup>, I<inf>ON</inf> > 500µA/µm at V<inf>DS</inf> = 1V, T= 80K. Ge-PTs exhibit superior photoresponsivity >1,000A/W and current gain linearity ranging from nW–mW for 850nm illumination. Size-tunable photo-luminescence (PL) of 300–1600nm (NUV-NIR) are observed on 5–100nm Ge NPs. Our gate stack of Ge NP/SiO<inf>2</inf>/Si<inf>1-x</inf>Ge<inf>x</inf> enables a practically achievable building block for monolithically-integrated Ge electronic and photonic ICs (EPICs) on Si.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"520 1","pages":"157-158"},"PeriodicalIF":0.0,"publicationDate":"2018-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77059602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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