Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510657
H. Sagong, K. Choi, J. Kim, T. Jeong, M. Choe, H. Shim, W. Kim, J. Park, S. Shin, S. Pae
We report the characterization and modeling of FinFET self-heating (FSH) and its reliability impact across multiple FinFET process technology generations. With technology node scaling, taller and narrower Fin shape allows higher performance. However, increased FSH and potential reliability issues must be well understood and mitigated. This paper presents FSH effects across multiple technology nodes and characterization, and modeling efforts used in design will be presented. The results on transistor and product level demonstrate excellent reliability performance beyond 10yrs
{"title":"Modeling of FinFET Self-Heating Effects in multiple FinFET Technology Generations with implication for Transistor and Product Reliability","authors":"H. Sagong, K. Choi, J. Kim, T. Jeong, M. Choe, H. Shim, W. Kim, J. Park, S. Shin, S. Pae","doi":"10.1109/VLSIT.2018.8510657","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510657","url":null,"abstract":"We report the characterization and modeling of FinFET self-heating (FSH) and its reliability impact across multiple FinFET process technology generations. With technology node scaling, taller and narrower Fin shape allows higher performance. However, increased FSH and potential reliability issues must be well understood and mitigated. This paper presents FSH effects across multiple technology nodes and characterization, and modeling efforts used in design will be presented. The results on transistor and product level demonstrate excellent reliability performance beyond 10yrs","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"11 1","pages":"121-122"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75165987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510675
J. Kye, Hoonki Kim, J. Lim, Seungyoung Lee, Jonghoon Jung, T. Song
Because of the complexity of technology the level of engagement between technology and design has been increased more than ever before. Design technology co-optimization (DTCO) is used to describe the process of making with competitive power, performance, area, and yield (PPAY) in various applications. This paper describes smart scaling technologies for advanced FinFET node to make technology more competitive.
{"title":"Smart scaling technology for advanced FinFET node","authors":"J. Kye, Hoonki Kim, J. Lim, Seungyoung Lee, Jonghoon Jung, T. Song","doi":"10.1109/VLSIT.2018.8510675","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510675","url":null,"abstract":"Because of the complexity of technology the level of engagement between technology and design has been increased more than ever before. Design technology co-optimization (DTCO) is used to describe the process of making with competitive power, performance, area, and yield (PPAY) in various applications. This paper describes smart scaling technologies for advanced FinFET node to make technology more competitive.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"119 1","pages":"149-150"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74289330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510650
R. Bao, R. Southwick, H. Zhou, C. Lee, B. Linder, T. Ando, D. Guo, H. Jagannathan, V. Narayanan
We report for the first time that replacement metal gate (RMG) work function metal (WFM) modulates the interface defects in Silicon and SiGe MOSFETs. Changing the effective work function (eWF) towards nFET band edge provides lower interface defects and higher mobility than eWF near the pFET band edge for both Si and SiGe substrates. Reducing the electric field across the dielectric (via eWF) improves bias temperature instability (BTI) for both n & pMOSFETs beyond expectation. Breakdown voltage increases and gate leakage decreases with increasing eWF for both n & pMOSFETs. Therefore, multi-Vt MOSFETs by RMG metal gate exhibit differentiated reliability as well as differentiated performance for both Si and SiGe channel materials.
{"title":"Differentiated Performance and Reliability Enabled by Multi-Work Function Solution in RMG Silicon and SiGe MOSFETs","authors":"R. Bao, R. Southwick, H. Zhou, C. Lee, B. Linder, T. Ando, D. Guo, H. Jagannathan, V. Narayanan","doi":"10.1109/VLSIT.2018.8510650","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510650","url":null,"abstract":"We report for the first time that replacement metal gate (RMG) work function metal (WFM) modulates the interface defects in Silicon and SiGe MOSFETs. Changing the effective work function (eWF) towards nFET band edge provides lower interface defects and higher mobility than eWF near the pFET band edge for both Si and SiGe substrates. Reducing the electric field across the dielectric (via eWF) improves bias temperature instability (BTI) for both n & pMOSFETs beyond expectation. Breakdown voltage increases and gate leakage decreases with increasing eWF for both n & pMOSFETs. Therefore, multi-Vt MOSFETs by RMG metal gate exhibit differentiated reliability as well as differentiated performance for both Si and SiGe channel materials.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"36 1","pages":"115-116"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87436532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510635
R. Delhougne, A. Arreghini, E. Rosseel, A. Hikavyy, E. Vecchio, L. Zhang, M. Pak, L. Nyns, T. Raymaekers, N. Jossart, L. Breuil, S. S. V-Palayam, C. Tan, G. Van den bosch, A. Furnémont
We are demonstrating for the first time epi-based monocrystalline silicon macaroni channel 3-D NAND devices. The highly controllable channel replacement process sequence leads to > 95% yield, with excellent uniformity and reproducibility, proving its potential for manufacturability. The electron mobility of the channel is improved by a factor 30 compared to the polycrystalline macaroni Si channel, together with a reduction of the off state leakage. Furthermore, this channel replacement fabrication process does not affect memory performance and reliability. The performance benefits of this channel replacement technique make it a potential candidate for fabricating future 3-D NAND devices.
{"title":"First demonstration of monocrystalline silicon macaroni channel for 3-D NAND memory devices","authors":"R. Delhougne, A. Arreghini, E. Rosseel, A. Hikavyy, E. Vecchio, L. Zhang, M. Pak, L. Nyns, T. Raymaekers, N. Jossart, L. Breuil, S. S. V-Palayam, C. Tan, G. Van den bosch, A. Furnémont","doi":"10.1109/VLSIT.2018.8510635","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510635","url":null,"abstract":"We are demonstrating for the first time epi-based monocrystalline silicon macaroni channel 3-D NAND devices. The highly controllable channel replacement process sequence leads to > 95% yield, with excellent uniformity and reproducibility, proving its potential for manufacturability. The electron mobility of the channel is improved by a factor 30 compared to the polycrystalline macaroni Si channel, together with a reduction of the off state leakage. Furthermore, this channel replacement fabrication process does not affect memory performance and reliability. The performance benefits of this channel replacement technique make it a potential candidate for fabricating future 3-D NAND devices.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"40 1","pages":"203-204"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76346463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510648
Y. Li, S. Kim, X. Sun, P. Solomon, T. Gokmen, H. Tsai, S. Koswatta, Z. Ren, R. Mo, C. Yeh, W. Haensch, E. Leobandung
We report a capacitor-based cross-point array that can be used to train analog-based Deep Neural Networks (DNNs), fabricated with trench capacitors in 14nm technology. The fundamental DNN functionalities of multiply-accumulate and weight-update are demonstrated. We also demonstrate the best symmetry and linearity ever reported for an analog cross-point array system. For DNNs, the capacitor leakage does not impact learning accuracy even without any refresh cycle, as the weights are continuously updated during training. This makes capacitor an ideal candidate for neural network training. We also discuss the scalability of this array using optimized low-leakage DRAM technology.
{"title":"Capacitor-based Cross-point Array for Analog Neural Network with Record Symmetry and Linearity","authors":"Y. Li, S. Kim, X. Sun, P. Solomon, T. Gokmen, H. Tsai, S. Koswatta, Z. Ren, R. Mo, C. Yeh, W. Haensch, E. Leobandung","doi":"10.1109/VLSIT.2018.8510648","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510648","url":null,"abstract":"We report a capacitor-based cross-point array that can be used to train analog-based Deep Neural Networks (DNNs), fabricated with trench capacitors in 14nm technology. The fundamental DNN functionalities of multiply-accumulate and weight-update are demonstrated. We also demonstrate the best symmetry and linearity ever reported for an analog cross-point array system. For DNNs, the capacitor leakage does not impact learning accuracy even without any refresh cycle, as the weights are continuously updated during training. This makes capacitor an ideal candidate for neural network training. We also discuss the scalability of this array using optimized low-leakage DRAM technology.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"6 1","pages":"25-26"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81987390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510618
J. Ryckaert, P. Schuddinck, P. Weckx, G. Bouche, B. Vincent, J. Smith, Y. Sherazi, A. Mallik, H. Mertens, S. Demuynck, T. H. Bao, A. Veloso, N. Horiguchi, A. Mocuta, D. Mocuta, J. Boemmels
The complementary FET (CFET) device consisting of a stacked n-type vertical sheet on a p-type fin is evaluated in a design-technology co-optimization (DTCO) framework. Through a double level access it offers a structural scaling of both standard cells (SDC) and SRAM by 50%. The proposed process flow requires accurate control of the elevation dimension for manufacturability. Based on TCAD analysis, the CFET can eventually outperform the finFET device and meet the N3 targets in power and performance. To achieve that, the dominating parasitic resistance of the deep vias needs to be reduced by the introduction of advanced MOL contacts featuring thin barriers.
{"title":"The Complementary FET (CFET) for CMOS scaling beyond N3","authors":"J. Ryckaert, P. Schuddinck, P. Weckx, G. Bouche, B. Vincent, J. Smith, Y. Sherazi, A. Mallik, H. Mertens, S. Demuynck, T. H. Bao, A. Veloso, N. Horiguchi, A. Mocuta, D. Mocuta, J. Boemmels","doi":"10.1109/VLSIT.2018.8510618","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510618","url":null,"abstract":"The complementary FET (CFET) device consisting of a stacked n-type vertical sheet on a p-type fin is evaluated in a design-technology co-optimization (DTCO) framework. Through a double level access it offers a structural scaling of both standard cells (SDC) and SRAM by 50%. The proposed process flow requires accurate control of the elevation dimension for manufacturability. Based on TCAD analysis, the CFET can eventually outperform the finFET device and meet the N3 targets in power and performance. To achieve that, the dominating parasitic resistance of the deep vias needs to be reduced by the introduction of advanced MOL contacts featuring thin barriers.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"141-142"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88300642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510649
T. Yajima, T. Nishimura, A. Toriumi
Spike integration and threshold processing are the basic signal processing in brain-inspired computing, such as deep learning, reservoir computing etc. In such processes, analog technology is essential for suppressing energy consumption. However, analog technology often faces problems in miniaturization due to deteriorated noise tolerance by scaling and intrinsically large analog elements such as capacitors. Here, we propose to exploit a thermal degree of freedom in phase transition materials for scalable and noise-tolerant analog spike processing. We focus on a two-terminal metal-insulator-transition VO2 device, where quasi-adiabatic Joule heating enables efficient spike integration, and metal-insulator transition implements threshold processing. This VO2 device is highly scalable, consuming only ~1fJ/spike (smallest so far) according to the simulation. By using this device, fully autonomous spike integration and threshold processing are also demonstrated. Exploiting the quasi-adiabatic thermal degree of freedom will facilitate scalable and energy-efficient analog implementation for a wide range of brain-inspired computing.
{"title":"Analog Spike Processing with High Scalability and Low Energy Consumption Using Thermal Degree of Freedom in Phase Transition Materials","authors":"T. Yajima, T. Nishimura, A. Toriumi","doi":"10.1109/VLSIT.2018.8510649","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510649","url":null,"abstract":"Spike integration and threshold processing are the basic signal processing in brain-inspired computing, such as deep learning, reservoir computing etc. In such processes, analog technology is essential for suppressing energy consumption. However, analog technology often faces problems in miniaturization due to deteriorated noise tolerance by scaling and intrinsically large analog elements such as capacitors. Here, we propose to exploit a thermal degree of freedom in phase transition materials for scalable and noise-tolerant analog spike processing. We focus on a two-terminal metal-insulator-transition VO2 device, where quasi-adiabatic Joule heating enables efficient spike integration, and metal-insulator transition implements threshold processing. This VO2 device is highly scalable, consuming only ~1fJ/spike (smallest so far) according to the simulation. By using this device, fully autonomous spike integration and threshold processing are also demonstrated. Exploiting the quasi-adiabatic thermal degree of freedom will facilitate scalable and energy-efficient analog implementation for a wide range of brain-inspired computing.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"224 1","pages":"27-28"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77305521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510637
Nuo Xu, Fan Chen, D. Apalkov, Weiyi Qi, Jing Wang, Zhengping Jiang, W. Choi, D. Kim
A rare-failure oriented optimization methodology for state-of-the-art STT-MRAM technology has been proposed. Physics-based device models and novel rare event sampling algorithms are used for massively parallel Monte Carlo simulations to identify the critical process variability sources and to evaluate the Write Error Rate (WER) at the resolution of 1E-9. New rare-failure figure-of-merits (FoMs) and design guidelines are suggested for optimizing the operation conditions of STT-MRAMs so that the energy-delay product can be minimized at satisfactory WER level.
{"title":"Rare-Failure Oriented STT-MRAM Technology Optimization","authors":"Nuo Xu, Fan Chen, D. Apalkov, Weiyi Qi, Jing Wang, Zhengping Jiang, W. Choi, D. Kim","doi":"10.1109/VLSIT.2018.8510637","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510637","url":null,"abstract":"A rare-failure oriented optimization methodology for state-of-the-art STT-MRAM technology has been proposed. Physics-based device models and novel rare event sampling algorithms are used for massively parallel Monte Carlo simulations to identify the critical process variability sources and to evaluate the Write Error Rate (WER) at the resolution of 1E-9. New rare-failure figure-of-merits (FoMs) and design guidelines are suggested for optimizing the operation conditions of STT-MRAMs so that the energy-delay product can be minimized at satisfactory WER level.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"11 1","pages":"187-188"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87957896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510687
Zhewei Jiang, Shihui Yin, Mingoo Seok, Jae-sun Seo
We present an in-memory computing SRAM macro that computes XNOR-and-accumulate in binary/ternary deep neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay product than digital ASIC, and also achieves significantly higher accuracy than prior in-SRAM computing macro (e.g., 98.3% vs. 90% for MNIST) by being able to support the mainstream DNN/CNN algorithms.
我们提出了一个内存计算SRAM宏，它可以在二进制/三元深度神经网络中在位线上计算xnor和累加，而不需要逐行访问数据。它实现了比数字ASIC高33倍的能量和300倍的能量延迟积，并且通过能够支持主流的DNN/CNN算法，也实现了比先前的sram计算宏(例如98.3% vs. MNIST的90%)更高的精度。
{"title":"XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks","authors":"Zhewei Jiang, Shihui Yin, Mingoo Seok, Jae-sun Seo","doi":"10.1109/VLSIT.2018.8510687","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510687","url":null,"abstract":"We present an in-memory computing SRAM macro that computes XNOR-and-accumulate in binary/ternary deep neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay product than digital ASIC, and also achieves significantly higher accuracy than prior in-SRAM computing macro (e.g., 98.3% vs. 90% for MNIST) by being able to support the mainstream DNN/CNN algorithms.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"129 1","pages":"173-174"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77608052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510685
M. Takase, S. Isono, Y. Tomekawa, T. Koyanagi, T. Tokuhara, M. Harada, Y. Inoue
We realized a simultaneous-capture wide-dynamic-range image sensor with 3.0 μm pixels using novel in-pixel 3D capacitors located in BEOL. We achieved high capacitance density of 41.7 fF/μm2 and low leakage current density of 3.6×10−10 A/cm2 at 1 V by applying 3D structure and optimizing dielectric deposition process. TDDB investigations showed that estimated failure time at 125°C is more than 10 years. We demonstrated over 120 dB dynamic range image sensor with 3.0 μm pixels, which is enabled by this BEOL 3D capacitor process technology. (Keywords: image sensor, capacitor, 3D, BEOL, high reliability and wide dynamic range)
{"title":"An over 120 dB wide-dynamic-range 3.0 μm pixel image sensor with in-pixel capacitor of 41.7 fF/um2 and high reliability enabled by BEOL 3D capacitor process","authors":"M. Takase, S. Isono, Y. Tomekawa, T. Koyanagi, T. Tokuhara, M. Harada, Y. Inoue","doi":"10.1109/VLSIT.2018.8510685","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510685","url":null,"abstract":"We realized a simultaneous-capture wide-dynamic-range image sensor with 3.0 μm pixels using novel in-pixel 3D capacitors located in BEOL. We achieved high capacitance density of 41.7 fF/μm<sup>2</sup> and low leakage current density of 3.6×10<sup>−10</sup> A/cm<sup>2</sup> at 1 V by applying 3D structure and optimizing dielectric deposition process. TDDB investigations showed that estimated failure time at 125°C is more than 10 years. We demonstrated over 120 dB dynamic range image sensor with 3.0 μm pixels, which is enabled by this BEOL 3D capacitor process technology. (Keywords: image sensor, capacitor, 3D, BEOL, high reliability and wide dynamic range)","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"10 1","pages":"71-72"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85231042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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