Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510680
N. S. Avasarala, G. Donadio, T. Witters, K. Opsomer, B. Govoreanu, A. Fantini, S. Clima, H. Oh, S. Kundu, W. Devulder, M. H. van der Veen, J. van Houdt, M. Heyns, L. Goux, G. Kar
We report on the reduction of leakage current at half threshold bias (Ioff1/2) down to the 1nA range achieved using Se-enriched or N-doped GeSe. Integrated 50nm OTS devices demonstrated excellent thermal stability up to 600°C, as well as electrical stability (Vth, Ioff1/2) when operated at a high on current density of 23MA/cm2 for 108 cycles.
{"title":"Half-threshold bias Ioff reduction down to nA range of thermally and electrically stable high-performance integrated OTS selector, obtained by Se enrichment and N-doping of thin GeSe layers","authors":"N. S. Avasarala, G. Donadio, T. Witters, K. Opsomer, B. Govoreanu, A. Fantini, S. Clima, H. Oh, S. Kundu, W. Devulder, M. H. van der Veen, J. van Houdt, M. Heyns, L. Goux, G. Kar","doi":"10.1109/VLSIT.2018.8510680","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510680","url":null,"abstract":"We report on the reduction of leakage current at half threshold bias (I<inf>off1/2</inf>) down to the 1nA range achieved using Se-enriched or N-doped GeSe. Integrated 50nm OTS devices demonstrated excellent thermal stability up to 600°C, as well as electrical stability (V<inf>th</inf>, I<inf>off1/2</inf>) when operated at a high on current density of 23MA/cm<sup>2</sup> for 10<sup>8</sup> cycles.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"6 1","pages":"209-210"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86199816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510619
A. Alian, S. E. Kazzi, A. Verhulst, A. Milenin, N. Pinna, T. Ivanov, D. Lin, D. Mocuta, N. Collaert
Pocketed vertical nanowire InGaAs/GaAsSb tunnel FETs (TFET) with sub-threshold swing (SS) reaching 47 mV/dec are demonstrated. The achieved sub-threshold performance is the steepest reported so far for a top-down TFET in the III-V material system. Smooth vertical wires with diameters as narrow as 30 nm are achieved using a CH4 based dry etch process. Drive current at 0.35 V supply voltage approaches 0.7 μA/μm for a fixed Ioff of 1 nA/μm.
{"title":"Record 47 mV/dec top-down vertical nanowire InGaAs/GaAsSb tunnel FETs","authors":"A. Alian, S. E. Kazzi, A. Verhulst, A. Milenin, N. Pinna, T. Ivanov, D. Lin, D. Mocuta, N. Collaert","doi":"10.1109/VLSIT.2018.8510619","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510619","url":null,"abstract":"Pocketed vertical nanowire InGaAs/GaAsSb tunnel FETs (TFET) with sub-threshold swing (SS) reaching 47 mV/dec are demonstrated. The achieved sub-threshold performance is the steepest reported so far for a top-down TFET in the III-V material system. Smooth vertical wires with diameters as narrow as 30 nm are achieved using a CH4 based dry etch process. Drive current at 0.35 V supply voltage approaches 0.7 μA/μm for a fixed Ioff of 1 nA/μm.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"34 1","pages":"133-134"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89475122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510668
M. Rakowski, Y. Ban, P. De Heyn, N. Pantano, B. Snyder, S. Balakrishnan, S. Van Huylenbroeck, L. Bogaerts, C. Demeurisse, F. Inoue, K. Rebibis, P. Nolmans, X. Sun, P. Bex, A. Srinivasan, J. de Coster, S. Lardenois, A. Miller, P. Absil, P. Verheyen, D. Velenis, M. Pantouvaki, J. Van Campenhout
We demonstrate a microbump flip-chip integrated 14nm-FinFET CMOS-Silicon Photonics (SiPh) technology platform enabling ultra-low power Optical I/O transceivers with 1.6Tb/s/mm2 bandwidth density. The transmitter combines a differential FinFET driver with a Si ring modulator, enabling 40Gb/s NRZ optical modulation at 154fJ/bit dynamic power consumption in a 0.015mm2 footprint. The receiver combines a FinFET trans-impedance amplifier (TIA) with a Ge photodiode, enabling 40Gb/s NRZ photodetection with −10.3dBm sensitivity at 75fJ/bit power consumption, in a 0.01mm2 footprint. High-quality data transmission and reception is demonstrated in a loop-back experiment at 1330nm wavelength over standard single mode fiber (SMF) with 2dB link margin. Finally, a 4×40Gb/s, 0.1mm2 wavelength-division multiplexing (WDM) transmitter with integrated thermal control is demonstrated, enabling Optical I/O scaling substantially beyond 100Gb/s per fiber.
{"title":"Hybrid 14nm FinFET - Silicon Photonics Technology for Low-Power Tb/s/mm2 Optical I/O","authors":"M. Rakowski, Y. Ban, P. De Heyn, N. Pantano, B. Snyder, S. Balakrishnan, S. Van Huylenbroeck, L. Bogaerts, C. Demeurisse, F. Inoue, K. Rebibis, P. Nolmans, X. Sun, P. Bex, A. Srinivasan, J. de Coster, S. Lardenois, A. Miller, P. Absil, P. Verheyen, D. Velenis, M. Pantouvaki, J. Van Campenhout","doi":"10.1109/VLSIT.2018.8510668","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510668","url":null,"abstract":"We demonstrate a microbump flip-chip integrated 14nm-FinFET CMOS-Silicon Photonics (SiPh) technology platform enabling ultra-low power Optical I/O transceivers with 1.6Tb/s/mm2 bandwidth density. The transmitter combines a differential FinFET driver with a Si ring modulator, enabling 40Gb/s NRZ optical modulation at 154fJ/bit dynamic power consumption in a 0.015mm2 footprint. The receiver combines a FinFET trans-impedance amplifier (TIA) with a Ge photodiode, enabling 40Gb/s NRZ photodetection with −10.3dBm sensitivity at 75fJ/bit power consumption, in a 0.01mm2 footprint. High-quality data transmission and reception is demonstrated in a loop-back experiment at 1330nm wavelength over standard single mode fiber (SMF) with 2dB link margin. Finally, a 4×40Gb/s, 0.1mm2 wavelength-division multiplexing (WDM) transmitter with integrated thermal control is demonstrated, enabling Optical I/O scaling substantially beyond 100Gb/s per fiber.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"15 1","pages":"221-222"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85106163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510624
M. Mahmoodi, H. Nili, D. Strukov
We propose a novel architecture ("RX-PUF") for physically unclonable functions (PUF) based on analog RRAM crossbar array circuits. RX-PUF takes advantage of unique RRAM properties, such as I-V nonlinearity, and its device-to-device (d2d) variations and tunability. As a proof of concept, we have prototyped a 600 kb challenge response pair (CRP) PUF using 250 nm half-pitch (F) 20×20 crossbar arrays with passively integrated devices. The RX-PUF prototype features excellent physical characteristics, e.g. ~1600 F2/bit density and up to 41 fJ/bit energy efficiency. Its functional performance, improved by utilizing hidden input, is also very promising. The measured bit error rate (BER) was 0.7% at RT and ≤ 5.3% at 100°C, even without using any error correction methods. The measured responses showed near-ideal uniformity (50.04%) and inter-HD (50.12%) and passed all relevant NIST randomness tests. The preliminary results showed also very high resilience of RX-PUF against machine learning (ML) attacks.
{"title":"RX-PUF: Low Power, Dense, Reliable, and Resilient Physically Unclonable Functions Based on Analog Passive RRAM Crossbar Arrays","authors":"M. Mahmoodi, H. Nili, D. Strukov","doi":"10.1109/VLSIT.2018.8510624","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510624","url":null,"abstract":"We propose a novel architecture (\"RX-PUF\") for physically unclonable functions (PUF) based on analog RRAM crossbar array circuits. RX-PUF takes advantage of unique RRAM properties, such as I-V nonlinearity, and its device-to-device (d2d) variations and tunability. As a proof of concept, we have prototyped a 600 kb challenge response pair (CRP) PUF using 250 nm half-pitch (F) 20×20 crossbar arrays with passively integrated devices. The RX-PUF prototype features excellent physical characteristics, e.g. ~1600 F2/bit density and up to 41 fJ/bit energy efficiency. Its functional performance, improved by utilizing hidden input, is also very promising. The measured bit error rate (BER) was 0.7% at RT and ≤ 5.3% at 100°C, even without using any error correction methods. The measured responses showed near-ideal uniformity (50.04%) and inter-HD (50.12%) and passed all relevant NIST randomness tests. The preliminary results showed also very high resilience of RX-PUF against machine learning (ML) attacks.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"126 1","pages":"99-100"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88120951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510621
C. Yeh, W. Chien, R. Bruce, H. Cheng, I. Kuo, C. Yang, A. Ray, H. Miyazoe, W. Kim, F. Carta, E. Lai, M. BrightSky, H. Lung
For the first time published, high endurance OTS (ovonic threshold switch, here, TeAsGeSiSe-based) is integrated with PCM (here, doped Ge2Sb2Te5) to form a 3D stackable pillar type device. With the help of an etch buffer layer and a damage-free pillar RIE process, we achieved 100% array yield without OTS/PCM composition modification. Anneal tests show this one-selector/one-resistor (1S1R) pillar device is BEOL-compatible.We report excellent electrical performance by 1S1R OTS-PCM device; selector provides the fast turn on/off speed which enables 10ns fast RESET speed, program endurance is 109 cycles, and read endurance is higher than 1011 cycles.
{"title":"High Endurance Self-Heating OTS-PCM Pillar Cell for 3D Stackable Memory","authors":"C. Yeh, W. Chien, R. Bruce, H. Cheng, I. Kuo, C. Yang, A. Ray, H. Miyazoe, W. Kim, F. Carta, E. Lai, M. BrightSky, H. Lung","doi":"10.1109/VLSIT.2018.8510621","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510621","url":null,"abstract":"For the first time published, high endurance OTS (ovonic threshold switch, here, TeAsGeSiSe-based) is integrated with PCM (here, doped Ge2Sb2Te5) to form a 3D stackable pillar type device. With the help of an etch buffer layer and a damage-free pillar RIE process, we achieved 100% array yield without OTS/PCM composition modification. Anneal tests show this one-selector/one-resistor (1S1R) pillar device is BEOL-compatible.We report excellent electrical performance by 1S1R OTS-PCM device; selector provides the fast turn on/off speed which enables 10ns fast RESET speed, program endurance is 109 cycles, and read endurance is higher than 1011 cycles.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"418 1","pages":"205-206"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79496201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510700
Qian Yu, Xiaopeng Zhong, F. Boussaid, A. Bermak, CY Tsui
New gas sensitive FET (Gas-FET) structures are proposed to enable standard CMOS fabrication of high performance high density gas sensor arrays that are fully integrated with their associated circuitry. The performance of the proposed Gas-FET structures was investigated by fabricating an 8×8 Gas-FET array comprising 45µm×46µm sensing elements. Room temperature sub-ppm acetone sensing capability is demonstrated for non-invasive diabetes diagnosis through exhaled human breath. Performance comparison shows that the fabricated array boasts superior sensitivity while enabling ultra-low power operation at room temperature, with over 3 orders magnitude reduction in power consumption compared to previously reported standard CMOS resistive gas sensors.
{"title":"High Performance High Density Gas-FET Array in Standard CMOS","authors":"Qian Yu, Xiaopeng Zhong, F. Boussaid, A. Bermak, CY Tsui","doi":"10.1109/VLSIT.2018.8510700","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510700","url":null,"abstract":"New gas sensitive FET (Gas-FET) structures are proposed to enable standard CMOS fabrication of high performance high density gas sensor arrays that are fully integrated with their associated circuitry. The performance of the proposed Gas-FET structures was investigated by fabricating an 8×8 Gas-FET array comprising 45µm×46µm sensing elements. Room temperature sub-ppm acetone sensing capability is demonstrated for non-invasive diabetes diagnosis through exhaled human breath. Performance comparison shows that the fabricated array boasts superior sensitivity while enabling ultra-low power operation at room temperature, with over 3 orders magnitude reduction in power consumption compared to previously reported standard CMOS resistive gas sensors.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"38 1","pages":"39-40"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81147453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510625
A. Tsiara, X. Garros, L. Brunet, P. Batude, C. Fenouillet-Béranger, K. Triantopoulos, M. Cassé, M. Vinet, F. Gaillard, G. Ghibaudo
We investigate in detail, for the first time, both performance and reliability of a 3D sequential integration process. It is clearly demonstrated that the top level transistor can be successfully processed at 630°C with almost no impact on the performance and reliability of the bottom level. It is also highlighted that top level devices meet the P&NBTI reliability requirements. Finally an example of successful and robust 3D logic integration is proposed based on a 3D inverter combining a top-level PMOS with a bottom-level NMOS.
{"title":"Performance and Reliability of a Fully Integrated 3D Sequential Technology","authors":"A. Tsiara, X. Garros, L. Brunet, P. Batude, C. Fenouillet-Béranger, K. Triantopoulos, M. Cassé, M. Vinet, F. Gaillard, G. Ghibaudo","doi":"10.1109/VLSIT.2018.8510625","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510625","url":null,"abstract":"We investigate in detail, for the first time, both performance and reliability of a 3D sequential integration process. It is clearly demonstrated that the top level transistor can be successfully processed at 630°C with almost no impact on the performance and reliability of the bottom level. It is also highlighted that top level devices meet the P&NBTI reliability requirements. Finally an example of successful and robust 3D logic integration is proposed based on a 3D inverter combining a top-level PMOS with a bottom-level NMOS.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"89 1","pages":"75-76"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75907120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510672
G. Jan, L. Thomas, S. Le, Yuan-Jen Lee, Huanlong Liu, Jian Zhu, J. Iwata-Harms, Sahil J. Patel, R. Tong, V. Sundar, S. Serrano-Guisan, D. Shen, R. He, J. Haq, Z. Teng, V. Lam, Yi Yang, Yu-Jen Wang, T. Zhong, H. Fukuzawa, P. Wang
We present for the first time STT-MRAM devices with ultra low operating voltage and power compatible with next generation 0x node logic voltages. By engineering the tunnel barrier and improving the efficiency of the devices we report a record low writing voltage of 0.17V for a 1ppm error rate, which has been achieved for a 20ns write operation using a writing current of only 35uA. We further demonstrate error rates below 10-9 at voltage and current at 0.25V and 50uA using 10ns writing pulses on the same 30nm devices with extended 400C thermal budget while preserving functionality confirm the almost unlimited endurance of these data and retention at 85°C. Finally, TDDB studies confirm the almost unlimited endurance of these devices at the operating voltage.
{"title":"Demonstration of Ultra-Low Voltage and Ultra Low Power STT-MRAM designed for compatibility with 0x node embedded LLC applications","authors":"G. Jan, L. Thomas, S. Le, Yuan-Jen Lee, Huanlong Liu, Jian Zhu, J. Iwata-Harms, Sahil J. Patel, R. Tong, V. Sundar, S. Serrano-Guisan, D. Shen, R. He, J. Haq, Z. Teng, V. Lam, Yi Yang, Yu-Jen Wang, T. Zhong, H. Fukuzawa, P. Wang","doi":"10.1109/VLSIT.2018.8510672","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510672","url":null,"abstract":"We present for the first time STT-MRAM devices with ultra low operating voltage and power compatible with next generation 0x node logic voltages. By engineering the tunnel barrier and improving the efficiency of the devices we report a record low writing voltage of 0.17V for a 1ppm error rate, which has been achieved for a 20ns write operation using a writing current of only 35uA. We further demonstrate error rates below 10-9 at voltage and current at 0.25V and 50uA using 10ns writing pulses on the same 30nm devices with extended 400C thermal budget while preserving functionality confirm the almost unlimited endurance of these data and retention at 85°C. Finally, TDDB studies confirm the almost unlimited endurance of these devices at the operating voltage.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"63 1","pages":"65-66"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80721223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510666
J. Mitard, D. Jang, G. Eneman, H. Arimura, B. Parvais, O. Richard, P. Van Marcke, L. Witters, E. Capogreco, H. Bender, R. Ritzenthaler, H. Mertens, A. Hikavyy, R. Loo, H. Dekkers, F. Sebaai, A. Milenin, N. Horiguchi, A. Mocuta, D. Mocuta, N. Collaert
An in-depth study of scaled nanowire Ge pFETs for digital and analog applications is proposed. Improved device characteristics are first obtained after gaining a good understanding of the HPA on device performance. Up to 45% higher ID,SAT is obtained at IOFF=3nA/fin when comparing to best Si GAA nFET and similar ID,SAT is found when benchmarking to mature 14/16nm pFinFET technology at −0.5 VDD. The temperature dependent study of ID,SAT highlights that the mechanism limiting the transport in Ge at short channel are neither purely diffusive nor fully ballistic.
{"title":"An In-depth Study of High-Performing Strained Germanium Nanowires pFETs","authors":"J. Mitard, D. Jang, G. Eneman, H. Arimura, B. Parvais, O. Richard, P. Van Marcke, L. Witters, E. Capogreco, H. Bender, R. Ritzenthaler, H. Mertens, A. Hikavyy, R. Loo, H. Dekkers, F. Sebaai, A. Milenin, N. Horiguchi, A. Mocuta, D. Mocuta, N. Collaert","doi":"10.1109/VLSIT.2018.8510666","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510666","url":null,"abstract":"An in-depth study of scaled nanowire Ge pFETs for digital and analog applications is proposed. Improved device characteristics are first obtained after gaining a good understanding of the HPA on device performance. Up to 45% higher ID,SAT is obtained at IOFF=3nA/fin when comparing to best Si GAA nFET and similar ID,SAT is found when benchmarking to mature 14/16nm pFinFET technology at −0.5 VDD. The temperature dependent study of ID,SAT highlights that the mechanism limiting the transport in Ge at short channel are neither purely diffusive nor fully ballistic.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"17 1","pages":"83-84"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82134951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510641
M. Togo, R. Asra, P. Balasubramaniam, X. Zhang, H. Yu, S. Yamaguchi, E. Geiss, H. Yang, B. Cohen, H. Lo, O. Hu, H. Lazar, O. Kwon, D. Burnett, J. Versaggi, E. Banghart, M. K. Hassan, E. Bazizi, L. Pantisano, J. G. Lee, S. Samavedam, D. K. Sohn
A multiple workfunction (multi-WF) integration technology was developed for ultra-low voltage operation in high performance FinFETs. It is essential to solve three key issues in the multi-WF process, a) short channel effect (SCE) degradation due to removing halo implants b) gate resistance increase due to multi-WF stack, and c) gate dielectric reliability degradation due to additional patterning. In this study, we resolve these issues through the combination of junction engineering and workfunction metal (WFM) boolean engineering in long channel (LC) and short channel (SC) devices for SCE, WFM stack optimization for gate resistance, and HK interface optimization for reliability. In logic devices, 15/13% N/PFET DC and 14% AC performance were improved without SCE or reliability degradation. In SRAM devices, 43% Vt mismatch (Vtmm) improvement resulted in record Vmin yield down to 0.4V on 128Mb 0.064μm2 SRAM array.
{"title":"Multiple Workfunction High Performance FinFETs for Ultra-low Voltage Operation","authors":"M. Togo, R. Asra, P. Balasubramaniam, X. Zhang, H. Yu, S. Yamaguchi, E. Geiss, H. Yang, B. Cohen, H. Lo, O. Hu, H. Lazar, O. Kwon, D. Burnett, J. Versaggi, E. Banghart, M. K. Hassan, E. Bazizi, L. Pantisano, J. G. Lee, S. Samavedam, D. K. Sohn","doi":"10.1109/VLSIT.2018.8510641","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510641","url":null,"abstract":"A multiple workfunction (multi-WF) integration technology was developed for ultra-low voltage operation in high performance FinFETs. It is essential to solve three key issues in the multi-WF process, a) short channel effect (SCE) degradation due to removing halo implants b) gate resistance increase due to multi-WF stack, and c) gate dielectric reliability degradation due to additional patterning. In this study, we resolve these issues through the combination of junction engineering and workfunction metal (WFM) boolean engineering in long channel (LC) and short channel (SC) devices for SCE, WFM stack optimization for gate resistance, and HK interface optimization for reliability. In logic devices, 15/13% N/PFET DC and 14% AC performance were improved without SCE or reliability degradation. In SRAM devices, 43% Vt mismatch (Vtmm) improvement resulted in record Vmin yield down to 0.4V on 128Mb 0.064μm2 SRAM array.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"81-82"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79799205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：