This paper presents studies on the launderability of 4 types of conductive fabrics made by weaving polyester and nylon yarns with metal coatings (Cu, Ag, Ni/Cu, Ni/Cu/Co). They are laminated with thermoplastic urethane (TPU) film under hot compression on the 3 common fabrics (Spandex, Nylon, Denim) with different elongation and flexibility. Electrical resistance as a function of laundry cycles is used to characterize the performance of the conductive materials. The laundry procedure is to follow AATCC M6 test standard by using the AATCC compliant laundry machine and dryer with the factor control such as detergent, water temperature, agitation speed and spin speed and so on. After intended wash and dry cycles, test samples are measured in electrical resistance with 4 point probe ohm meter to detect the resistance stability. The rise of resistance of conductive material over the wash/dry cycle can be compared among 4 metal coating on the 3 common fabrics. In general, the unstable resistance and electrical open can be reflected with the microstructure fracture observation under 3D optical microscope and SEM to provide further insight on the performance of these conductive materials withstanding laundering process. Furthermore, Non-destructive analysis of low angle XRD and XRF are also adopted to analyze the metal crystalline lattice structure and thickness change after laundering process for the understanding of degradation mechanisms. The elongation effect of base fabric of Spandex, Polyester and Nylon under certain washing shear force during agitation on the conductive fabric launderability can be concluded.
{"title":"Laundering Reliability of Electrically Conductive Fabrics for E-Textile Applications","authors":"J. Lee, Weifeng Liu, ChangHo Lo, Cheng-Chih Chen","doi":"10.1109/ECTC.2019.00281","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00281","url":null,"abstract":"This paper presents studies on the launderability of 4 types of conductive fabrics made by weaving polyester and nylon yarns with metal coatings (Cu, Ag, Ni/Cu, Ni/Cu/Co). They are laminated with thermoplastic urethane (TPU) film under hot compression on the 3 common fabrics (Spandex, Nylon, Denim) with different elongation and flexibility. Electrical resistance as a function of laundry cycles is used to characterize the performance of the conductive materials. The laundry procedure is to follow AATCC M6 test standard by using the AATCC compliant laundry machine and dryer with the factor control such as detergent, water temperature, agitation speed and spin speed and so on. After intended wash and dry cycles, test samples are measured in electrical resistance with 4 point probe ohm meter to detect the resistance stability. The rise of resistance of conductive material over the wash/dry cycle can be compared among 4 metal coating on the 3 common fabrics. In general, the unstable resistance and electrical open can be reflected with the microstructure fracture observation under 3D optical microscope and SEM to provide further insight on the performance of these conductive materials withstanding laundering process. Furthermore, Non-destructive analysis of low angle XRD and XRF are also adopted to analyze the metal crystalline lattice structure and thickness change after laundering process for the understanding of degradation mechanisms. The elongation effect of base fabric of Spandex, Polyester and Nylon under certain washing shear force during agitation on the conductive fabric launderability can be concluded.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"1826-1832"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82066659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper simulates the pressure of extreme marine environment, carries out pressure test on BGA devices, studies the changes and trends of BGA solder joints before and after test, analyses the reliability changes and the potential risks. The model of BGA solder joints is established by means of finite element modeling, and the influence of the position and size of voids in BGA solder joints after reflow soldering in pressure test is studied. Therefore, the preventive inspection measures for the corresponding reliability risk of BGA solder joints are put forward, which provides reliability assurance advice for BGA solder joints exposed to extreme marine environment.
{"title":"Research on Applied Reliability of BGA Solder Balls in Extreme Marine Environment","authors":"Liyuan Liu, T. Lu, D. Luo, Hui Xiao","doi":"10.1109/ECTC.2019.00315","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00315","url":null,"abstract":"The paper simulates the pressure of extreme marine environment, carries out pressure test on BGA devices, studies the changes and trends of BGA solder joints before and after test, analyses the reliability changes and the potential risks. The model of BGA solder joints is established by means of finite element modeling, and the influence of the position and size of voids in BGA solder joints after reflow soldering in pressure test is studied. Therefore, the preventive inspection measures for the corresponding reliability risk of BGA solder joints are put forward, which provides reliability assurance advice for BGA solder joints exposed to extreme marine environment.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"107 1","pages":"2054-2060"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87666258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. I. Mohd Ghazali, Saikat Mondal, Saranraj Karuppuswami, P. Chahal
In this paper, Additive Manufacturing (AM) using 3D printing has been shown as a potential candidate for realizing customized compact solutions for RF packaging applications. Cost effective 3D printing based packaging solutions with customized substrates and air gaps allow easier integration of multiple RF components with lower substrate losses. Using a damascene-like conductor patterning process and a LEGO-like assembly process, an amplifier coupled to an air-substrate based patch antenna is demonstrated in a single integrated package. The antenna overlays the amplifier circuit leading to a compact design. The proposed customization of substrates and 3D printing strategies can be extended to multiple-system level stacking for SOP/SIP packaging customized for applications such as 5G.
{"title":"3D Printed Substrates for the Design of Compact RF Systems","authors":"M. I. Mohd Ghazali, Saikat Mondal, Saranraj Karuppuswami, P. Chahal","doi":"10.1109/ECTC.2019.00025","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00025","url":null,"abstract":"In this paper, Additive Manufacturing (AM) using 3D printing has been shown as a potential candidate for realizing customized compact solutions for RF packaging applications. Cost effective 3D printing based packaging solutions with customized substrates and air gaps allow easier integration of multiple RF components with lower substrate losses. Using a damascene-like conductor patterning process and a LEGO-like assembly process, an amplifier coupled to an air-substrate based patch antenna is demonstrated in a single integrated package. The antenna overlays the amplifier circuit leading to a compact design. The proposed customization of substrates and 3D printing strategies can be extended to multiple-system level stacking for SOP/SIP packaging customized for applications such as 5G.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"17 1","pages":"113-118"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87563727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The full preferential growth intermetallic compound (IMC) interconnects are fabricated on a (111) Cu single crystal substrate by the method named current driven bonding (CDB), and the morphology, orientation, electromigration resistance and mechanical properties of the full preferential growth Cu6Sn5 grains in the (111) Cu/IMC (30 µm Cu6Sn5)/Cu interconnects are investigated. The CDB method successfully controls the crystal orientation and maintains the preferential growth of Cu6Sn5 grains on (111) Cu single crystal substrate. The prism-type Cu6Sn5 grains show a texture feature and the continuous preferential epitaxial growth of Cu6Sn5 form the full IMC interconnect with <"11" "2" -"0" >Cu6Sn5 directions paralleling to the current flowing direction. The fabrication of full preferential growth IMC interconnects provides an approach to unify the orientations of the IMC interconnects, which effectively eliminates the random distribution of grain orientations and thus the anisotropy of interconnects. The full (111) Cu/Cu6Sn5/Cu IMC interconnects exhibite an excellent electromigration resistance and high mechanical reliability even after having experienced high temperature aging and high current stressing. There is no obvious damage after aging and current stressing (2.0×104 A/cm2) at 150 oC and 180 oC even for 500 h. The average tensile strength of full preferential growth IMC interconnects remaines unchanged, i.e., 111.1 MPa and 108.1 MPa, even after aging at 150 oC for 500 h and current stressing (2.0×104 A/cm2) at 150 oC for 500 h, respectively, which are similar to that of the as-soldered state (118.8 MPa). This work is expected to provide theory support and guidance for the application of full preferential growth and high strength IMC interconnects in 3D IC packaging.
{"title":"Effects of Electromigration on Microstructural Evolution and Mechanical Properties of Preferential Growth Intermetallic Compound Interconnects for 3D Packaging","authors":"Mingliang L. Huang, L. Zou","doi":"10.1109/ECTC.2019.00274","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00274","url":null,"abstract":"The full preferential growth intermetallic compound (IMC) interconnects are fabricated on a (111) Cu single crystal substrate by the method named current driven bonding (CDB), and the morphology, orientation, electromigration resistance and mechanical properties of the full preferential growth Cu6Sn5 grains in the (111) Cu/IMC (30 µm Cu6Sn5)/Cu interconnects are investigated. The CDB method successfully controls the crystal orientation and maintains the preferential growth of Cu6Sn5 grains on (111) Cu single crystal substrate. The prism-type Cu6Sn5 grains show a texture feature and the continuous preferential epitaxial growth of Cu6Sn5 form the full IMC interconnect with <\"11\" \"2\" -\"0\" >Cu6Sn5 directions paralleling to the current flowing direction. The fabrication of full preferential growth IMC interconnects provides an approach to unify the orientations of the IMC interconnects, which effectively eliminates the random distribution of grain orientations and thus the anisotropy of interconnects. The full (111) Cu/Cu6Sn5/Cu IMC interconnects exhibite an excellent electromigration resistance and high mechanical reliability even after having experienced high temperature aging and high current stressing. There is no obvious damage after aging and current stressing (2.0×104 A/cm2) at 150 oC and 180 oC even for 500 h. The average tensile strength of full preferential growth IMC interconnects remaines unchanged, i.e., 111.1 MPa and 108.1 MPa, even after aging at 150 oC for 500 h and current stressing (2.0×104 A/cm2) at 150 oC for 500 h, respectively, which are similar to that of the as-soldered state (118.8 MPa). This work is expected to provide theory support and guidance for the application of full preferential growth and high strength IMC interconnects in 3D IC packaging.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"418 1","pages":"1774-1781"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82776698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ahmed Elmogi, A. Desmet, J. Missinne, H. Ramon, J. Lambrecht, P. De Heyn, M. Pantouvaki, J. Van Campenhout, J. Bauwelinck, G. Van Steenberge
Packaging and assembly challenges for photonic chips still need to be addressed in order to enable rapid deployment in mass-market production. Integration and assembly solutions that not only enable ease of packaging but also allow a dense co-integration of the electronic and photonic ICs are essential. In that context, we demonstrate an adaptive patterning of both optical and electrical fan-out for face-up electronic-photonic integration. For the optical fan-out, we developed an approach based on adiabatic optical coupling between single-mode polymer waveguides and silicon waveguides on a silicon photonic chip. The polymer waveguides were directly patterned on the silicon photonic chip by direct-write lithography (DWL). The electrical interconnects between a photonic chip and electronic IC are realized by employing high-speed silver interconnects using aerosol-jet printing (AJP), as a promising alternative for the traditional bond-wires. Furthermore, a direct comparison between the AJP interconnects and the conventional bondwires is established. Finally, an NRZ optical transmitter has been successfully demonstrated based on the AJP interconnection and clear open eye diagrams were obtained at 56 Gb/s.
{"title":"Adaptive Patterning of Optical and Electrical Fan-Out for Photonic Chip Packaging","authors":"Ahmed Elmogi, A. Desmet, J. Missinne, H. Ramon, J. Lambrecht, P. De Heyn, M. Pantouvaki, J. Van Campenhout, J. Bauwelinck, G. Van Steenberge","doi":"10.1109/ECTC.2019.00269","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00269","url":null,"abstract":"Packaging and assembly challenges for photonic chips still need to be addressed in order to enable rapid deployment in mass-market production. Integration and assembly solutions that not only enable ease of packaging but also allow a dense co-integration of the electronic and photonic ICs are essential. In that context, we demonstrate an adaptive patterning of both optical and electrical fan-out for face-up electronic-photonic integration. For the optical fan-out, we developed an approach based on adiabatic optical coupling between single-mode polymer waveguides and silicon waveguides on a silicon photonic chip. The polymer waveguides were directly patterned on the silicon photonic chip by direct-write lithography (DWL). The electrical interconnects between a photonic chip and electronic IC are realized by employing high-speed silver interconnects using aerosol-jet printing (AJP), as a promising alternative for the traditional bond-wires. Furthermore, a direct comparison between the AJP interconnects and the conventional bondwires is established. Finally, an NRZ optical transmitter has been successfully demonstrated based on the AJP interconnection and clear open eye diagrams were obtained at 56 Gb/s.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"61 1","pages":"1757-1763"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83139829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ji Li, Yang Wang, Peiren Wang, Jiangling He, Handa Liu, Gengzhao Xiang
This work proposes a novel hybrid additive manufacturing method integrating dual-material FDM 3D printing and selective electroless plating. Fused deposition modeling dual-material 3D printer is employed to fabricate 3D substrate consisting of platable and non-platable plastics according to CAD digital design. After proper surface treatments, only platable plastic is able to preserve the electroless catalysts and thereby metal film can be selectively deposited. This offers a convenient solution for freeform patterning of 3D circuitry. After electronic components mounting, a full-functional customized 3D electronic product is created. The adhesion of electroless metal film can achieve the highest grade (5B) of tape test, and the minimal resistivity obtained is 5 µΩ · cm with copper film. A 3D LED blinking circuitry was fabricated as demonstrators to prove the feasibility and potential of this technology.
{"title":"Rapid Production of Customized 3D Electronics Via Hybrid Additive Manufacturing Technology","authors":"Ji Li, Yang Wang, Peiren Wang, Jiangling He, Handa Liu, Gengzhao Xiang","doi":"10.1109/ECTC.2019.00028","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00028","url":null,"abstract":"This work proposes a novel hybrid additive manufacturing method integrating dual-material FDM 3D printing and selective electroless plating. Fused deposition modeling dual-material 3D printer is employed to fabricate 3D substrate consisting of platable and non-platable plastics according to CAD digital design. After proper surface treatments, only platable plastic is able to preserve the electroless catalysts and thereby metal film can be selectively deposited. This offers a convenient solution for freeform patterning of 3D circuitry. After electronic components mounting, a full-functional customized 3D electronic product is created. The adhesion of electroless metal film can achieve the highest grade (5B) of tape test, and the minimal resistivity obtained is 5 µΩ · cm with copper film. A 3D LED blinking circuitry was fabricated as demonstrators to prove the feasibility and potential of this technology.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"47 1","pages":"135-140"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80735896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Meier Karsten, Winkler Maria, L. David, D. Abhijit, Bock Karlheinz
The increasing demand for highly reliable electronic devices, even though they are exposed to harsh use conditions, is one of the main drivers for the development of electronic systems. System development process relies on the selection of materials, technologies and a proper design to meet the mission profile's demands. Among many others, the lead-free solder alloy SnAg1.0Cu0.5 (SAC105) is widely used for many electronic assemblies deployed for various applications. The fatigue behaviour of SAC105 under thermal loads (namely temperature cycling and shock testing) and drop testing has been covered extensively in the literature. Work on damage accumulation under vibration conditions has been accomplished but primarily at room temperature. Therefore, this work aims to expand knowledge of the fatigue behaviour of SAC105 under combined thermal and vibration loading. In this work, vibration durability experiments were conducted at temperatures from -40°C to +125°C and vibration peak-to-peak amplitudes from 0.6 mm to 1.6 mm. Currently, specimens have been subjected to tests with durations of 75x10E6 or 150x10E6 vibration cycles. Cross sections were analysed to relate damage locations and severity to stress conditions (temperature and vibration amplitude). As expected, damage levels were observed to increase with increasing temperatures and vibration amplitudes.
{"title":"Fatigue Behaviour of Lead-Free Solder Joints Under Combined Thermal and Vibration Loads","authors":"Meier Karsten, Winkler Maria, L. David, D. Abhijit, Bock Karlheinz","doi":"10.1109/ECTC.2019.00082","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00082","url":null,"abstract":"The increasing demand for highly reliable electronic devices, even though they are exposed to harsh use conditions, is one of the main drivers for the development of electronic systems. System development process relies on the selection of materials, technologies and a proper design to meet the mission profile's demands. Among many others, the lead-free solder alloy SnAg1.0Cu0.5 (SAC105) is widely used for many electronic assemblies deployed for various applications. The fatigue behaviour of SAC105 under thermal loads (namely temperature cycling and shock testing) and drop testing has been covered extensively in the literature. Work on damage accumulation under vibration conditions has been accomplished but primarily at room temperature. Therefore, this work aims to expand knowledge of the fatigue behaviour of SAC105 under combined thermal and vibration loading. In this work, vibration durability experiments were conducted at temperatures from -40°C to +125°C and vibration peak-to-peak amplitudes from 0.6 mm to 1.6 mm. Currently, specimens have been subjected to tests with durations of 75x10E6 or 150x10E6 vibration cycles. Cross sections were analysed to relate damage locations and severity to stress conditions (temperature and vibration amplitude). As expected, damage levels were observed to increase with increasing temperatures and vibration amplitudes.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"16 1","pages":"498-504"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81201164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tan Lu, Han Gu, Yougen Hu, T. Zhao, Pengli Zhu, R. Sun, C. Wong
With the rapid growth of modern electronic devices towards higher power, higher integration, thinner, lighter, and smaller, electrical and thermal conductive as well as electromagnetic interference (EMI) shielding issues are attracted more and more concerns. Thermal interface materials (TIMs) with high thermal conductivity and excellent EMI shielding efficiency are desired to solve heat emission and EMI problems of the electronic devices. So far, most of studies were independently focused on TIMs or EMI shielding materials, which have many limits for some practical applications. In this work, to address the challenges, a unique material with above dual functions was developed. The material composed of Cu foam skeleton and filled thermoplastic polyurethane/silver (TPU/Ag) elastic conductive composite, which shows better mechanical flexibility, higher thermal conductivity and higher EMI shielding effectiveness compared with sole Cu foam or TPU/Ag composite. The outstanding performance of the Cu foam/TPU/Ag composite will see a promising application in the EMI shielding and heat management of electronic devices.
{"title":"Three Dimensional Copper Foam-Filled Elastic Conductive Composites with Simultaneously Enhanced Mechanical, Electrical, Thermal and Electromagnetic Interference (EMI) Shielding Properties","authors":"Tan Lu, Han Gu, Yougen Hu, T. Zhao, Pengli Zhu, R. Sun, C. Wong","doi":"10.1109/ECTC.2019.00295","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00295","url":null,"abstract":"With the rapid growth of modern electronic devices towards higher power, higher integration, thinner, lighter, and smaller, electrical and thermal conductive as well as electromagnetic interference (EMI) shielding issues are attracted more and more concerns. Thermal interface materials (TIMs) with high thermal conductivity and excellent EMI shielding efficiency are desired to solve heat emission and EMI problems of the electronic devices. So far, most of studies were independently focused on TIMs or EMI shielding materials, which have many limits for some practical applications. In this work, to address the challenges, a unique material with above dual functions was developed. The material composed of Cu foam skeleton and filled thermoplastic polyurethane/silver (TPU/Ag) elastic conductive composite, which shows better mechanical flexibility, higher thermal conductivity and higher EMI shielding effectiveness compared with sole Cu foam or TPU/Ag composite. The outstanding performance of the Cu foam/TPU/Ag composite will see a promising application in the EMI shielding and heat management of electronic devices.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"46 1","pages":"1916-1920"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91241544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Novel low-temperature curable positive-tone photosensitive polyimide (posi-PSPI) with high reliability has been developed as dielectric layers for copper redistribution layers (RDLs) in Fan-Out wafer/panel level packages (FOWLP, FOPLP). The posi-PSPI shows high tolerance to thermal cycle test, high temperature storage test and Cu migration test. In order to achieve these properties, we investigated both segments of flexible and rigid molecular skeletons within the base polymer backbone. Through a modification of suitable flexible segment contributed to Cu migration resistance with its assumed characteristics to have better flow coverage of Cu patterns. In addition to segmental modification, we also came to realize that a balance between flexible and rigid segment was an important factor for the stabilization of elongation under freezing temperature and thermal cycle test. Furthermore, we have also investigated an additive within the material such as anti-oxidant. This additive suppressed the voids from generating between Cu and Polyimide, which are the initial cause of delamination. This phenomenon of void formation was due to rapid speed of Cu oxide diffusion during a high temperature storage test. The posi-PSPI offers fine pattern with good sensitivity by photolithographic system. It can also be processed by laser direct imager (LDI) instead of i-line stepper or aligner, and the patterned material made by photolithography can be reworked by organic solvents. In addition, this posi-PSPI showed high adhesion to various substrates, such as Si, Cu, Mold resin, and PI itself. These features certify that this material is suitable for applications of FOWLP/FOPLP.
{"title":"Development of Novel Low-Temperature Curable Positive-Tone Photosensitive Dielectric Materials with High Reliability","authors":"Yutaro Koyama, Yu Shoji, K. Hashimoto, Yuki Masuda, Hitoshi Araki, Masao Tomikawa","doi":"10.1109/ECTC.2019.00060","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00060","url":null,"abstract":"Novel low-temperature curable positive-tone photosensitive polyimide (posi-PSPI) with high reliability has been developed as dielectric layers for copper redistribution layers (RDLs) in Fan-Out wafer/panel level packages (FOWLP, FOPLP). The posi-PSPI shows high tolerance to thermal cycle test, high temperature storage test and Cu migration test. In order to achieve these properties, we investigated both segments of flexible and rigid molecular skeletons within the base polymer backbone. Through a modification of suitable flexible segment contributed to Cu migration resistance with its assumed characteristics to have better flow coverage of Cu patterns. In addition to segmental modification, we also came to realize that a balance between flexible and rigid segment was an important factor for the stabilization of elongation under freezing temperature and thermal cycle test. Furthermore, we have also investigated an additive within the material such as anti-oxidant. This additive suppressed the voids from generating between Cu and Polyimide, which are the initial cause of delamination. This phenomenon of void formation was due to rapid speed of Cu oxide diffusion during a high temperature storage test. The posi-PSPI offers fine pattern with good sensitivity by photolithographic system. It can also be processed by laser direct imager (LDI) instead of i-line stepper or aligner, and the patterned material made by photolithography can be reworked by organic solvents. In addition, this posi-PSPI showed high adhesion to various substrates, such as Si, Cu, Mold resin, and PI itself. These features certify that this material is suitable for applications of FOWLP/FOPLP.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"33 1","pages":"346-351"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76688705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Thong Nguyen, Xinying Wang, Xu Chen, J. Schutt-Ainé
Volterra kernels are well known to be the multidimensional extension of the impulse response of a linear time invariant (LTI) system. It can be used to accurately model weakly nonlinear, specifically, polynomial nonlinearity systems. It has been used in the past for white-box model order reduction (MOR) to model frequency-domain performance metric quantities such as distortion in power amplifiers (PA). In this paper, we train a neural network from time-domain response of high-speed link buffers to extract multiple high-order kernels at once. Once the kernels are extracted, they can fully characterize the dynamics of the buffers of interest. Using the kernels, we demonstrate that time-domain response is straight-forward to obtain using super-, or multi-dimensional convolution. Previous work has used a shallow feed-forward neural network to train the system by using Gaussian noise as the identification signal. This is not convenient for the method to be compatible with existing computer-aided design tools. In this work, we directly use a pseudo random bit sequence (PRBS) to train the network. The proposed technique is more challenging because the PRBS has flat regions which have highly rich frequency spectrum and requires longer memory length, but allows the method to be compatible with existing simulation programs. We investigate different topologies including feed-forward neural network and recurrent neural network. Comparisons between training phase, inference phase, convergence are presented using different neural network topologies. The paper presents a numerical example using a 28Gbps data rate PAM4 transceiver to validate the proposed method against traditional simulation methods such as IBIS or SPICE level simulation for comparison in speed and accuracy. Using Volterra kernels promises a novel way to perform accurate nonlinear circuit simulation in the LTI system framework which is already well known and well developed. It can be conveniently incorporated into existing EDA frameworks.
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