Youngjae Kim, Jinho Hah, Patxi Fernandez-Zelaia, Sangil Lee, L. Christie, P. Houston, S. Melkote, K. Moon, C. Wong
Differences in microstructures of lead-free solder joints, Sn-Ag-Cu (96.5 wt./3.0 wt./0.5 wt.% SAC-305), made by two different semiconductor packaging processes such as reflow and TCB are discussed. Despite the enormous potential for TCB solder bonding process in microelectronic packaging, there has been few studies regarding the comparative analysis on electro-migration (EM) failure mechanism for the reflow process. We have systematically examined the EM-derived failures of the reflow and TCB-processed solder joints and demonstrated a process-structure-property linkage. This study also includes the analysis performed using generalized spherical harmonics (GSH) representation, a statistical and quantitative measure of material crystallographic informatics, which is novel in this field as to analyzing solder joint microstructures.
{"title":"Microstructures of Pb-Free Solder Joints by Reflow and Thermo-Compression Bonding (TCB) Processes","authors":"Youngjae Kim, Jinho Hah, Patxi Fernandez-Zelaia, Sangil Lee, L. Christie, P. Houston, S. Melkote, K. Moon, C. Wong","doi":"10.1109/ECTC.2019.00324","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00324","url":null,"abstract":"Differences in microstructures of lead-free solder joints, Sn-Ag-Cu (96.5 wt./3.0 wt./0.5 wt.% SAC-305), made by two different semiconductor packaging processes such as reflow and TCB are discussed. Despite the enormous potential for TCB solder bonding process in microelectronic packaging, there has been few studies regarding the comparative analysis on electro-migration (EM) failure mechanism for the reflow process. We have systematically examined the EM-derived failures of the reflow and TCB-processed solder joints and demonstrated a process-structure-property linkage. This study also includes the analysis performed using generalized spherical harmonics (GSH) representation, a statistical and quantitative measure of material crystallographic informatics, which is novel in this field as to analyzing solder joint microstructures.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"38 1","pages":"2349-2358"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78431336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fuhan Liu, Chandrasekharan Nair, Gaurav Khurana, A. Watanabe, Bartlet H. Deprospo, A. Kubo, C. Lin, T. Makita, Naoki Watanabe, R. Tummala
Microvia is the vertical interconnect structure for multi-layer redistribution layers (RDLs) in high-density interconnect (HDI) printed circuit boards (PCBs), HDI package substrates, 2.5D interposers and fan-out packages. Three technologies such as photolithography, UV laser and excimer laser have been used to form small microvias (≤ 20 µm diameter) in polymer dielectrics. All the three above mentioned technologies are studied and compared in the work presented in this paper. Photovia was first introduced by IBM for Surface Laminar Circuit technology and it has scaled down from 125 µm then to below 10 µm today. The smallest photovia demonstrated is 2 µm in diameter by using 365 nm photolithography in 5 µm thick TOK photo-imageable dielectric (PID) (IF4605) film. Photovias of 3 µm diameter were also demonstrated in 5 µm thick Taiyo Ink dielectric dry film material (PDM) which passed 1,500 thermal cycles (-55 C to 125 C). The limitation of photovia technology is the availability and cost of photo-sensitive dielectric materials with the required electrical, mechanical, thermal and chemical properties. The state-of-the-art microvia diameter is 20 µm by using conventional high-speed UV laser technologies. Multi-layer RDL with microvias and trenches of 4 µm feature sizes are simultaneously fabricated in a 7 µm thick Ajinomoto Build-up Film (ABF) with small fillers by using excimer laser and passed 1,000 thermal cycles (-55 C to 125 C). This paper demonstrates a novel picosecond UV laser technology to push the limits of low-cost UV laser technology by optimizing laser parameters and dielectric materials. The Cornerstone picosecond UV laser tool from ESI is capable of producing output power of 16W at 355 nm wavelength. The pulse duration is 5 ps which minimizes the heat-affected zone of polymer dielectric and the high (80 MHz) repetition rate enables this laser to be used in high throughput manufacturing processes. Microvias with minimum diameter of < 7 µm were fabricated in 5 µm thick ABF with small fillers and in 7 µm thick novel Panasonic low stress dielectric film-S (PLS-S), by using 355 nm picosecond UV laser tool. These ABF and PLS-S films are non-photosensitive dielectric materials. This is the first demonstration of very small microvias (< 7 µm) in polymer dielectrics using UV laser ablation. The motivation of this work is to address the high RDL interconnect density requirements for 2.5D interposer and high density (HD) fan-out packages. The next generation of low-cost, ultra-small microvias will (1) Increase the RDL I/O density, (2) Meet fine bump pitch requirements, (3) Reduce the metal layer count for package substrate RDL, (4) Fill the gap between semiconductor back-end-of-line (BEOL) process and semi-additive process (SAP) and thereby (5) Improve the packaging performance at lower costs.
{"title":"Next Generation of 2-7 Micron Ultra-Small Microvias for 2.5D Panel Redistribution Layer by Using Laser and Photolithography Technologies","authors":"Fuhan Liu, Chandrasekharan Nair, Gaurav Khurana, A. Watanabe, Bartlet H. Deprospo, A. Kubo, C. Lin, T. Makita, Naoki Watanabe, R. Tummala","doi":"10.1109/ECTC.2019.00144","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00144","url":null,"abstract":"Microvia is the vertical interconnect structure for multi-layer redistribution layers (RDLs) in high-density interconnect (HDI) printed circuit boards (PCBs), HDI package substrates, 2.5D interposers and fan-out packages. Three technologies such as photolithography, UV laser and excimer laser have been used to form small microvias (≤ 20 µm diameter) in polymer dielectrics. All the three above mentioned technologies are studied and compared in the work presented in this paper. Photovia was first introduced by IBM for Surface Laminar Circuit technology and it has scaled down from 125 µm then to below 10 µm today. The smallest photovia demonstrated is 2 µm in diameter by using 365 nm photolithography in 5 µm thick TOK photo-imageable dielectric (PID) (IF4605) film. Photovias of 3 µm diameter were also demonstrated in 5 µm thick Taiyo Ink dielectric dry film material (PDM) which passed 1,500 thermal cycles (-55 C to 125 C). The limitation of photovia technology is the availability and cost of photo-sensitive dielectric materials with the required electrical, mechanical, thermal and chemical properties. The state-of-the-art microvia diameter is 20 µm by using conventional high-speed UV laser technologies. Multi-layer RDL with microvias and trenches of 4 µm feature sizes are simultaneously fabricated in a 7 µm thick Ajinomoto Build-up Film (ABF) with small fillers by using excimer laser and passed 1,000 thermal cycles (-55 C to 125 C). This paper demonstrates a novel picosecond UV laser technology to push the limits of low-cost UV laser technology by optimizing laser parameters and dielectric materials. The Cornerstone picosecond UV laser tool from ESI is capable of producing output power of 16W at 355 nm wavelength. The pulse duration is 5 ps which minimizes the heat-affected zone of polymer dielectric and the high (80 MHz) repetition rate enables this laser to be used in high throughput manufacturing processes. Microvias with minimum diameter of < 7 µm were fabricated in 5 µm thick ABF with small fillers and in 7 µm thick novel Panasonic low stress dielectric film-S (PLS-S), by using 355 nm picosecond UV laser tool. These ABF and PLS-S films are non-photosensitive dielectric materials. This is the first demonstration of very small microvias (< 7 µm) in polymer dielectrics using UV laser ablation. The motivation of this work is to address the high RDL interconnect density requirements for 2.5D interposer and high density (HD) fan-out packages. The next generation of low-cost, ultra-small microvias will (1) Increase the RDL I/O density, (2) Meet fine bump pitch requirements, (3) Reduce the metal layer count for package substrate RDL, (4) Fill the gap between semiconductor back-end-of-line (BEOL) process and semi-additive process (SAP) and thereby (5) Improve the packaging performance at lower costs.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"198 1","pages":"924-930"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79978779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nahid Aslani Amoli, Sridhar Sivapurapu, Rui-Bin Chen, Yi Zhou, M. Bellaredj, P. Kohl, S. Sitaraman, M. Swaminathan
Flexible hybrid electronics (FHE) is a promising technology enabling many applications in biomedical, communication, energy harvesting and internet of things (IoT) areas. To realize FHE applications, the components and devices used in the mentioned technologies need to be electrically characterized under various flexible conditions such as stretching, bending, twisting, and folding. Also, the strain analysis from the mechanical point of view needs to be conducted to justify the reliable applications of FHE under different flexible scenarios. In this paper, the design and electrical characterization of coplanar waveguides (CPWs) in flexible substrates such as Kapton polyimide and polyethylene terephthalate (PET) under uniaxial bending are studied and discussed. The fabricated lines were measured using a vector network analyzer (VNA) up to 8 GHz under both flat and bending conditions. Finite-element models (FEM) of CPW lines were created in ANSYS HFSS to capture the effect of bending on the CPW frequency response. In addition, the variations in the trace width and separations along the CPW lines were modeled accurately to capture the variations in the fabrication process and their effect on the CPW S-parameters in the flat condition. The finite element analysis of strain variation during bending was also performed and the relationship between strain variation and CPW performance was investigated. The bending of the CPW lines was carried out using two parallel plates that had a gap distance varying from 40 mm to 140 mm. The S-parameters were monitored in-situ while the substrate was under bending. The experimental results were compared against simulated results under both flat and bent configurations. Based on the conducted studies, correlation was achieved for the flat and bending scenarios between measurement and simulation results. Also, it was observed that the CPW line has better matching and lower losses compared with the flat case and tensile bending cases.
{"title":"Screen-Printed Flexible Coplanar Waveguide Transmission Lines: Multi-physics Modeling and Measurement","authors":"Nahid Aslani Amoli, Sridhar Sivapurapu, Rui-Bin Chen, Yi Zhou, M. Bellaredj, P. Kohl, S. Sitaraman, M. Swaminathan","doi":"10.1109/ECTC.2019.00044","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00044","url":null,"abstract":"Flexible hybrid electronics (FHE) is a promising technology enabling many applications in biomedical, communication, energy harvesting and internet of things (IoT) areas. To realize FHE applications, the components and devices used in the mentioned technologies need to be electrically characterized under various flexible conditions such as stretching, bending, twisting, and folding. Also, the strain analysis from the mechanical point of view needs to be conducted to justify the reliable applications of FHE under different flexible scenarios. In this paper, the design and electrical characterization of coplanar waveguides (CPWs) in flexible substrates such as Kapton polyimide and polyethylene terephthalate (PET) under uniaxial bending are studied and discussed. The fabricated lines were measured using a vector network analyzer (VNA) up to 8 GHz under both flat and bending conditions. Finite-element models (FEM) of CPW lines were created in ANSYS HFSS to capture the effect of bending on the CPW frequency response. In addition, the variations in the trace width and separations along the CPW lines were modeled accurately to capture the variations in the fabrication process and their effect on the CPW S-parameters in the flat condition. The finite element analysis of strain variation during bending was also performed and the relationship between strain variation and CPW performance was investigated. The bending of the CPW lines was carried out using two parallel plates that had a gap distance varying from 40 mm to 140 mm. The S-parameters were monitored in-situ while the substrate was under bending. The experimental results were compared against simulated results under both flat and bent configurations. Based on the conducted studies, correlation was achieved for the flat and bending scenarios between measurement and simulation results. Also, it was observed that the CPW line has better matching and lower losses compared with the flat case and tensile bending cases.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"45 1","pages":"249-257"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80268529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jinto George, D. Danovitch, A. Leblanc, Eric Savage, M. Ayukawa, Dexter Macaisa
The temperature sensitivity of CZT medical imaging devices precludes the use of traditional solder attach technologies for package interconnection. Continued advancement in electrically conductive adhesives (ECAs) has resulted in commercially available ultra-low temperature (<60°C) cure candidates that would be compatible with CZT device assembly. However, inherent to their low cure temperature is a rapid onset of room temperature polymerization and associated increase in viscosity. This quickly degrades printability and thereby manufacturing pot life. Conversely, ECA's with a longer pot life typically cure at an unacceptably higher temperature and have lower viscosities that are not compatible with screen printing. To address this dichotomy, we propose an approach that enables low temperature interconnection by initiating the cure process prior to material printing in the assembly process. The approach uses a short time, high temperature pre-heat of a high pot life material to initiate polymerization in a controlled fashion before it is interconnected to the temperature sensitive device then cured at an ultra-low temperature. The results demonstrate that the pre-treatment not only serves to shift the particular material's viscosity to a more acceptable range for screen printing, it also improves low temperature cure resistivity values from 21KΩ-cm to less than 1 mΩ-cm. At the same time, the pre-treatment maintains the long pot life of the material that favors its use in a volume-manufacturing environment. This approach opens the door for exploring a larger portfolio of electrical conductive adhesives to be used in low temperature interconnection applications.
{"title":"Pre-Cure Modification of Electrically Conductive Adhesive for Low Temperature Interconnection","authors":"Jinto George, D. Danovitch, A. Leblanc, Eric Savage, M. Ayukawa, Dexter Macaisa","doi":"10.1109/ECTC.2019.00-30","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00-30","url":null,"abstract":"The temperature sensitivity of CZT medical imaging devices precludes the use of traditional solder attach technologies for package interconnection. Continued advancement in electrically conductive adhesives (ECAs) has resulted in commercially available ultra-low temperature (<60°C) cure candidates that would be compatible with CZT device assembly. However, inherent to their low cure temperature is a rapid onset of room temperature polymerization and associated increase in viscosity. This quickly degrades printability and thereby manufacturing pot life. Conversely, ECA's with a longer pot life typically cure at an unacceptably higher temperature and have lower viscosities that are not compatible with screen printing. To address this dichotomy, we propose an approach that enables low temperature interconnection by initiating the cure process prior to material printing in the assembly process. The approach uses a short time, high temperature pre-heat of a high pot life material to initiate polymerization in a controlled fashion before it is interconnected to the temperature sensitive device then cured at an ultra-low temperature. The results demonstrate that the pre-treatment not only serves to shift the particular material's viscosity to a more acceptable range for screen printing, it also improves low temperature cure resistivity values from 21KΩ-cm to less than 1 mΩ-cm. At the same time, the pre-treatment maintains the long pot life of the material that favors its use in a volume-manufacturing environment. This approach opens the door for exploring a larger portfolio of electrical conductive adhesives to be used in low temperature interconnection applications.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"5 1","pages":"2117-2125"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81927017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Hsu, Chi-Yuan Chen, Stanley Lin, Ta-Jen Yu, NamJu Cho, M. Hsieh
With the fast growth in emerging technologies for mobile applications, packaging solutions are being driven by advanced Silicon (Si) nodes technology (down to 7nm), smaller form factor package designs, efficiency enhancement and lower power consumption. The flip chip chip scale package (fcCSP) has been widely adopted as the solution for mobile devices to satisfy these challenging requirements. In order to create a lower cost solution, the fcCSP uses the cost-effective combination of copper (Cu) pillar bumps, embedded trace substrate (ETS) technology, mass reflow (MR) chip attach and molded underfill (MUF) processes. Although the utilization of MR chip attach is a cost-effective process for flip chip package assembly, there is a high risk for a bump to trace short, especially for the designs with finer bump pitch and line width / line spacing (LW/LS) with an escaped trace. To reduce this risk, the laser assisted bonding (LAB) methodology is introduced to study the 7nm chip-package interaction (CPI) of an fcCSP with a 60µm bump pitch and escaped traces design in this paper. For the purpose of measuring the extremely low-k (ELK) performance in a 14x14mm fine pitch fcCSP with 7nm live die, the thunder test (two-times MR and quick temperature cycling (QTC) tests) as well as the hammer test with multi-reflow process (peak temperature at 260ºC) have been evaluated after performing LAB and MR chip attach methodologies. The results show that although both chip attach methodologies can pass the normal requirements of the thunder and hammer tests, the utilization of LAB technology can further enhance the strength of ELK and produce better yield performance. From these results, it is believed that LAB not only can guarantee assembly yield with less ELK damage risk in the examined 7nm fcCSP, but can also accommodate Si node and bump pitch reduction with a finer LW/LS substrate with escaped traces design.
{"title":"7nm Chip-Package Interaction Study on a Fine Pitch Flip Chip Package with Laser Assisted Bonding and Mass Reflow Technology","authors":"I. Hsu, Chi-Yuan Chen, Stanley Lin, Ta-Jen Yu, NamJu Cho, M. Hsieh","doi":"10.1109/ECTC.2019.00050","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00050","url":null,"abstract":"With the fast growth in emerging technologies for mobile applications, packaging solutions are being driven by advanced Silicon (Si) nodes technology (down to 7nm), smaller form factor package designs, efficiency enhancement and lower power consumption. The flip chip chip scale package (fcCSP) has been widely adopted as the solution for mobile devices to satisfy these challenging requirements. In order to create a lower cost solution, the fcCSP uses the cost-effective combination of copper (Cu) pillar bumps, embedded trace substrate (ETS) technology, mass reflow (MR) chip attach and molded underfill (MUF) processes. Although the utilization of MR chip attach is a cost-effective process for flip chip package assembly, there is a high risk for a bump to trace short, especially for the designs with finer bump pitch and line width / line spacing (LW/LS) with an escaped trace. To reduce this risk, the laser assisted bonding (LAB) methodology is introduced to study the 7nm chip-package interaction (CPI) of an fcCSP with a 60µm bump pitch and escaped traces design in this paper. For the purpose of measuring the extremely low-k (ELK) performance in a 14x14mm fine pitch fcCSP with 7nm live die, the thunder test (two-times MR and quick temperature cycling (QTC) tests) as well as the hammer test with multi-reflow process (peak temperature at 260ºC) have been evaluated after performing LAB and MR chip attach methodologies. The results show that although both chip attach methodologies can pass the normal requirements of the thunder and hammer tests, the utilization of LAB technology can further enhance the strength of ELK and produce better yield performance. From these results, it is believed that LAB not only can guarantee assembly yield with less ELK damage risk in the examined 7nm fcCSP, but can also accommodate Si node and bump pitch reduction with a finer LW/LS substrate with escaped traces design.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"53 1","pages":"289-293"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76722157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yu-An Shen, Shiqi Zhou, Jiahui Li, K. Tu, H. Nishikawa
Thermomigration has become a critical reliability issue in consumer electronic products because of Joule heating. To conduct heat away, it requires temperature gradient. Just 1°C difference across a microbump of 10 µm in diameter produces a temperature gradient of 1000 °C/cm, which can cause thermomigration, especially in low melting eutectic SnBi solder joints. However, the study of thermomigration in SnBi soler joints is hardly seen, not to mention the effect and the details. In this study, a Cu/Sn-58Bi/Cu joint with a 42 µm solder height, bonded by a reflow process, is examined for thermomigration with a thermal gradient of 1309 °C/cm. We report here that Bi atoms move from the hot end to the cold end, following the temperature gradient, it is the dominant diffusing species. The Sn atoms move from the cold end to the hot end. Under the assumption of constant volume, the Sn atoms are being squeezed by the Bi atoms at the cold end and have to make room for the Bi atoms, so they move to the hot end. Moreover, the formation of Cu-Sn intermetallic compound (IMC) layers at the cold and hot end site were symmetrical, unaffected by thermomigration. Additionally, finite-element-method (FEM) simulations showed that the phase separation of Bi and Sn has reduced current crowding regions, which affects the electromigration of the eutectic SnBi solder joints.
{"title":"Microstructure and Property Changes in Cu/Sn-58Bi/Cu Solder Joints During Thermomigration","authors":"Yu-An Shen, Shiqi Zhou, Jiahui Li, K. Tu, H. Nishikawa","doi":"10.1109/ECTC.2019.00307","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00307","url":null,"abstract":"Thermomigration has become a critical reliability issue in consumer electronic products because of Joule heating. To conduct heat away, it requires temperature gradient. Just 1°C difference across a microbump of 10 µm in diameter produces a temperature gradient of 1000 °C/cm, which can cause thermomigration, especially in low melting eutectic SnBi solder joints. However, the study of thermomigration in SnBi soler joints is hardly seen, not to mention the effect and the details. In this study, a Cu/Sn-58Bi/Cu joint with a 42 µm solder height, bonded by a reflow process, is examined for thermomigration with a thermal gradient of 1309 °C/cm. We report here that Bi atoms move from the hot end to the cold end, following the temperature gradient, it is the dominant diffusing species. The Sn atoms move from the cold end to the hot end. Under the assumption of constant volume, the Sn atoms are being squeezed by the Bi atoms at the cold end and have to make room for the Bi atoms, so they move to the hot end. Moreover, the formation of Cu-Sn intermetallic compound (IMC) layers at the cold and hot end site were symmetrical, unaffected by thermomigration. Additionally, finite-element-method (FEM) simulations showed that the phase separation of Bi and Sn has reduced current crowding regions, which affects the electromigration of the eutectic SnBi solder joints.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"43 1","pages":"2003-2008"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77045825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Inoue, A. Phommahaxay, A. Podpod, S. Suhard, Hitoshi Hoshino, B. Moeller, E. Sleeckx, Kenneth June Rebibis, Andy Miller, E. Beyne
Feasibility study of alternative dicing technologies for collective die to wafer direct bonding combined with wafer to wafer direct bonded dies has been performed. Several dicing technologies such as blade dicing, laser grooving + plasma dicing, laser grooving + stealth dicing and laser grooving from backside were evaluated for this integration scheme. For the case of blade diced dies, the collective die to wafer direct bonding are not succeeded. This was due to particle interruption, caused by remaining particles from dicing. For the case of laser grooving + plasma dicing and laser grooving from backside, successful die to wafer direct bonding were observed. However, the die edge was not bonded for the case of laser grooving + stealth dicing. This was attributed to the occurrence of the laser recast caused during laser grooving. Based on the characterization of dicing techniques for this approach, we have achieved successful integration of collective die to wafer bonding combined with wafer to wafer bonded dies.
{"title":"Advanced Dicing Technologies for Combination of Wafer to Wafer and Collective Die to Wafer Direct Bonding","authors":"F. Inoue, A. Phommahaxay, A. Podpod, S. Suhard, Hitoshi Hoshino, B. Moeller, E. Sleeckx, Kenneth June Rebibis, Andy Miller, E. Beyne","doi":"10.1109/ECTC.2019.00073","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00073","url":null,"abstract":"Feasibility study of alternative dicing technologies for collective die to wafer direct bonding combined with wafer to wafer direct bonded dies has been performed. Several dicing technologies such as blade dicing, laser grooving + plasma dicing, laser grooving + stealth dicing and laser grooving from backside were evaluated for this integration scheme. For the case of blade diced dies, the collective die to wafer direct bonding are not succeeded. This was due to particle interruption, caused by remaining particles from dicing. For the case of laser grooving + plasma dicing and laser grooving from backside, successful die to wafer direct bonding were observed. However, the die edge was not bonded for the case of laser grooving + stealth dicing. This was attributed to the occurrence of the laser recast caused during laser grooving. Based on the characterization of dicing techniques for this approach, we have achieved successful integration of collective die to wafer bonding combined with wafer to wafer bonded dies.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"151 1","pages":"437-445"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79509391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Saleem, R. Andersson, M. Bylund, Charlotte Goemare, Guilhem Pacot, M. Kabir, V. Desmaris
Complete on-chip fully solid-state 3D integrated capacitors using vertically aligned carbon nanofibers as electrodes to provide a large 3D surface in a MIM configuration have been manufactured and characterized in terms of capacitance per device footprint area, equivalent series resistance (ESR), breakdown voltage and leakage current. The entire manufacturing process of the capacitors is completely CMOS compatible, which along with the low device profile of about 4 µm makes the devices readily available for integration on a CMOS-chip, in 3D stacking, or redistribution layers in a 2.5D interposer technology. Capacitances of 200 nF/mm2, ESR of about 100 mΩ, breakdown voltages of 25 V and leakage current of the order of 0.004 A/F have been measured.
{"title":"Fully Solid-State Integrated Capacitors Based on Carbon Nanofibers and Dielectrics with Specific Capacitances Higher Than 200 nF/mm2","authors":"A. Saleem, R. Andersson, M. Bylund, Charlotte Goemare, Guilhem Pacot, M. Kabir, V. Desmaris","doi":"10.1109/ECTC.2019.00288","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00288","url":null,"abstract":"Complete on-chip fully solid-state 3D integrated capacitors using vertically aligned carbon nanofibers as electrodes to provide a large 3D surface in a MIM configuration have been manufactured and characterized in terms of capacitance per device footprint area, equivalent series resistance (ESR), breakdown voltage and leakage current. The entire manufacturing process of the capacitors is completely CMOS compatible, which along with the low device profile of about 4 µm makes the devices readily available for integration on a CMOS-chip, in 3D stacking, or redistribution layers in a 2.5D interposer technology. Capacitances of 200 nF/mm2, ESR of about 100 mΩ, breakdown voltages of 25 V and leakage current of the order of 0.004 A/F have been measured.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"240 1 1","pages":"1870-1876"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77029387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Dias, M. Kelly, D. Balaraman, Hideaki Shoji, Tomio Shiraiwa, K. Oh, Joonyoung Park
Automotive Grade 1 and 0 package requirements, defined by Automotive Electronics Council (AEC) Document AEC-100, require more severe temperature cycling and high temperature storage conditions to meet harsh automotive field requirements, such as a maximum 150°C device operating temperature, 15-year reliability and zero-defect quality level. Moreover, increased integration of device functionality to meet the new automotive requirements for in-vehicle networking, autonomous driving, infotainment and sensor integration are driving increases in die and package sizes. This paper provides an update on flip chip ball grid array (FCBGA) package development as quality and reliability requirements increase for larger and larger package form factors and approaches that should be taken to meet Grade 1/0 requirements. Package quality and wear-out failure modes and mechanisms experienced during extended reliability testing in Automotive Grade 2 and 3 package qualifications have identified thermomechanical stress and material degradation at high temperatures as key factors for focus in Grade 1/0 development. To achieve higher grade levels, key package substrate materials such as core, solder resist and build-up layers need to be evaluated as well as assembly materials such as underfills materials may need improvement. Mechanical simulation data of key material properties such as coefficient of thermal expansion (CTE), modulus of elasticity (E1) and glass transition temperature (Tg) of the substrate and assembly materials are used to provide guidance for the selection of substrate and assembly materials used in the design of experiments to meet Auto Grade 1 and 0 reliability requirements. Taguchi mechanical simulations results show that use of low CTE materials for the substrate core and build up material was beneficial in preventing SR cracking, UF cracking and bump cracking. Reliability stress results on design of experiments based on inputs from simulation resulted in developing a substrate and assembly material set that meets AEC100 solder resist (SR) Grade 1 and 0 package requirements on a 45-mm x 45-mm FCBGA.
汽车电子委员会(AEC)文件AEC-100定义的汽车1级和0级封装要求需要更严格的温度循环和高温存储条件，以满足苛刻的汽车领域要求，例如最高150°C的设备工作温度，15年的可靠性和零缺陷的质量水平。此外，为了满足汽车对车载网络、自动驾驶、信息娱乐和传感器集成的新要求，设备功能的集成度不断提高，推动了芯片和封装尺寸的增加。本文提供了倒装芯片球栅阵列(FCBGA)封装开发的最新进展，因为越来越大的封装尺寸和满足1/0级要求的方法对质量和可靠性的要求越来越高。在汽车2级和3级封装资格的扩展可靠性测试中，封装质量、磨损失效模式和机制已经确定，高温下的热机械应力和材料退化是1/0级开发重点关注的关键因素。为了达到更高的等级水平，需要评估关键封装基板材料，如核心，抗焊料和堆积层，以及组装材料，如下填充材料可能需要改进。利用基板和装配材料的热膨胀系数(CTE)、弹性模量(E1)、玻璃化转变温度(Tg)等关键材料性能的力学仿真数据，为实验设计中所使用的基板和装配材料的选择提供指导，以满足Auto Grade 1和0级可靠性要求。Taguchi力学模拟结果表明，采用低CTE材料作为基板芯和堆焊材料有利于防止SR开裂、UF开裂和凹凸开裂。基于仿真输入的实验设计的可靠性应力结果导致开发出符合AEC100耐焊(SR) 1级和0级封装要求的45 mm x 45 mm FCBGA基板和组装材料组。
{"title":"Challenges and Approaches to Developing Automotive Grade 1/0 FCBGA Package Capability","authors":"R. Dias, M. Kelly, D. Balaraman, Hideaki Shoji, Tomio Shiraiwa, K. Oh, Joonyoung Park","doi":"10.1109/ECTC.2019.00032","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00032","url":null,"abstract":"Automotive Grade 1 and 0 package requirements, defined by Automotive Electronics Council (AEC) Document AEC-100, require more severe temperature cycling and high temperature storage conditions to meet harsh automotive field requirements, such as a maximum 150°C device operating temperature, 15-year reliability and zero-defect quality level. Moreover, increased integration of device functionality to meet the new automotive requirements for in-vehicle networking, autonomous driving, infotainment and sensor integration are driving increases in die and package sizes. This paper provides an update on flip chip ball grid array (FCBGA) package development as quality and reliability requirements increase for larger and larger package form factors and approaches that should be taken to meet Grade 1/0 requirements. Package quality and wear-out failure modes and mechanisms experienced during extended reliability testing in Automotive Grade 2 and 3 package qualifications have identified thermomechanical stress and material degradation at high temperatures as key factors for focus in Grade 1/0 development. To achieve higher grade levels, key package substrate materials such as core, solder resist and build-up layers need to be evaluated as well as assembly materials such as underfills materials may need improvement. Mechanical simulation data of key material properties such as coefficient of thermal expansion (CTE), modulus of elasticity (E1) and glass transition temperature (Tg) of the substrate and assembly materials are used to provide guidance for the selection of substrate and assembly materials used in the design of experiments to meet Auto Grade 1 and 0 reliability requirements. Taguchi mechanical simulations results show that use of low CTE materials for the substrate core and build up material was beneficial in preventing SR cracking, UF cracking and bump cracking. Reliability stress results on design of experiments based on inputs from simulation resulted in developing a substrate and assembly material set that meets AEC100 solder resist (SR) Grade 1 and 0 package requirements on a 45-mm x 45-mm FCBGA.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"14 1","pages":"163-167"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82559912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Gschwandl, P. Fuchs, T. Antretter, M. Pfost, I. Mitev, Tao Qi, T. Krivec, A. Schingale, M. Decker
The shift of the automotive industry towards e-mobility results in a strong demand for highly reliable power electronics. A major goal in their design is to improve the thermal management of all components. Most commonly power electronics are subject to high temperature loads, either internally generated by an active part (semiconductor) or externally applied. Depending on the materials used, such as metals, polymers, etc., thermo-mechanical stresses will arise and promote different failure mechanisms. The complexity of the loading situation, especially in the case of internally generated loads, calls for a sequential approach, consisting of a Finite Volume Method (FVM) and a Finite Element Analysis (FEA) for the lifetime assessment of these components. Using this methodology, the highly complex temperature distribution of any power package can be determined. Consequently, accurate results for the thermo-mechanical stress situation from chip to power packages are deduced and critical spots are identified. Based on the obtained stress fields, an enhanced lifetime assessment of power packages can be performed. The proposed methodology is validated on a standard TO-263 package for a short circuit loading scenario.
{"title":"A Sequential Finite Volume Method / Finite Element Analysis of a Power Electronic Semiconductor Chip","authors":"M. Gschwandl, P. Fuchs, T. Antretter, M. Pfost, I. Mitev, Tao Qi, T. Krivec, A. Schingale, M. Decker","doi":"10.1109/ECTC.2019.00232","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00232","url":null,"abstract":"The shift of the automotive industry towards e-mobility results in a strong demand for highly reliable power electronics. A major goal in their design is to improve the thermal management of all components. Most commonly power electronics are subject to high temperature loads, either internally generated by an active part (semiconductor) or externally applied. Depending on the materials used, such as metals, polymers, etc., thermo-mechanical stresses will arise and promote different failure mechanisms. The complexity of the loading situation, especially in the case of internally generated loads, calls for a sequential approach, consisting of a Finite Volume Method (FVM) and a Finite Element Analysis (FEA) for the lifetime assessment of these components. Using this methodology, the highly complex temperature distribution of any power package can be determined. Consequently, accurate results for the thermo-mechanical stress situation from chip to power packages are deduced and critical spots are identified. Based on the obtained stress fields, an enhanced lifetime assessment of power packages can be performed. The proposed methodology is validated on a standard TO-263 package for a short circuit loading scenario.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"43 1","pages":"1509-1514"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81784238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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