Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776532
M. Kim, N. Harada, Y. Kikuchi, J. Boemmels, J. Mitard, T. Huynh-Bao, P. Matagne, Z. Tao, W. Li, K. Devriendt, L. Ragnarsson, C. Lorant, F. Sebaai, C. Porret, E. Rosseel, A. Dangol, D. Batuk, G. Martinez-Alanis, J. Geypen, N. Jourdan, A. Sepúlveda, H. Puliyalil, G. Jamieson, M. H. van der Veen, L. Teugels, Z. El-Mekki, E. Altamirano-Sanchez, Y. Li, H. Nakamura, D. Mocuta, F. Masuoka
For the first time, we establish a fabrication process flow of an EUV-era ultra-density 6-surrounding-gate-transistor SRAM with $0.0205 mu text{m}^{2}$ unit cell area and demonstrate nMOS surrounding-gate-transistor function. In this paper, 6-surrounding-gate-transistor SRAM design layout is shown, and the fabrication process flow and key process steps are explained in detail. NMOS functional device characteristics of surrounding-gate-transistor is analyzed.
我们首次建立了euv时代的超密度6-包围栅极SRAM的制造工艺流程，单元面积为0.0205 mu text{m}^{2}$，并演示了nMOS包围栅极晶体管的功能。本文给出了六围栅晶体管SRAM的设计版图，并对其制作工艺流程和关键工艺步骤进行了详细说明。分析了围栅晶体管的NMOS功能器件特性。
{"title":"12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices","authors":"M. Kim, N. Harada, Y. Kikuchi, J. Boemmels, J. Mitard, T. Huynh-Bao, P. Matagne, Z. Tao, W. Li, K. Devriendt, L. Ragnarsson, C. Lorant, F. Sebaai, C. Porret, E. Rosseel, A. Dangol, D. Batuk, G. Martinez-Alanis, J. Geypen, N. Jourdan, A. Sepúlveda, H. Puliyalil, G. Jamieson, M. H. van der Veen, L. Teugels, Z. El-Mekki, E. Altamirano-Sanchez, Y. Li, H. Nakamura, D. Mocuta, F. Masuoka","doi":"10.23919/VLSIT.2019.8776532","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776532","url":null,"abstract":"For the first time, we establish a fabrication process flow of an EUV-era ultra-density 6-surrounding-gate-transistor SRAM with $0.0205 mu text{m}^{2}$ unit cell area and demonstrate nMOS surrounding-gate-transistor function. In this paper, 6-surrounding-gate-transistor SRAM design layout is shown, and the fabrication process flow and key process steps are explained in detail. NMOS functional device characteristics of surrounding-gate-transistor is analyzed.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"75 1","pages":"T198-T199"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85829318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776544
S. Okumura, M. Yabuuchi, K. Hijioka, Koichi Nose
A Processing-In-Memory (PIM) accelerator with ternary SRAM is proposed for low-power, large-scale deep neural network (DNN) processing. The accelerator consists of Ternary Neural Arithmetic Memory (TNAM) which is capable of bit-scalable MAC (multiply and accumulation) operation in accordance with target accuracy and power limit. An ADC less readout circuits to reduce analog-digital conversion power and a system-level variation avoidance technique utilizing features of TNAM are also proposed. A test chip with large-scale PIM is fabricated and successfully operate convolutional neural networks (CNNs) with 8.8TOPS/W and highest accuracy and area density among recent SRAM-type PIMs are obtained.
{"title":"A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2","authors":"S. Okumura, M. Yabuuchi, K. Hijioka, Koichi Nose","doi":"10.23919/VLSIT.2019.8776544","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776544","url":null,"abstract":"A Processing-In-Memory (PIM) accelerator with ternary SRAM is proposed for low-power, large-scale deep neural network (DNN) processing. The accelerator consists of Ternary Neural Arithmetic Memory (TNAM) which is capable of bit-scalable MAC (multiply and accumulation) operation in accordance with target accuracy and power limit. An ADC less readout circuits to reduce analog-digital conversion power and a system-level variation avoidance technique utilizing features of TNAM are also proposed. A test chip with large-scale PIM is fabricated and successfully operate convolutional neural networks (CNNs) with 8.8TOPS/W and highest accuracy and area density among recent SRAM-type PIMs are obtained.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"336 1","pages":"C248-C249"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86790236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776563
P. Kanhaiya, C. Lau, G. Hills, M. Bishop, M. Shulaker
We experimentally demonstrate the first static random-access memory (SRAM) arrays based on carbon nanotube (CNT) field-effect transistors (CNFETs). We demonstrate full 1 Kbit 6 transistor (6T) SRAM arrays fabricated with CNFET CMOS (totalling 6,144 p-and n-type CNFETs), with all 1,024 cells functioning correctly without any per-unit customization. We demonstrate robust operation by writing and reading multiple patterns to the Kbit arrays and characterize single-cell SRAM variability (write and read margins) and repeat cycling of cells. Due to low-temperature BEOL-compatible processing, CNFET SRAM enables new opportunities for digital systems, since: (1) CNFET SRAM can be fabricated directly on top of computing logic, and (2) buried power rails (i.e., as in our demonstration where the power rails are fabricated underneath the FET) can potentially enable smaller-area SRAM layouts.
{"title":"1 Kbit 6T SRAM Arrays in Carbon Nanotube FET CMOS","authors":"P. Kanhaiya, C. Lau, G. Hills, M. Bishop, M. Shulaker","doi":"10.23919/VLSIT.2019.8776563","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776563","url":null,"abstract":"We experimentally demonstrate the first static random-access memory (SRAM) arrays based on carbon nanotube (CNT) field-effect transistors (CNFETs). We demonstrate full 1 Kbit 6 transistor (6T) SRAM arrays fabricated with CNFET CMOS (totalling 6,144 p-and n-type CNFETs), with all 1,024 cells functioning correctly without any per-unit customization. We demonstrate robust operation by writing and reading multiple patterns to the Kbit arrays and characterize single-cell SRAM variability (write and read margins) and repeat cycling of cells. Due to low-temperature BEOL-compatible processing, CNFET SRAM enables new opportunities for digital systems, since: (1) CNFET SRAM can be fabricated directly on top of computing logic, and (2) buried power rails (i.e., as in our demonstration where the power rails are fabricated underneath the FET) can potentially enable smaller-area SRAM layouts.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"1 1","pages":"T54-T55"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77582839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776569
Ming-Hung Wu, Ming-Chun Hong, Chih-Cheng Chang, P. Sahu, Jeng-Hua Wei, Heng-Yuan Lee, Shyh-Shyuan Shcu, T. Hou
This work reports the complete framework from device to architecture for deep learning acceleration in an all-spin artificial neural network (ANN) built by highly manufacturable STT-MRAM technology. The most compact analog integrate-and-fire neuron reported to date is developed based on the back-hopping oscillation in magnetic tunnel junctions. This novel device is unique because it performs numerous essential neural functions simultaneously, including current integration, voltage spike generation, state reset, and 4-bit precision. The device itself is also a stochastic binary synapse, and thus eases the implementation of the compact all-spin ANN with high accuracy for online training.
{"title":"Extremely Compact Integrate-and-Fire STT-MRAM Neuron: A Pathway toward All-Spin Artificial Deep Neural Network","authors":"Ming-Hung Wu, Ming-Chun Hong, Chih-Cheng Chang, P. Sahu, Jeng-Hua Wei, Heng-Yuan Lee, Shyh-Shyuan Shcu, T. Hou","doi":"10.23919/VLSIT.2019.8776569","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776569","url":null,"abstract":"This work reports the complete framework from device to architecture for deep learning acceleration in an all-spin artificial neural network (ANN) built by highly manufacturable STT-MRAM technology. The most compact analog integrate-and-fire neuron reported to date is developed based on the back-hopping oscillation in magnetic tunnel junctions. This novel device is unique because it performs numerous essential neural functions simultaneously, including current integration, voltage spike generation, state reset, and 4-bit precision. The device itself is also a stochastic binary synapse, and thus eases the implementation of the compact all-spin ANN with high accuracy for online training.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"15 1","pages":"T34-T35"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77614543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776511
M. Cai, Hyunwoo Park, Jackie Yang, Youseok Suh, Jun Chen, Yandong Gao, Lunwei Chang, John Zhu, S. C. Song, Jihong Choi, Gary Chen, Bo Yu, Xiao-Yong Wang, V. Huang, Gudoor Reddy, Nagaraj Kelageri, D. Kidd, P. Pénzes, W. Chung, S. Yang, S.B. Lee, B. Tien, G. Nallapati, S. Wu, P. Chidambaram
We report on Qualcomm® Snapdragon™ SDM855 mobile SoC and world's first commercial 5G platform using industry-leading 7nm FINFET technologies. SDM855 exhibits $> 30%$ CPU performance gain over the previous generation thanks to a new design architecture enabled by dual poly pitch process integration. Low voltage operation and tight spread in power consumption has been achieved through process and design co-development, delivering a high performance and low power solution for both mobile and AI applications. Extending the 7nm technology with 2nd-year process enhancement demonstrates up to 50mV CPU Vmin reduction without any change to design rules, which paves the road for an integrated 5G mobile platform with $> 10text{Gbps}$ connectivity.
{"title":"7nm Mobile SoC and 5G Platform Technology and Design Co-Development for PPA and Manufacturability","authors":"M. Cai, Hyunwoo Park, Jackie Yang, Youseok Suh, Jun Chen, Yandong Gao, Lunwei Chang, John Zhu, S. C. Song, Jihong Choi, Gary Chen, Bo Yu, Xiao-Yong Wang, V. Huang, Gudoor Reddy, Nagaraj Kelageri, D. Kidd, P. Pénzes, W. Chung, S. Yang, S.B. Lee, B. Tien, G. Nallapati, S. Wu, P. Chidambaram","doi":"10.23919/VLSIT.2019.8776511","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776511","url":null,"abstract":"We report on Qualcomm® Snapdragon™ SDM855 mobile SoC and world's first commercial 5G platform using industry-leading 7nm FINFET technologies. SDM855 exhibits $> 30%$ CPU performance gain over the previous generation thanks to a new design architecture enabled by dual poly pitch process integration. Low voltage operation and tight spread in power consumption has been achieved through process and design co-development, delivering a high performance and low power solution for both mobile and AI applications. Extending the 7nm technology with 2nd-year process enhancement demonstrates up to 50mV CPU Vmin reduction without any change to design rules, which paves the road for an integrated 5G mobile platform with $> 10text{Gbps}$ connectivity.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"40 1","pages":"T104-T105"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74797451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776513
P. Schuddinck, O. Zografos, P. Weckx, P. Matagne, S. Sarkar, Y. Sherazi, R. Baert, D. Jang, D. Yakimets, A. Gupta, B. Parvais, J. Ryckaert, D. Verkest, A. Mocuta
The structure of the complementary FET (CFET) with NMOS stacked on top of PMOS, inherently yields standard cells and SRAM cells with 25% smaller layout area, 25% higher pin density and 2x higher routing flexibility than FinFET with same overall active footprint. Moreover, our work, based on advanced modelling, demonstrates that 4 track CFET can match and even outperform 5 track FinFET; without the need to lower S/D contact resistivity down to $5text{e}-10Omega.text{cm}^{2}$ or to elevate the channel stress up to 2GPa. All gains in power-performance-area at circuit-level are maintained at block-level, making 4 track CFET a suitable candidate for N3 & N2 technologies. Keywords: CFET, scaling, S/D engineering, Pi-gate.
{"title":"Device-, Circuit- & Block-level evaluation of CFET in a 4 track library","authors":"P. Schuddinck, O. Zografos, P. Weckx, P. Matagne, S. Sarkar, Y. Sherazi, R. Baert, D. Jang, D. Yakimets, A. Gupta, B. Parvais, J. Ryckaert, D. Verkest, A. Mocuta","doi":"10.23919/VLSIT.2019.8776513","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776513","url":null,"abstract":"The structure of the complementary FET (CFET) with NMOS stacked on top of PMOS, inherently yields standard cells and SRAM cells with 25% smaller layout area, 25% higher pin density and 2x higher routing flexibility than FinFET with same overall active footprint. Moreover, our work, based on advanced modelling, demonstrates that 4 track CFET can match and even outperform 5 track FinFET; without the need to lower S/D contact resistivity down to $5text{e}-10Omega.text{cm}^{2}$ or to elevate the channel stress up to 2GPa. All gains in power-performance-area at circuit-level are maintained at block-level, making 4 track CFET a suitable candidate for N3 & N2 technologies. Keywords: CFET, scaling, S/D engineering, Pi-gate.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"38 1","pages":"T204-T205"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91038183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776522
Zhihong Liu, Hanlin Xie, K. Lee, C. S. Tan, G. Ng, E. Fitzgerald
GaN-on-Si has revealed its great potential for next-generation power electronics applications, however, there remains a challenge in increasing the breakdown voltage $(BV_{text{off}})$ due to the limit of the GaN epilayer thickness on large size wafers. In this work we propose a GaN-on-Insulator (GNOI)-on-Si structure to address this issue. A 200 mm GNOI-on-Si wafer was prepared through removing the original Si substrate of a GaN-on-Si wafer and bonding onto a fresh SiO2/Si substrate. HEMTs were fabricated with measured $BV_{text{off}}$ much larger than those on GaN-on-Si. Record high $BV text{off}$ up to 2200 V and high figure-of-merit (FOM) $BV_{off^2}/R_{text{on, sp}}$ up to 1.87 GW/cm2 have been achieved in the HEMTs on a 200 mm GNOI-on-Si wafer with a thin GaN epilayer of $3.2 {mu m}$.
{"title":"GaN HEMTs with Breakdown Voltage of 2200 V Realized on a 200 mm GaN-on-Insulator(GNOI)-on-Si Wafer","authors":"Zhihong Liu, Hanlin Xie, K. Lee, C. S. Tan, G. Ng, E. Fitzgerald","doi":"10.23919/VLSIT.2019.8776522","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776522","url":null,"abstract":"GaN-on-Si has revealed its great potential for next-generation power electronics applications, however, there remains a challenge in increasing the breakdown voltage $(BV_{text{off}})$ due to the limit of the GaN epilayer thickness on large size wafers. In this work we propose a GaN-on-Insulator (GNOI)-on-Si structure to address this issue. A 200 mm GNOI-on-Si wafer was prepared through removing the original Si substrate of a GaN-on-Si wafer and bonding onto a fresh SiO2/Si substrate. HEMTs were fabricated with measured $BV_{text{off}}$ much larger than those on GaN-on-Si. Record high $BV text{off}$ up to 2200 V and high figure-of-merit (FOM) $BV_{off^2}/R_{text{on, sp}}$ up to 1.87 GW/cm2 have been achieved in the HEMTs on a 200 mm GNOI-on-Si wafer with a thin GaN epilayer of $3.2 {mu m}$.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"47 1","pages":"T242-T243"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88314157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776506
S. Srinivasa, Yung-Ning Tu, Xin Si, Cheng-Xin Xue, Chun-Ying Lee, F. Hsueh, Chane-Hone Shen, J. Shieh, W. Yeh, A. Ramanathan, M. Ho, J. Sampson, Meng-Fan Chang, V. Narayanan
This paper presents the first monolithic 3D two-layer reconfigurable SRAM macro capable of executing multiple Compute-in-Memory (CiM) tasks as part of data readout. Fabricated using low cost FinFET based 3D+-IC, the SRAM offers concurrent data read from both layers and write from layer 2 with 0.4V $text{V}_{text{dd}min}$ 12.8x improved computation latency is achieved as compared to near memory computation of successive Boolean operations.
{"title":"Monolithic 3D+ -IC based Reconfigurable Compute-in-Memory SRAM Macro","authors":"S. Srinivasa, Yung-Ning Tu, Xin Si, Cheng-Xin Xue, Chun-Ying Lee, F. Hsueh, Chane-Hone Shen, J. Shieh, W. Yeh, A. Ramanathan, M. Ho, J. Sampson, Meng-Fan Chang, V. Narayanan","doi":"10.23919/VLSIT.2019.8776506","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776506","url":null,"abstract":"This paper presents the first monolithic 3D two-layer reconfigurable SRAM macro capable of executing multiple Compute-in-Memory (CiM) tasks as part of data readout. Fabricated using low cost FinFET based 3D+-IC, the SRAM offers concurrent data read from both layers and write from layer 2 with 0.4V $text{V}_{text{dd}min}$ 12.8x improved computation latency is achieved as compared to near memory computation of successive Boolean operations.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"103 1","pages":"T32-T33"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80297739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776539
Kaizhen Han, Ying Wu, Y. Huang, Shengqiang Xu, Annie Kumar, E. Kong, Yuye Kang, Jishen Zhang, Chengkuan Wang, Haiwen Xu, Chen Sun, X. Gong
For the first time, complementary FinFETs and complementary tunneling FinFETs (TFFETs), with fin width $(W_{Fin})$ of 20 nm and fin height $(H_{{fin}})$ of 50 nm, were co-integrated on the same substrate, enabled by the formation of high-quality GeSn-on-insulator (GeSnOI) substrate with 200 mm wafer size. Decent electrical characteristics were realized for both GeSn n-and p-channel FinFETs and TFFETs. We also performed simulation studies to show the promise of the GeSnOI platform, which is not only able to suppress the off-state leakage current and improve the $I_{on}/I_{off}$ ratio of tunneling FETs, but can also provide the powerful flexibility of using a back bias to achieve superior electrical characteristics beyond the benefits of incorporating Sn into Ge.
通过形成200 mm晶圆尺寸的高质量GeSnOI衬底，首次将翅片宽度$(W_{fin})$为20 nm，翅片高度$(H_{{fin}})$为50 nm的互补finfet和互补隧道finfet (tffet)在同一衬底上共集成。GeSn n沟道和p沟道finfet以及tffet均实现了良好的电特性。我们还进行了仿真研究，以显示GeSnOI平台的前景，该平台不仅能够抑制关态泄漏电流，提高隧道fet的$ i {on}/ $ i {off}}比值，而且还可以提供强大的灵活性，使用反偏置来实现超越将Sn加入Ge的好处的优越电气特性。
{"title":"First Demonstration of Complementary FinFETs and Tunneling FinFETs Co-Integrated on a 200 mm GeSnOI Substrate: A Pathway towards Future Hybrid Nano-electronics Systems","authors":"Kaizhen Han, Ying Wu, Y. Huang, Shengqiang Xu, Annie Kumar, E. Kong, Yuye Kang, Jishen Zhang, Chengkuan Wang, Haiwen Xu, Chen Sun, X. Gong","doi":"10.23919/VLSIT.2019.8776539","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776539","url":null,"abstract":"For the first time, complementary FinFETs and complementary tunneling FinFETs (TFFETs), with fin width $(W_{Fin})$ of 20 nm and fin height $(H_{{fin}})$ of 50 nm, were co-integrated on the same substrate, enabled by the formation of high-quality GeSn-on-insulator (GeSnOI) substrate with 200 mm wafer size. Decent electrical characteristics were realized for both GeSn n-and p-channel FinFETs and TFFETs. We also performed simulation studies to show the promise of the GeSnOI platform, which is not only able to suppress the off-state leakage current and improve the $I_{on}/I_{off}$ ratio of tunneling FETs, but can also provide the powerful flexibility of using a back bias to achieve superior electrical characteristics beyond the benefits of incorporating Sn into Ge.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"74 1","pages":"T182-T183"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86916863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776487
S. Dutta, A. Saha, P. Panda, W. Chakraborty, J. Gomez, A. Khanna, S. Gupta, K. Roy, S. Datta
Biologically plausible mechanism like homeostasis compliments Hebbian learning to allow unsupervised learning in spiking neural networks [1]. In this work, we propose a novel ferroelectric-based quasi-LIF neuron that induces intrinsic homeostasis. We experimentally characterize and perform phase-field simulations to delineate the non-trivial transient polarization relaxation mechanism associated with multi-domain interaction in poly-crystalline ferroelectric, such as Zr doped $text{HfO}_{2}$, that underlines the Q-LIF behavior. Network level simulations with the Q-LIF neuron model exhibits a 2.3x reduction in firing rate compared to traditional LIF neuron while maintaining iso-accuracy of 84-85% across varying network sizes. Such an energy-efficient hardware for spiking neuron can enable ultra-low power data processing in energy constrained environments suitable for edge-intelligence.
{"title":"Biologically Plausible Ferroelectric Quasi-Leaky Integrate and Fire Neuron","authors":"S. Dutta, A. Saha, P. Panda, W. Chakraborty, J. Gomez, A. Khanna, S. Gupta, K. Roy, S. Datta","doi":"10.23919/VLSIT.2019.8776487","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776487","url":null,"abstract":"Biologically plausible mechanism like homeostasis compliments Hebbian learning to allow unsupervised learning in spiking neural networks [1]. In this work, we propose a novel ferroelectric-based quasi-LIF neuron that induces intrinsic homeostasis. We experimentally characterize and perform phase-field simulations to delineate the non-trivial transient polarization relaxation mechanism associated with multi-domain interaction in poly-crystalline ferroelectric, such as Zr doped $text{HfO}_{2}$, that underlines the Q-LIF behavior. Network level simulations with the Q-LIF neuron model exhibits a 2.3x reduction in firing rate compared to traditional LIF neuron while maintaining iso-accuracy of 84-85% across varying network sizes. Such an energy-efficient hardware for spiking neuron can enable ultra-low power data processing in energy constrained environments suitable for edge-intelligence.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"6 1","pages":"T140-T141"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88010137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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