Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776516
W. Chien, H. Ho, C. Yeh, C.H. Yang, H. Cheng, W. Kim, I. Kuo, L. Gignac, E. Lai, N. Gong, Y. Chou, C. Cheng, Y. Lin, J. Papalia, F. Carta, A. Rav, R. Bruce, M. Briahtxky, H. Lung
We present a scaling study toward lZnm node 3D Cross-point PCM (XPCM) for Storage Class Memory (SCM) applications. The low operation current, and low metal line loading resistance are desired to avoid a wide operation voltage distribution in a cross-point array. For the first time, AC threshold voltage (Vth) of 1S1R OTS-PCM was studied, which will impact the operation scheme. To achieve Tera bits per chip density, six layers 1Znm 3D XPCM with OTS showing high Vth and low leakage current, and scalable periphery circuit are required.
我们提出了一种用于存储类存储器(SCM)应用的lZnm节点三维交叉点PCM (XPCM)的缩放研究。低工作电流和低金属线负载电阻是为了避免在交叉点阵列中的宽工作电压分布。首次研究了1S1R OTS-PCM的交流阈值电压(Vth)对运行方案的影响。为了达到每芯片Tera位密度，需要6层具有高电压和低漏电流的具有OTS的1Znm 3D XPCM，以及可扩展的外围电路。
{"title":"Comprehensive Scaling Study on 3D Cross-Point PCM toward 1Znm Node for SCM Applications","authors":"W. Chien, H. Ho, C. Yeh, C.H. Yang, H. Cheng, W. Kim, I. Kuo, L. Gignac, E. Lai, N. Gong, Y. Chou, C. Cheng, Y. Lin, J. Papalia, F. Carta, A. Rav, R. Bruce, M. Briahtxky, H. Lung","doi":"10.23919/VLSIT.2019.8776516","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776516","url":null,"abstract":"We present a scaling study toward lZnm node 3D Cross-point PCM (XPCM) for Storage Class Memory (SCM) applications. The low operation current, and low metal line loading resistance are desired to avoid a wide operation voltage distribution in a cross-point array. For the first time, AC threshold voltage (Vth) of 1S1R OTS-PCM was studied, which will impact the operation scheme. To achieve Tera bits per chip density, six layers 1Znm 3D XPCM with OTS showing high Vth and low leakage current, and scalable periphery circuit are required.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"30 1","pages":"T60-T61"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82850790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776497
K. Ni, W. Chakraborty, Jeffrey A. Smith, B. Grisafe, S. Datta
In this work, we present a comprehensive Kinetic Monte Carlo (KMC) modeling based statistical framework to evaluate the device-to-device variation of thin-film HfO2 ferroelectric FET (FeFET). We conclude that the closing of the memory window in a FeFET array with device scaling can be attributed to: 1) limited number of domains; 2) variation among domains; 3) intrinsic stochasticity of individual domain switching. To enable further scaling of FeFET, co-optimization approaches from material, process, and device operation to control variation are proposed: i) increase the number of domains through material/process optimization (e.g. decrease of deposition temperature, etc.); ii) improve the uniformity of domains (e.g. minimizing the domain size variation and defect distribution, etc.); iii) increase the pulse amplitude/width to ensure deterministic switching of individual domains.
{"title":"Fundamental Understanding and Control of Device-to-Device Variation in Deeply Scaled Ferroelectric FETs","authors":"K. Ni, W. Chakraborty, Jeffrey A. Smith, B. Grisafe, S. Datta","doi":"10.23919/VLSIT.2019.8776497","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776497","url":null,"abstract":"In this work, we present a comprehensive Kinetic Monte Carlo (KMC) modeling based statistical framework to evaluate the device-to-device variation of thin-film HfO2 ferroelectric FET (FeFET). We conclude that the closing of the memory window in a FeFET array with device scaling can be attributed to: 1) limited number of domains; 2) variation among domains; 3) intrinsic stochasticity of individual domain switching. To enable further scaling of FeFET, co-optimization approaches from material, process, and device operation to control variation are proposed: i) increase the number of domains through material/process optimization (e.g. decrease of deposition temperature, etc.); ii) improve the uniformity of domains (e.g. minimizing the domain size variation and defect distribution, etc.); iii) increase the pulse amplitude/width to ensure deterministic switching of individual domains.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"3 1","pages":"T40-T41"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90871490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776526
Dae-Myeong Geum, Sanghyeon Kim, S. Kim, S. Kang, J. Kyhm, J. Song, W. Choi, E. Yoon
Multicolor photodetectors (PDs) by using bulk p-i-n based visible GaAs and near-infrared (IR) InGaAs PD have been successfully fabricated via monolithic integration by wafer bonding and epitaxial lift-off. It showed high-performance individual operation comparable to that of bulk PDs with tight vertical alignment on a single substrate for future high-resolution multicolor PDs. At the same time, it covered a broad wavelength range from visible to IR.
{"title":"Monolithic lntegratIon of GaAs//InGaAs photodetectors for multicolor detection","authors":"Dae-Myeong Geum, Sanghyeon Kim, S. Kim, S. Kang, J. Kyhm, J. Song, W. Choi, E. Yoon","doi":"10.23919/VLSIT.2019.8776526","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776526","url":null,"abstract":"Multicolor photodetectors (PDs) by using bulk p-i-n based visible GaAs and near-infrared (IR) InGaAs PD have been successfully fabricated via monolithic integration by wafer bonding and epitaxial lift-off. It showed high-performance individual operation comparable to that of bulk PDs with tight vertical alignment on a single substrate for future high-resolution multicolor PDs. At the same time, it covered a broad wavelength range from visible to IR.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"1 1","pages":"T248-T249"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79933602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776485
Bonan Yan, Qing Yang, Wei-Hao Chen, Kung-Tang Chang, Jian-Wei Su, Chien-Hua Hsu, Sih-Han Li, Heng-Yuan Lee, S. Sheu, M. Ho, Qing Wu, Meng-Fan Chang, Yiran Chen, Hai Helen Li
This work presents a hybrid CMOS-RRAM integration of spiking nonvolatile computing-in-memory (nvCIM) processing engine (PE) that includes a 64Kb RRAM macro and a novel in situ nonlinear activation (ISNA) module. We integrate the computing controller and nonlinear activation function on-chip to compute convolutional or fully-connected neural network. ISNA merges A/D conversion and activation computation by leveraging its nonlinear working region. This eliminates the need for additional circuits to realize nonlinearity and reduces area by 43.7x w.r.t. the ADC scheme. The activation precision of ISNA can be configured from 1 to 8 bits to balance throughput, accuracy and power efficiency. The measurement of 4-layer LeNet shows such optimization improves 23.1% of computing speed via compromising a 2.5% relative accuracy drop. The proposed nvCIM PE achieves 16.9 TOPS/W power efficiency and a maximum spike frequency of 99.24 MHz.
{"title":"RRAM-based Spiking Nonvolatile Computing-In-Memory Processing Engine with Precision-Configurable In Situ Nonlinear Activation","authors":"Bonan Yan, Qing Yang, Wei-Hao Chen, Kung-Tang Chang, Jian-Wei Su, Chien-Hua Hsu, Sih-Han Li, Heng-Yuan Lee, S. Sheu, M. Ho, Qing Wu, Meng-Fan Chang, Yiran Chen, Hai Helen Li","doi":"10.23919/VLSIT.2019.8776485","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776485","url":null,"abstract":"This work presents a hybrid CMOS-RRAM integration of spiking nonvolatile computing-in-memory (nvCIM) processing engine (PE) that includes a 64Kb RRAM macro and a novel in situ nonlinear activation (ISNA) module. We integrate the computing controller and nonlinear activation function on-chip to compute convolutional or fully-connected neural network. ISNA merges A/D conversion and activation computation by leveraging its nonlinear working region. This eliminates the need for additional circuits to realize nonlinearity and reduces area by 43.7x w.r.t. the ADC scheme. The activation precision of ISNA can be configured from 1 to 8 bits to balance throughput, accuracy and power efficiency. The measurement of 4-layer LeNet shows such optimization improves 23.1% of computing speed via compromising a 2.5% relative accuracy drop. The proposed nvCIM PE achieves 16.9 TOPS/W power efficiency and a maximum spike frequency of 99.24 MHz.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"35 1","pages":"T86-T87"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87153160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776576
T. Yamamoto
Superconducting parametric amplifier, originally developed more than half a century ago, gained renewed interests in some experiments of superconducting quantum electronics about a decade ago, and now has become an indispensable tool in the field of superconducting quantum information processing. More recently, there are several proposals, where a parametric oscillator, which is a parametric amplifier pumped above the threshold, is used as a quantum bit and the network of the parametric oscillators solve some computational tasks. Here, we briefly introduce the research activity on the development of the superconducting parametric devices, including our results, with some historical backgrounds.
{"title":"Superconducting parametric devices","authors":"T. Yamamoto","doi":"10.23919/VLSIT.2019.8776576","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776576","url":null,"abstract":"Superconducting parametric amplifier, originally developed more than half a century ago, gained renewed interests in some experiments of superconducting quantum electronics about a decade ago, and now has become an indispensable tool in the field of superconducting quantum information processing. More recently, there are several proposals, where a parametric oscillator, which is a parametric amplifier pumped above the threshold, is used as a quantum bit and the network of the parametric oscillators solve some computational tasks. Here, we briefly introduce the research activity on the development of the superconducting parametric devices, including our results, with some historical backgrounds.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"187 1","pages":"T28-T29"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81188620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776499
K. Nishioka, H. Honjo, S. Ikeda, T. Watanabe, S. Miura, H. Inoue, T. Tanigawa, Y. Noguchi, M. Yasuhira, H. Sato, T. Endoh
We have proposed novel quad-interface magnetic tunnel junction (MTJ) technology which brings forth an increase of both thermal stability factor $Delta$ and switching efficiency $Delta/I_{text{C}0}$ by a factor of 1.5-2 compared with conventional double-interface MTJ technology. We successfully fabricated the quad-interface MTJ using 300mm process based on novel low damage integration process including PVD, RIE and so on [1]. By developing the quad-interface MTJ, we have achieved about two times larger $Delta$ and $Delta/I_{text{C}0}$. Moreover, we have achieved about two times larger TMR ratio/RA by the stack development specific for the quad-interface MTJ technology. The developed quad-interface MTJ technology regarded as post-double-interface MTJ technology will become an essential technology for the scaling of the STT-MRAM beyond 20nm.
{"title":"Novel Quad interface MTJ technology and its first demonstration with high thermal stability and switching efficiency for STT-MRAM beyond 2Xnm","authors":"K. Nishioka, H. Honjo, S. Ikeda, T. Watanabe, S. Miura, H. Inoue, T. Tanigawa, Y. Noguchi, M. Yasuhira, H. Sato, T. Endoh","doi":"10.23919/VLSIT.2019.8776499","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776499","url":null,"abstract":"We have proposed novel quad-interface magnetic tunnel junction (MTJ) technology which brings forth an increase of both thermal stability factor $Delta$ and switching efficiency $Delta/I_{text{C}0}$ by a factor of 1.5-2 compared with conventional double-interface MTJ technology. We successfully fabricated the quad-interface MTJ using 300mm process based on novel low damage integration process including PVD, RIE and so on [1]. By developing the quad-interface MTJ, we have achieved about two times larger $Delta$ and $Delta/I_{text{C}0}$. Moreover, we have achieved about two times larger TMR ratio/RA by the stack development specific for the quad-interface MTJ technology. The developed quad-interface MTJ technology regarded as post-double-interface MTJ technology will become an essential technology for the scaling of the STT-MRAM beyond 20nm.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"12 1","pages":"T120-T121"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90062342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776553
Fei Mo, Yusaku Tagawa, C. Jin, Min-Ju Ahn, T. Saraya, T. Hiramoto, M. Kobayashi
We have experimentally demonstrated a ferroelectric HfO2 FET with memory operation by introducing ultrathin IGZO as a channel material. Ultrathin-body IGZO ferroelectric FET (FeFET) shows high mobility with deposited channel material, nearly ideal subthreshold slope, and controllable memory characteristics with the use of back-end compatible process. These results are attributed to the properties of IGZO channel: junctionless FET operation, nearly-zero low-k interfacial layer on metal-oxide channel and good capping effect for realizing ferroelectric phase formation with HfZrO2. IGZO FeFET will open a new path for high-density memory application. Keywords: ferroelectric FET, HfO2, IGZO, memory.
{"title":"Experimental Demonstration of Ferroelectric HfO2 FET with Ultrathin-body IGZO for High-Density and Low-Power Memory Application","authors":"Fei Mo, Yusaku Tagawa, C. Jin, Min-Ju Ahn, T. Saraya, T. Hiramoto, M. Kobayashi","doi":"10.23919/VLSIT.2019.8776553","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776553","url":null,"abstract":"We have experimentally demonstrated a ferroelectric HfO2 FET with memory operation by introducing ultrathin IGZO as a channel material. Ultrathin-body IGZO ferroelectric FET (FeFET) shows high mobility with deposited channel material, nearly ideal subthreshold slope, and controllable memory characteristics with the use of back-end compatible process. These results are attributed to the properties of IGZO channel: junctionless FET operation, nearly-zero low-k interfacial layer on metal-oxide channel and good capping effect for realizing ferroelectric phase formation with HfZrO2. IGZO FeFET will open a new path for high-density memory application. Keywords: ferroelectric FET, HfO2, IGZO, memory.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"104 1","pages":"T42-T43"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89219984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776532
M. Kim, N. Harada, Y. Kikuchi, J. Boemmels, J. Mitard, T. Huynh-Bao, P. Matagne, Z. Tao, W. Li, K. Devriendt, L. Ragnarsson, C. Lorant, F. Sebaai, C. Porret, E. Rosseel, A. Dangol, D. Batuk, G. Martinez-Alanis, J. Geypen, N. Jourdan, A. Sepúlveda, H. Puliyalil, G. Jamieson, M. H. van der Veen, L. Teugels, Z. El-Mekki, E. Altamirano-Sanchez, Y. Li, H. Nakamura, D. Mocuta, F. Masuoka
For the first time, we establish a fabrication process flow of an EUV-era ultra-density 6-surrounding-gate-transistor SRAM with $0.0205 mu text{m}^{2}$ unit cell area and demonstrate nMOS surrounding-gate-transistor function. In this paper, 6-surrounding-gate-transistor SRAM design layout is shown, and the fabrication process flow and key process steps are explained in detail. NMOS functional device characteristics of surrounding-gate-transistor is analyzed.
我们首次建立了euv时代的超密度6-包围栅极SRAM的制造工艺流程，单元面积为0.0205 mu text{m}^{2}$，并演示了nMOS包围栅极晶体管的功能。本文给出了六围栅晶体管SRAM的设计版图，并对其制作工艺流程和关键工艺步骤进行了详细说明。分析了围栅晶体管的NMOS功能器件特性。
{"title":"12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices","authors":"M. Kim, N. Harada, Y. Kikuchi, J. Boemmels, J. Mitard, T. Huynh-Bao, P. Matagne, Z. Tao, W. Li, K. Devriendt, L. Ragnarsson, C. Lorant, F. Sebaai, C. Porret, E. Rosseel, A. Dangol, D. Batuk, G. Martinez-Alanis, J. Geypen, N. Jourdan, A. Sepúlveda, H. Puliyalil, G. Jamieson, M. H. van der Veen, L. Teugels, Z. El-Mekki, E. Altamirano-Sanchez, Y. Li, H. Nakamura, D. Mocuta, F. Masuoka","doi":"10.23919/VLSIT.2019.8776532","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776532","url":null,"abstract":"For the first time, we establish a fabrication process flow of an EUV-era ultra-density 6-surrounding-gate-transistor SRAM with $0.0205 mu text{m}^{2}$ unit cell area and demonstrate nMOS surrounding-gate-transistor function. In this paper, 6-surrounding-gate-transistor SRAM design layout is shown, and the fabrication process flow and key process steps are explained in detail. NMOS functional device characteristics of surrounding-gate-transistor is analyzed.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"75 1","pages":"T198-T199"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85829318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-06-09DOI: 10.23919/VLSIT.2019.8776544
S. Okumura, M. Yabuuchi, K. Hijioka, Koichi Nose
A Processing-In-Memory (PIM) accelerator with ternary SRAM is proposed for low-power, large-scale deep neural network (DNN) processing. The accelerator consists of Ternary Neural Arithmetic Memory (TNAM) which is capable of bit-scalable MAC (multiply and accumulation) operation in accordance with target accuracy and power limit. An ADC less readout circuits to reduce analog-digital conversion power and a system-level variation avoidance technique utilizing features of TNAM are also proposed. A test chip with large-scale PIM is fabricated and successfully operate convolutional neural networks (CNNs) with 8.8TOPS/W and highest accuracy and area density among recent SRAM-type PIMs are obtained.
{"title":"A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2","authors":"S. Okumura, M. Yabuuchi, K. Hijioka, Koichi Nose","doi":"10.23919/VLSIT.2019.8776544","DOIUrl":"https://doi.org/10.23919/VLSIT.2019.8776544","url":null,"abstract":"A Processing-In-Memory (PIM) accelerator with ternary SRAM is proposed for low-power, large-scale deep neural network (DNN) processing. The accelerator consists of Ternary Neural Arithmetic Memory (TNAM) which is capable of bit-scalable MAC (multiply and accumulation) operation in accordance with target accuracy and power limit. An ADC less readout circuits to reduce analog-digital conversion power and a system-level variation avoidance technique utilizing features of TNAM are also proposed. A test chip with large-scale PIM is fabricated and successfully operate convolutional neural networks (CNNs) with 8.8TOPS/W and highest accuracy and area density among recent SRAM-type PIMs are obtained.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"336 1","pages":"C248-C249"},"PeriodicalIF":0.0,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86790236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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