Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870554
K. Fukuda, J. Hattori, H. Asai, M. Shimizu, T. Hashizume
A modeling method of deep level transient spectroscopy (DLTS) using circuit simulation with a MOS capacitor compact model which takes into account influences of deep level traps is proposed. In the proposed method, DLTS measurement procedures are described by transient analysis of circuit simulation. Stable numerical convergence is obtained even for the case in which carrier traps with wide range of time scales are included. Through case studies, it is proved that this method is a robust and versatile theoretical tool to predict DLTS signals, which helps to understand DLTS results and to optimize DLTS measurement conditions. Furthermore, the method is applied to several capacitance measurement methods discussed in literatures concerning GaN MIS capacitors, which ensures the practical ability of the proposed simulation approach.
{"title":"Simulation of deep level transient spectroscopy using circuit simulator with deep level trap model implemented by Verilog-A language","authors":"K. Fukuda, J. Hattori, H. Asai, M. Shimizu, T. Hashizume","doi":"10.1109/SISPAD.2019.8870554","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870554","url":null,"abstract":"A modeling method of deep level transient spectroscopy (DLTS) using circuit simulation with a MOS capacitor compact model which takes into account influences of deep level traps is proposed. In the proposed method, DLTS measurement procedures are described by transient analysis of circuit simulation. Stable numerical convergence is obtained even for the case in which carrier traps with wide range of time scales are included. Through case studies, it is proved that this method is a robust and versatile theoretical tool to predict DLTS signals, which helps to understand DLTS results and to optimize DLTS measurement conditions. Furthermore, the method is applied to several capacitance measurement methods discussed in literatures concerning GaN MIS capacitors, which ensures the practical ability of the proposed simulation approach.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1943 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91190309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870365
Hong-hyun Park, W. Choi, M. A. Pourghaderi, Jongchol Kim, U. Kwon, D. Kim
We present quantum transport simulation results of stacked silicon nanosheet (SiNS) nFETs. Our simulations are based on the non-equilibrium Green’s function (NEGF) method which is capable of dealing with all major physical effects necessary for steady-state electron transport in the complex-shaped devices. In order to help find optimal device design many split simulations for various geometry and process conditions were performed as a demonstration.
{"title":"NEGF simulations of stacked silicon nanosheet FETs for performance optimization","authors":"Hong-hyun Park, W. Choi, M. A. Pourghaderi, Jongchol Kim, U. Kwon, D. Kim","doi":"10.1109/SISPAD.2019.8870365","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870365","url":null,"abstract":"We present quantum transport simulation results of stacked silicon nanosheet (SiNS) nFETs. Our simulations are based on the non-equilibrium Green’s function (NEGF) method which is capable of dealing with all major physical effects necessary for steady-state electron transport in the complex-shaped devices. In order to help find optimal device design many split simulations for various geometry and process conditions were performed as a demonstration.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"10 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78196728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870377
T. Ikegami, K. Fukuda, J. Hattori
A Python-based device simulator named Impulse TCAD was developed. The simulator is built on top of a nonlinear finite volume method (FVM) solver. To describe physical behavior of non-standard materials, both device properties and their dominant equations can be customized. The given FVM equations are solved by the Newton method, where required derivatives of the equations are derived automatically by using an automatic differentiation technique. As a demonstration, a steady state analysis of the negative capacitance field effect transistors with ferroelectric materials is selected, where the coupled Poisson and Devonshire equations are implemented in several different ways.
{"title":"Implementation of Automatic Differentiation to Python-based Semiconductor Device Simulator","authors":"T. Ikegami, K. Fukuda, J. Hattori","doi":"10.1109/SISPAD.2019.8870377","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870377","url":null,"abstract":"A Python-based device simulator named Impulse TCAD was developed. The simulator is built on top of a nonlinear finite volume method (FVM) solver. To describe physical behavior of non-standard materials, both device properties and their dominant equations can be customized. The given FVM equations are solved by the Newton method, where required derivatives of the equations are derived automatically by using an automatic differentiation technique. As a demonstration, a steady state analysis of the negative capacitance field effect transistors with ferroelectric materials is selected, where the coupled Poisson and Devonshire equations are implemented in several different ways.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77944680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870373
T. Rollo, L. Daniel, D. Esseni
In recent years electron devices based on ferroelectric materials have attracted a lot of interest well beyond FeRAM memories. Negative capacitance transistors (NC-FETs) have been investigated as steep slope transistors [1], [2], and Ferroelectric FETs (Fe-FETs) are under intense scrutiny also as synaptic devices for neuromorphc computing, where the minor loops in ferroelectrics can allow to achieve multiple values of conductance in read mode [3], [4], [5]. Furthermore, the persistence of ferroelectricity in ultra-thin ferroelectric layers paved the way to ferroelectric tunnelling junctions [6], where a polarization dependent tunneling current can be exploited to realize high impedance memristors, amenable for ultra power-efficient and thus massive parallel computation.
{"title":"Accurate and Efficient Dynamic Simulations of Ferroelectric Based Electron Devices","authors":"T. Rollo, L. Daniel, D. Esseni","doi":"10.1109/SISPAD.2019.8870373","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870373","url":null,"abstract":"In recent years electron devices based on ferroelectric materials have attracted a lot of interest well beyond FeRAM memories. Negative capacitance transistors (NC-FETs) have been investigated as steep slope transistors [1], [2], and Ferroelectric FETs (Fe-FETs) are under intense scrutiny also as synaptic devices for neuromorphc computing, where the minor loops in ferroelectrics can allow to achieve multiple values of conductance in read mode [3], [4], [5]. Furthermore, the persistence of ferroelectricity in ultra-thin ferroelectric layers paved the way to ferroelectric tunnelling junctions [6], where a polarization dependent tunneling current can be exploited to realize high impedance memristors, amenable for ultra power-efficient and thus massive parallel computation.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"12 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74705802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870415
Jin Cho, D. Kimpton, E. Guichard
There are several device challenges unique to the select gate transistor in 3D NAND memory cell. It requires low leakage current to prevent read and program disturb problem and it needs to provide enough current during read and erase operation. In this paper, we examined the design optimization of select gate transistor with respect to various device elements including work-function, S/D overlap, and trap density. Finally, we reviewed the path to reduce the channel length of the select gate transistor in conjunction with the role of dummy cells.
{"title":"Optimization of select gate transistor in advanced 3D NAND memory cell","authors":"Jin Cho, D. Kimpton, E. Guichard","doi":"10.1109/SISPAD.2019.8870415","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870415","url":null,"abstract":"There are several device challenges unique to the select gate transistor in 3D NAND memory cell. It requires low leakage current to prevent read and program disturb problem and it needs to provide enough current during read and erase operation. In this paper, we examined the design optimization of select gate transistor with respect to various device elements including work-function, S/D overlap, and trap density. Finally, we reviewed the path to reduce the channel length of the select gate transistor in conjunction with the role of dummy cells.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"58 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74641704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870476
Manzanarez Hervé, Moreau Stéphane, Cueto Olga
Copper ions drift is modeled in the case of hybrid bonding integration. The continuity equation is coupled to the Poisson’s equation and a copper ion concentration saturation is assumed. A 1D geometry simulation is initially realized to validate the model and 2D geometry simulations of hybrid bonding are analyzed by looking the time to percolate (TTP).
{"title":"Metallic ions drift in hybrid bonding integration modeling, towards the evolution of failure criterion","authors":"Manzanarez Hervé, Moreau Stéphane, Cueto Olga","doi":"10.1109/SISPAD.2019.8870476","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870476","url":null,"abstract":"Copper ions drift is modeled in the case of hybrid bonding integration. The continuity equation is coupled to the Poisson’s equation and a copper ion concentration saturation is assumed. A 1D geometry simulation is initially realized to validate the model and 2D geometry simulations of hybrid bonding are analyzed by looking the time to percolate (TTP).","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"96 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73683552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/sispad.2019.8870522
{"title":"SISPAD 2019 Copyright Page","authors":"","doi":"10.1109/sispad.2019.8870522","DOIUrl":"https://doi.org/10.1109/sispad.2019.8870522","url":null,"abstract":"","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"39 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84206540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870363
Teren Liu, Tao Fang, K. Kavanagh, Hongyu Yu, G. Xia
This paper reports the successful atomic layer patterning of 2-dimensional Black Phosphorus (BP) and the simulation of the etching process by Density Functional Theory (DFT) method. The wet etching process can etch selected regions of few-layer black phosphorous with an atomic layer accuracy, which provides a feasible patterning approach for large-scale manufacturing of few-layer BP materials and devices. Absorption energies of iodine atoms/molecules at different location of BP layer edge were also calculated by DFT method, shown a vertical etching direction preference which was important for achieving high quality patterns.
{"title":"A new wet etching method for black phosphorus layer number engineering: experiment, modeling and DFT simulations","authors":"Teren Liu, Tao Fang, K. Kavanagh, Hongyu Yu, G. Xia","doi":"10.1109/SISPAD.2019.8870363","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870363","url":null,"abstract":"This paper reports the successful atomic layer patterning of 2-dimensional Black Phosphorus (BP) and the simulation of the etching process by Density Functional Theory (DFT) method. The wet etching process can etch selected regions of few-layer black phosphorous with an atomic layer accuracy, which provides a feasible patterning approach for large-scale manufacturing of few-layer BP materials and devices. Absorption energies of iodine atoms/molecules at different location of BP layer edge were also calculated by DFT method, shown a vertical etching direction preference which was important for achieving high quality patterns.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"43 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84876944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870494
D. Verreck, A. Arreghini, F. Schanovsky, Z. Stanojevic, K. Steiner, F. Mitterbauer, M. Karner, G. Van den bosch, A. Furnémont
The polycrystalline nature of state-of-the-art 3D NAND flash channels complicates on-current and variability modeling. We have therefore developed a 3D TCAD model that captures percolating current behavior and the resulting variability, and implemented it into the Global TCAD Solutions software package. In our simulation flow, we model the channel transport through the randomly generated grain structure with thermionic emission modulated by discrete traps at the grain boundaries, combined with a crystal orientation dependent mobility model inside the grains. We show that this approach can reproduce experimentally observed on-current temperature dependence and variability and use it to investigate the influence of defect density levels and average grain size.
{"title":"3D TCAD Model for Poly-Si Channel Current and Variability in Vertical NAND Flash Memory","authors":"D. Verreck, A. Arreghini, F. Schanovsky, Z. Stanojevic, K. Steiner, F. Mitterbauer, M. Karner, G. Van den bosch, A. Furnémont","doi":"10.1109/SISPAD.2019.8870494","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870494","url":null,"abstract":"The polycrystalline nature of state-of-the-art 3D NAND flash channels complicates on-current and variability modeling. We have therefore developed a 3D TCAD model that captures percolating current behavior and the resulting variability, and implemented it into the Global TCAD Solutions software package. In our simulation flow, we model the channel transport through the randomly generated grain structure with thermionic emission modulated by discrete traps at the grain boundaries, combined with a crystal orientation dependent mobility model inside the grains. We show that this approach can reproduce experimentally observed on-current temperature dependence and variability and use it to investigate the influence of defect density levels and average grain size.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"35 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80792925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870435
T. Herrmann, A. Zaka, N. Subramani, Zhixing Zhao, S. Lehmann, Y. Andee
The paper describes manufacturing process and layout optimizations to improve RF performance of 22FDX® N/PFET devices, based on a comprehensive calibration of DC and RF figures of merit. Process and Device simulations of the individual and combined elements show ft/fmax improvement up to about 1.13/1.1x (NFET) and about 1.32/1.24x (PFET) over standard devices mainly driven by mechanical stress and parasitic R/C elements.
{"title":"RF performance improvement on 22FDX® platform and beyond","authors":"T. Herrmann, A. Zaka, N. Subramani, Zhixing Zhao, S. Lehmann, Y. Andee","doi":"10.1109/SISPAD.2019.8870435","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870435","url":null,"abstract":"The paper describes manufacturing process and layout optimizations to improve RF performance of 22FDX® N/PFET devices, based on a comprehensive calibration of DC and RF figures of merit. Process and Device simulations of the individual and combined elements show ft/fmax improvement up to about 1.13/1.1x (NFET) and about 1.32/1.24x (PFET) over standard devices mainly driven by mechanical stress and parasitic R/C elements.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"9 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82524067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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