Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870384
J. Locati, C. Rivero, J. Delalleau, V. Della Marca, K. Coulié, J. Innocenti, O. Paulet, A. Régnier, S. Niel
In this paper, a new device architecture has been studied by TCAD process simulations in order to provide the improvements on the electrical characteristics. We focus mainly on the drain-bulk junction breakdown voltage, of a double 130 nm poly gate transistor for Non-Volatile Memory technology. It is used as a word line select transistor, handling the drain voltage up to 13 V. The proposed structure has been implemented on silicon and the electrical measurements demonstrate the good predictability given by simulations. Finally, a new zero-cost added process asymmetric architecture is also studied to propose further improvements in terms of footprint or electrical characteristics.
{"title":"TCAD investigation of zero-cost high voltage transistor architectures for logic memory circuits","authors":"J. Locati, C. Rivero, J. Delalleau, V. Della Marca, K. Coulié, J. Innocenti, O. Paulet, A. Régnier, S. Niel","doi":"10.1109/SISPAD.2019.8870384","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870384","url":null,"abstract":"In this paper, a new device architecture has been studied by TCAD process simulations in order to provide the improvements on the electrical characteristics. We focus mainly on the drain-bulk junction breakdown voltage, of a double 130 nm poly gate transistor for Non-Volatile Memory technology. It is used as a word line select transistor, handling the drain voltage up to 13 V. The proposed structure has been implemented on silicon and the electrical measurements demonstrate the good predictability given by simulations. Finally, a new zero-cost added process asymmetric architecture is also studied to propose further improvements in terms of footprint or electrical characteristics.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"20 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74443152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870436
A. Afzalian, G. Pourtois
A state-of-the-art DFT-NEGF based ATOmistic - MOdelling Solver (ATOMOS) was developed and used to assess the physics and fundamental-performance potential of various scaled mono-layer transition-metal-dichalcogenides and blackphosphorus (BP) MOSFETs down to a gate length of 5 nm, including the effect of electron-phonon scattering. Our study highlights the good scalability and drive-current potential of HfS2 and the impact of optical-phonon scattering for BP.
{"title":"ATOMOS: An ATomistic MOdelling Solver for dissipative DFT transport in ultra-scaled HfS2 and Black phosphorus MOSFETs","authors":"A. Afzalian, G. Pourtois","doi":"10.1109/SISPAD.2019.8870436","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870436","url":null,"abstract":"A state-of-the-art DFT-NEGF based ATOmistic - MOdelling Solver (ATOMOS) was developed and used to assess the physics and fundamental-performance potential of various scaled mono-layer transition-metal-dichalcogenides and blackphosphorus (BP) MOSFETs down to a gate length of 5 nm, including the effect of electron-phonon scattering. Our study highlights the good scalability and drive-current potential of HfS2 and the impact of optical-phonon scattering for BP.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"50 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73470044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870558
F. Pace, O. Marcelot, P. Martin-Gonthier, O. Saint-Pé, M. Bréart de Boisanger, Rose-Marie Sauvage, P. Magnan
Parasitic Light Sensitivity (PLS) is a key performance parameter for Global Shutter CMOS Image Sensors (GSCIS), which quantifies the sensor sensitivity to light when the shutter is supposed closed. Its modeling and understanding would allow for an optimization in developing future sensors. This paper aims to present an efficient method for 2D modeling PLS in GSCIS through separation of the optical problem from the carriers motion one. The optical problem is solved thanks to Finite-Differences Time-Domain (FDTD) simulations, while solution to the carriers motion problem is given through the application of the Boltzmann Transport Equation (BTE). This method is presented as a faster alternative to the coupled use of FDTD and TCAD simulations: since it is supposed that the two problem solutions are independent, the two simulations can be performed in parallel. The results show good match between the developed method and the TCAD solutions, thus showing fair agreement with experimental data, probably due to a poor knowledge of the back-end process.
{"title":"An Efficient Method for Modeling Parasitic Light Sensitivity in Global Shutter CMOS Image Sensors","authors":"F. Pace, O. Marcelot, P. Martin-Gonthier, O. Saint-Pé, M. Bréart de Boisanger, Rose-Marie Sauvage, P. Magnan","doi":"10.1109/SISPAD.2019.8870558","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870558","url":null,"abstract":"Parasitic Light Sensitivity (PLS) is a key performance parameter for Global Shutter CMOS Image Sensors (GSCIS), which quantifies the sensor sensitivity to light when the shutter is supposed closed. Its modeling and understanding would allow for an optimization in developing future sensors. This paper aims to present an efficient method for 2D modeling PLS in GSCIS through separation of the optical problem from the carriers motion one. The optical problem is solved thanks to Finite-Differences Time-Domain (FDTD) simulations, while solution to the carriers motion problem is given through the application of the Boltzmann Transport Equation (BTE). This method is presented as a faster alternative to the coupled use of FDTD and TCAD simulations: since it is supposed that the two problem solutions are independent, the two simulations can be performed in parallel. The results show good match between the developed method and the TCAD solutions, thus showing fair agreement with experimental data, probably due to a poor knowledge of the back-end process.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"12 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72882164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870506
D. Verreck, G. Arutchelvan, M. Heyns, I. Radu
A tied double gate structure has been shown to deliver optimal device-level performance in few-layer MoS2 field-effect transistors. However, the enlarged gate capacitance from the added gate increases circuit-level power consumption and negatively affects minimum obtainable delay. Here, we therefore use a calibrated design-technology co-optimization approach that includes the interconnect load to evaluate back gate size reduction strategies in terms of power and delay. We consider the impact of a spacer region and varying interconnect length. We find that power consumption can be decreased by almost 20% by reducing the back gate overlap with the source-drain contacts without negatively affecting delay, as the carrier injection is occurring dominantly at the contact edges. We also show that opening the back gate underneath the channel provides additional benefit for locally interconnected devices.
{"title":"Device and Circuit Level Gate Configuration Optimization for 2D Material Field-Effect Transistors","authors":"D. Verreck, G. Arutchelvan, M. Heyns, I. Radu","doi":"10.1109/SISPAD.2019.8870506","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870506","url":null,"abstract":"A tied double gate structure has been shown to deliver optimal device-level performance in few-layer MoS2 field-effect transistors. However, the enlarged gate capacitance from the added gate increases circuit-level power consumption and negatively affects minimum obtainable delay. Here, we therefore use a calibrated design-technology co-optimization approach that includes the interconnect load to evaluate back gate size reduction strategies in terms of power and delay. We consider the impact of a spacer region and varying interconnect length. We find that power consumption can be decreased by almost 20% by reducing the back gate overlap with the source-drain contacts without negatively affecting delay, as the carrier injection is occurring dominantly at the contact edges. We also show that opening the back gate underneath the channel provides additional benefit for locally interconnected devices.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"28 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81249777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870426
W. Sung, Min-Hui Chuang, Yiming Li
We advance the localized work-function fluctuation (LWKF) method to examine the variability of threshold voltage $(mathrm{V}_{mathrm{t}mathrm{h}})$ induced by titanium nitride (TiN) metal-gate work-function fluctuation (WKF) and combined the WKF with the random dopant fluctuation (RDF) for various grain sizes on Si gate-all-around (GAA) nanowire (NW) MOSFETs. Our results show that the WKF-induced variability of $mathrm{V}_{mathrm{t}mathrm{h}}$ will be dominated by bamboo-type TiN grains and its impact is larger than that induced by the RDF with doped channel (RDF (doped)). Additionally, the variability of $mathrm{V}_{mathrm{t}mathrm{h}}$ induced by the WKF and the RDF (doped) could be treated as independent fluctuation sources because the channel dopants are away from the metal-gate/high-$kappa$ interface. Consequently, statistical models are further proposed for the $sigmamathrm{V}_{mathrm{t}mathrm{h}}$ induced by the WKF and the combined WKF with RDF (doped) by considering position effect of nanosized TiN grains.
{"title":"Variability of Threshold Voltage Induced by Work-Function Fluctuation and Random Dopant Fluctuation on Gate-All-Around Nanowire nMOSFETs","authors":"W. Sung, Min-Hui Chuang, Yiming Li","doi":"10.1109/SISPAD.2019.8870426","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870426","url":null,"abstract":"We advance the localized work-function fluctuation (LWKF) method to examine the variability of threshold voltage $(mathrm{V}_{mathrm{t}mathrm{h}})$ induced by titanium nitride (TiN) metal-gate work-function fluctuation (WKF) and combined the WKF with the random dopant fluctuation (RDF) for various grain sizes on Si gate-all-around (GAA) nanowire (NW) MOSFETs. Our results show that the WKF-induced variability of $mathrm{V}_{mathrm{t}mathrm{h}}$ will be dominated by bamboo-type TiN grains and its impact is larger than that induced by the RDF with doped channel (RDF (doped)). Additionally, the variability of $mathrm{V}_{mathrm{t}mathrm{h}}$ induced by the WKF and the RDF (doped) could be treated as independent fluctuation sources because the channel dopants are away from the metal-gate/high-$kappa$ interface. Consequently, statistical models are further proposed for the $sigmamathrm{V}_{mathrm{t}mathrm{h}}$ induced by the WKF and the combined WKF with RDF (doped) by considering position effect of nanosized TiN grains.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89460313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870361
Aaron Kramer, M. L. Van de Put, C. Hinkle, W. Vandenberghe
Trigonal-Tellurium (t-Te), a van der Waals material, recently garnered interest to the nanoelectronics community because a high hole mobility, a high bandgap, and low temperature growth have all been observed in nanostructures. We analyze various t-Te nanostructures (nanowires and layers) using first principles simulations. We compare bandgap variation and relative stability among different shapes and sizes of Te nanostructures. We determine that nanowires host higher bandgaps and are preferentially grown, rather than layers of t-Te. We also propose a simplified model using the number of van der Waals interactions in explaining relative stability among t-Te nanostructures. Finally, we study uniquely shaped (auxiliary) t-Te nanostructures and verify that their stability obeys the same simplified model.
{"title":"Trigonal Tellurium Nanostructure Formation Energy and Band gap","authors":"Aaron Kramer, M. L. Van de Put, C. Hinkle, W. Vandenberghe","doi":"10.1109/SISPAD.2019.8870361","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870361","url":null,"abstract":"Trigonal-Tellurium (t-Te), a van der Waals material, recently garnered interest to the nanoelectronics community because a high hole mobility, a high bandgap, and low temperature growth have all been observed in nanostructures. We analyze various t-Te nanostructures (nanowires and layers) using first principles simulations. We compare bandgap variation and relative stability among different shapes and sizes of Te nanostructures. We determine that nanowires host higher bandgaps and are preferentially grown, rather than layers of t-Te. We also propose a simplified model using the number of van der Waals interactions in explaining relative stability among t-Te nanostructures. Finally, we study uniquely shaped (auxiliary) t-Te nanostructures and verify that their stability obeys the same simplified model.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"11 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89766999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870526
O. Badami, S. Berrada, H. Carrillo-Nuñez, C. Medina-Bailón, V. Georgiev, A. Asenov
The microelectronic industry has moved from matured bulk planar transistor to three-dimensional (3D) architectures with small non-trivial cross-sections and short channel lengths requiring quantum simulation techniques. In addition, novel materials, which enhance the transistor performance, are considered as silicon channel replacement. This necessitates the efficient inclusion of surface roughness scattering in quantum transport simulations. In this work, we report an approximate methodology to include surface roughness scattering in 3D Non-Equilibrium Green’s Function (NEGF) simulations using self-energy formulation within the self-consistent Born approximation (SCBA). The method is validated with the well established methodology of treating surface roughness as a variability source. We also extract the mobility from our simulations and then compare with to those reported in the literature.
{"title":"Surface Roughness Scattering in NEGF using self-energy formulation","authors":"O. Badami, S. Berrada, H. Carrillo-Nuñez, C. Medina-Bailón, V. Georgiev, A. Asenov","doi":"10.1109/SISPAD.2019.8870526","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870526","url":null,"abstract":"The microelectronic industry has moved from matured bulk planar transistor to three-dimensional (3D) architectures with small non-trivial cross-sections and short channel lengths requiring quantum simulation techniques. In addition, novel materials, which enhance the transistor performance, are considered as silicon channel replacement. This necessitates the efficient inclusion of surface roughness scattering in quantum transport simulations. In this work, we report an approximate methodology to include surface roughness scattering in 3D Non-Equilibrium Green’s Function (NEGF) simulations using self-energy formulation within the self-consistent Born approximation (SCBA). The method is validated with the well established methodology of treating surface roughness as a variability source. We also extract the mobility from our simulations and then compare with to those reported in the literature.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"12 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84895461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870391
T. Sadi, O. Badami, V. Georgiev, J. Ding, A. Asenov
Nowadays, resistive random-access memories (RRAMs) are widely considered as the next generation of non-volatile memory devices. Here, we employ a physics-based multi-scale kinetic Monte Carlo simulator to study the microscopic transport properties and characteristics of promising RRAM devices based on transition metal oxides, specifically hafnium oxide (HfOx) based structures. The simulator handles self-consistently electronic charge and thermal transport in the three-dimensional (3D) space, allowing the realistic study of the dynamics of conductive filaments responsible for switching. By presenting insightful results, we argue that using a simulator of a 3D nature, accounting for self-consistent fields and self-heating, is necessary for understanding switching in RRAMs. As an example, we look into the unipolar operation mode, by showing how only the correct inclusion of self-heating allows the proper reconstruction of the switching behaviour. The simulation framework is well-suited for exploring the operation and reliability of RRAMs, providing a reliable computational tool for the optimization of existing device technologies and the path finding and development of new RRAM options.
{"title":"Physical Insights into the Transport Properties of RRAMs Based on Transition Metal Oxides","authors":"T. Sadi, O. Badami, V. Georgiev, J. Ding, A. Asenov","doi":"10.1109/SISPAD.2019.8870391","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870391","url":null,"abstract":"Nowadays, resistive random-access memories (RRAMs) are widely considered as the next generation of non-volatile memory devices. Here, we employ a physics-based multi-scale kinetic Monte Carlo simulator to study the microscopic transport properties and characteristics of promising RRAM devices based on transition metal oxides, specifically hafnium oxide (HfOx) based structures. The simulator handles self-consistently electronic charge and thermal transport in the three-dimensional (3D) space, allowing the realistic study of the dynamics of conductive filaments responsible for switching. By presenting insightful results, we argue that using a simulator of a 3D nature, accounting for self-consistent fields and self-heating, is necessary for understanding switching in RRAMs. As an example, we look into the unipolar operation mode, by showing how only the correct inclusion of self-heating allows the proper reconstruction of the switching behaviour. The simulation framework is well-suited for exploring the operation and reliability of RRAMs, providing a reliable computational tool for the optimization of existing device technologies and the path finding and development of new RRAM options.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"4 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82013024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870500
U. Kwon, Jeong-Guk Min, Seon-Young Lee, Alexander Schmidt, D. Kim, Yasuyuki Kayama, Yutaka Nishizawa, Kiyoshi Ishikawa
TCAD prediction of the stress field generated by dislocation is crucial for the optimization of stressors for next generation logic devices. In this paper, we present a new hybrid approach for dislocation stress field calculation and its application to strained Si devices. New methodology combines an analytic stress field model for dislocation cores and consecutive FEM stress solving to get mechanical equilibrium. It was applied to the design optimization of dislocation stress memorization technique (D-SMT), its local layout effect (LLE) modeling, and the relaxation of lattice mismatch strain at Si/SiGe interface which degrades eSiGe stress. All the simulation results were verified with experimental results.
{"title":"Progress in dislocation stress field model and its appications","authors":"U. Kwon, Jeong-Guk Min, Seon-Young Lee, Alexander Schmidt, D. Kim, Yasuyuki Kayama, Yutaka Nishizawa, Kiyoshi Ishikawa","doi":"10.1109/SISPAD.2019.8870500","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870500","url":null,"abstract":"TCAD prediction of the stress field generated by dislocation is crucial for the optimization of stressors for next generation logic devices. In this paper, we present a new hybrid approach for dislocation stress field calculation and its application to strained Si devices. New methodology combines an analytic stress field model for dislocation cores and consecutive FEM stress solving to get mechanical equilibrium. It was applied to the design optimization of dislocation stress memorization technique (D-SMT), its local layout effect (LLE) modeling, and the relaxation of lattice mismatch strain at Si/SiGe interface which degrades eSiGe stress. All the simulation results were verified with experimental results.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"19 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83739522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870359
S. Fiorentini, R. Orio, W. Goes, J. Ender, V. Sverdlov
Simulations of free-layer switching in spin - transfer torque MRAM are usually performed with the torque computed approximately by assuming a position-independent electric current density through the structure. For high values of the tunneling magnetoresistance, this description is not accurate anymore, and one needs to solve the spin and charge drift-diffusion equations in the whole structure self-consistently. We compute the switching time distribution obtained by the self-consistent model and compare it to the switching times from the fixed current density approach. We show that, provided the current is appropriately adjusted, the simplified model can mimic the correct switching time distribution even in the case of high TMR.
{"title":"Comprehensive Comparison of Switching Models for Perpendicular Spin-Transfer Torque MRAM Cells","authors":"S. Fiorentini, R. Orio, W. Goes, J. Ender, V. Sverdlov","doi":"10.1109/SISPAD.2019.8870359","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870359","url":null,"abstract":"Simulations of free-layer switching in spin - transfer torque MRAM are usually performed with the torque computed approximately by assuming a position-independent electric current density through the structure. For high values of the tunneling magnetoresistance, this description is not accurate anymore, and one needs to solve the spin and charge drift-diffusion equations in the whole structure self-consistently. We compute the switching time distribution obtained by the self-consistent model and compare it to the switching times from the fixed current density approach. We show that, provided the current is appropriately adjusted, the simplified model can mimic the correct switching time distribution even in the case of high TMR.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76896284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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