Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870459
M. Kantner, T. Koprucki, H. Wünsche, U. Bandelow
The device-scale simulation of electrically driven quantum light sources based on semiconductor quantum dots requires a combination of the (semi-)classical semiconductor device equations with cavity quantum electrodynamics. We present a comprehensive quantum-classical simulation approach that self-consistently couples the (semi-)classical drift-diffusion system to a Lindblad-type quantum master equation. This allows to describe the spatially resolved carrier transport in complex, multi-dimensional device geometries along with the fully quantum-mechanical light-matter interaction in the quantum dot-cavity system. The latter gives access to important quantum optical figures of merit, in particular the second-order correlation function of the emitted radiation. In order to account for the quantum confined Stark effect in the device’s internal electric field, the system is solved along with a Schrödinger–Poisson problem, that describes the envelope wave functions and energy levels of the quantum dot carriers. The approach is demonstrated by numerical simulations of a single-photon emitting diode.
{"title":"Simulation of quantum dot based single-photon sources using the Schrödinger-Poisson-Drift-Diffusion-Lindblad system","authors":"M. Kantner, T. Koprucki, H. Wünsche, U. Bandelow","doi":"10.1109/SISPAD.2019.8870459","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870459","url":null,"abstract":"The device-scale simulation of electrically driven quantum light sources based on semiconductor quantum dots requires a combination of the (semi-)classical semiconductor device equations with cavity quantum electrodynamics. We present a comprehensive quantum-classical simulation approach that self-consistently couples the (semi-)classical drift-diffusion system to a Lindblad-type quantum master equation. This allows to describe the spatially resolved carrier transport in complex, multi-dimensional device geometries along with the fully quantum-mechanical light-matter interaction in the quantum dot-cavity system. The latter gives access to important quantum optical figures of merit, in particular the second-order correlation function of the emitted radiation. In order to account for the quantum confined Stark effect in the device’s internal electric field, the system is solved along with a Schrödinger–Poisson problem, that describes the envelope wave functions and energy levels of the quantum dot carriers. The approach is demonstrated by numerical simulations of a single-photon emitting diode.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"22 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89215886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870548
E. Caruso, F. Bettetti, L. D. Linz, D. Pin, M. Segatto, P. Palestri
We present an approach to model 1/f and random telegraph noise in TCAD combining the models for non-local tunneling to traps and generation/recombination noise. The TCAD results are compared with simple numerical expression to understand the influence of the device and trap parameters on the noise spectrum. The simulation deck is then used to compute the low-frequency noise spectrum in III-V MOSFETs using traps distributions extracted from multi-frequency C-V measurements.
{"title":"Modeling 1/f and Lorenzian noise in III-V MOSFETs","authors":"E. Caruso, F. Bettetti, L. D. Linz, D. Pin, M. Segatto, P. Palestri","doi":"10.1109/SISPAD.2019.8870548","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870548","url":null,"abstract":"We present an approach to model 1/f and random telegraph noise in TCAD combining the models for non-local tunneling to traps and generation/recombination noise. The TCAD results are compared with simple numerical expression to understand the influence of the device and trap parameters on the noise spectrum. The simulation deck is then used to compute the low-frequency noise spectrum in III-V MOSFETs using traps distributions extracted from multi-frequency C-V measurements.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"88 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72694359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870518
O. Badami, T. Sadi, V. Georgiev, F. Adamu-Lema, V. Thirunavukkarasu, J. Ding, A. Asenov
To keep up with the increase in demand for storing data, flash memories have been scaled down dramatically and stacked by the semiconductor industry. Furthermore, processing large data has highlighted the limitations of the von Neumann architecture. To overcome this, different types of memory devices like Resistive Random-Access Memories (RRAMs) have also gained a lot of importance. Hence, carrier dynamics in oxides has gained significant traction in recent years. In this work, we discuss the kinetic Monte Carlo methodology as implemented in our integrated simulation environment NESS (Nano-Electronic Simulation Software) that allows us to study carrier transport in the oxide using accurate physics based models. As an example, we study the retention characteristics in a molecule based flash memory.
{"title":"Multiscale Modeling of Charge Trapping in Molecule Based Flash Memories","authors":"O. Badami, T. Sadi, V. Georgiev, F. Adamu-Lema, V. Thirunavukkarasu, J. Ding, A. Asenov","doi":"10.1109/SISPAD.2019.8870518","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870518","url":null,"abstract":"To keep up with the increase in demand for storing data, flash memories have been scaled down dramatically and stacked by the semiconductor industry. Furthermore, processing large data has highlighted the limitations of the von Neumann architecture. To overcome this, different types of memory devices like Resistive Random-Access Memories (RRAMs) have also gained a lot of importance. Hence, carrier dynamics in oxides has gained significant traction in recent years. In this work, we discuss the kinetic Monte Carlo methodology as implemented in our integrated simulation environment NESS (Nano-Electronic Simulation Software) that allows us to study carrier transport in the oxide using accurate physics based models. As an example, we study the retention characteristics in a molecule based flash memory.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"89 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74724149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870354
L. Balestra, S. Reggiani, A. Gnudi, E. Gnani, G. Baccarani, J. Dobrzynska, J. Vobecký
Diamond-like carbon (DLC) is a very attractive material for Microelectronics, as it can be used to create robust passivation layers in semiconductor devices. In this work, the modelling of DLC in a TCAD framework is addressed, with special attention to the role played as the bevel coating of large-area high-voltage diodes. The TCAD simulations are nicely compared with experiments, giving rise to a detailed explanation of the role played by the DLC conductivity on the diode performance.
{"title":"Numerical Investigation of the Leakage Current and Blocking Capabilities of High-Power Diodes with Doped DLC Passivation Layers","authors":"L. Balestra, S. Reggiani, A. Gnudi, E. Gnani, G. Baccarani, J. Dobrzynska, J. Vobecký","doi":"10.1109/SISPAD.2019.8870354","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870354","url":null,"abstract":"Diamond-like carbon (DLC) is a very attractive material for Microelectronics, as it can be used to create robust passivation layers in semiconductor devices. In this work, the modelling of DLC in a TCAD framework is addressed, with special attention to the role played as the bevel coating of large-area high-voltage diodes. The TCAD simulations are nicely compared with experiments, giving rise to a detailed explanation of the role played by the DLC conductivity on the diode performance.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"22 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74288108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870384
J. Locati, C. Rivero, J. Delalleau, V. Della Marca, K. Coulié, J. Innocenti, O. Paulet, A. Régnier, S. Niel
In this paper, a new device architecture has been studied by TCAD process simulations in order to provide the improvements on the electrical characteristics. We focus mainly on the drain-bulk junction breakdown voltage, of a double 130 nm poly gate transistor for Non-Volatile Memory technology. It is used as a word line select transistor, handling the drain voltage up to 13 V. The proposed structure has been implemented on silicon and the electrical measurements demonstrate the good predictability given by simulations. Finally, a new zero-cost added process asymmetric architecture is also studied to propose further improvements in terms of footprint or electrical characteristics.
{"title":"TCAD investigation of zero-cost high voltage transistor architectures for logic memory circuits","authors":"J. Locati, C. Rivero, J. Delalleau, V. Della Marca, K. Coulié, J. Innocenti, O. Paulet, A. Régnier, S. Niel","doi":"10.1109/SISPAD.2019.8870384","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870384","url":null,"abstract":"In this paper, a new device architecture has been studied by TCAD process simulations in order to provide the improvements on the electrical characteristics. We focus mainly on the drain-bulk junction breakdown voltage, of a double 130 nm poly gate transistor for Non-Volatile Memory technology. It is used as a word line select transistor, handling the drain voltage up to 13 V. The proposed structure has been implemented on silicon and the electrical measurements demonstrate the good predictability given by simulations. Finally, a new zero-cost added process asymmetric architecture is also studied to propose further improvements in terms of footprint or electrical characteristics.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"20 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74443152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/sispad.2019.8870433
{"title":"SISPAD 2019 Author Index","authors":"","doi":"10.1109/sispad.2019.8870433","DOIUrl":"https://doi.org/10.1109/sispad.2019.8870433","url":null,"abstract":"","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"44 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79406803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/sispad.2019.8870457
Uma Sharma, S. Mahapatra
A SPICE compatible model is developed for the time kinetics of linear drain current drift (ΔIDLIN) under Hot Carrier Degradation (HCD) stress in 28 nm Fully Depleted Silicon On Insulator (FDSOI) n-channel FETs having High-K Metal Gate (HKMG) gate stack. The impact of varying the drain (VD), gate (VG) and body (VBB) biases is modeled. The framework is also capable of modeling the channel length (LCH) and gate-oxide thickness (TOX) variations. Impact of Self-Heating Effect (SHE) has also been taken into consideration during ΔIDLIN modeling.
{"title":"A SPICE Compatible Compact Model for Process and Bias Dependence of HCD in HKMG FDSOI MOSFETs","authors":"Uma Sharma, S. Mahapatra","doi":"10.1109/sispad.2019.8870457","DOIUrl":"https://doi.org/10.1109/sispad.2019.8870457","url":null,"abstract":"A SPICE compatible model is developed for the time kinetics of linear drain current drift (ΔI<inf>DLIN</inf>) under Hot Carrier Degradation (HCD) stress in 28 nm Fully Depleted Silicon On Insulator (FDSOI) n-channel FETs having High-K Metal Gate (HKMG) gate stack. The impact of varying the drain (V<inf>D</inf>), gate (V<inf>G</inf>) and body (V<inf>BB</inf>) biases is modeled. The framework is also capable of modeling the channel length (L<inf>CH</inf>) and gate-oxide thickness (T<inf>OX</inf>) variations. Impact of Self-Heating Effect (SHE) has also been taken into consideration during ΔI<inf>DLIN</inf> modeling.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82195444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870553
E. Caruso, J. Lin, S. Monaghan, K. Cherkaoui, L. Floyd, F. Gity, P. Palestri, D. Esseni, L. Selmi, P. Hurley
In this work, we describe how the frequency dependence of conductance (G) and capacitance (C) of a generic MOS capacitor results in peaks of the functions $mathrm {G}/omega$ and $-omega mathrm {dC}/mathrm {d}omega$. By means of TCAD simulations, we show that $mathrm {G}/omega$ and $-omega mathrm {dC}/mathrm {d}omega$ peak at the same value and at the same frequency for every bias point from accumulation to inversion. We illustrate how the properties of the peaks change with the semiconductor doping ($mathrm {N}_{mathrm {D}}$), oxide capacitance (Cox), minority carrier lifetime $(tau_{mathrm{g}})$, interface defect parameters ($mathrm {lt pgt N}_{mathrm {IT}}$, $sigma$) and majority carrier dielectric relaxation time $(tau_{mathrm {r}})$. Finally, we demonstrate how these insights on $mathrm {G}/omega$ and $-omega mathrm {dC}/mathrm {d}omega$ can be used to extract Cox, $mathrm {lt pgt N}_{mathrm {D}}$ and $tau_{mathrm {g}}$ from InGaAs MOSCAP measurements
{"title":"Relationship between capacitance and conductance in MOS capacitors","authors":"E. Caruso, J. Lin, S. Monaghan, K. Cherkaoui, L. Floyd, F. Gity, P. Palestri, D. Esseni, L. Selmi, P. Hurley","doi":"10.1109/SISPAD.2019.8870553","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870553","url":null,"abstract":"In this work, we describe how the frequency dependence of conductance (G) and capacitance (C) of a generic MOS capacitor results in peaks of the functions $mathrm {G}/omega$ and $-omega mathrm {dC}/mathrm {d}omega$. By means of TCAD simulations, we show that $mathrm {G}/omega$ and $-omega mathrm {dC}/mathrm {d}omega$ peak at the same value and at the same frequency for every bias point from accumulation to inversion. We illustrate how the properties of the peaks change with the semiconductor doping ($mathrm {N}_{mathrm {D}}$), oxide capacitance (Cox), minority carrier lifetime $(tau_{mathrm{g}})$, interface defect parameters ($mathrm {lt pgt N}_{mathrm {IT}}$, $sigma$) and majority carrier dielectric relaxation time $(tau_{mathrm {r}})$. Finally, we demonstrate how these insights on $mathrm {G}/omega$ and $-omega mathrm {dC}/mathrm {d}omega$ can be used to extract Cox, $mathrm {lt pgt N}_{mathrm {D}}$ and $tau_{mathrm {g}}$ from InGaAs MOSCAP measurements","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"33 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87362119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870456
P. Khakbaz, F. Driussi, A. Gambi, Paolo Giannozzi, S. Venica, David Esseni, A. Gaho, S. Kataria, Max C. Lemme
The experimental results of Metal-graphene (M-G) contact resistance RC have been investigated in-depth by means of Density Functional Theory (DFT). The simulations allowed us to build a consistent picture explaining the RC dependence on the metal contact materials employed in this work and on the applied back-gate voltage. In this respect, the M-G distance is paramount in determining the RC behavior.
{"title":"DFT study of graphene doping due to metal contacts","authors":"P. Khakbaz, F. Driussi, A. Gambi, Paolo Giannozzi, S. Venica, David Esseni, A. Gaho, S. Kataria, Max C. Lemme","doi":"10.1109/SISPAD.2019.8870456","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870456","url":null,"abstract":"The experimental results of Metal-graphene (M-G) contact resistance RC have been investigated in-depth by means of Density Functional Theory (DFT). The simulations allowed us to build a consistent picture explaining the RC dependence on the metal contact materials employed in this work and on the applied back-gate voltage. In this respect, the M-G distance is paramount in determining the RC behavior.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"25 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88520062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/SISPAD.2019.8870505
Wangyong Chen, Linlin Cai, Xiaoyan Liu, G. Du
Trap dynamics based 3D Kinetic Monte Carlo (KMC) simulator is developed to offer physical insights into the electrical characteristics degradation and quantitative reliability evaluation for advanced MOSFETs. The physics-based 3D KMC simulation enables to reproduce the evolution of stress-induced charge distribution in the multi-layer dielectrics and identify the trap impact on the degradation of device performance. Simulation results of UTBB FDSOI MOSFETs reveal that assumption of the uniform charge distribution in the dielectrics induced by stress underestimates the statistical degradation and variability. It also shows that the higher intrinsic trap density of back-gate oxide leads to the larger degradation and its variability, especially for the increased back-gate bias case.
{"title":"Trap Dynamics based 3D Kinetic Monte Carlo Simulation for Reliability Evaluation of UTBB MOSFETs","authors":"Wangyong Chen, Linlin Cai, Xiaoyan Liu, G. Du","doi":"10.1109/SISPAD.2019.8870505","DOIUrl":"https://doi.org/10.1109/SISPAD.2019.8870505","url":null,"abstract":"Trap dynamics based 3D Kinetic Monte Carlo (KMC) simulator is developed to offer physical insights into the electrical characteristics degradation and quantitative reliability evaluation for advanced MOSFETs. The physics-based 3D KMC simulation enables to reproduce the evolution of stress-induced charge distribution in the multi-layer dielectrics and identify the trap impact on the degradation of device performance. Simulation results of UTBB FDSOI MOSFETs reveal that assumption of the uniform charge distribution in the dielectrics induced by stress underestimates the statistical degradation and variability. It also shows that the higher intrinsic trap density of back-gate oxide leads to the larger degradation and its variability, especially for the increased back-gate bias case.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"45 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77671625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：