Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256944
I. Krivorotov, G. Rowlands, T. Rahman, J. Katine, J. Langer, A. Lyle, H. Zhao, J. G. Alzate, A. Kovalev, Y. Tserkovnyak, Z. Zeng, H. W. Jiang, K. Galatsis, Y. Huai, P. Amiri, K. Wang, J. Wang
Since the initial prediction and experimental demonstration of magnetization reversal by spin transfer torque (STT), there has been continuous progress toward the development of nonvolatile magnetic random access memory based on STT switching (STT-RAM) in nanoscale magnetic tunnel junctions (MTJs). In the most common STT-RAM configuration shown in Fig. 1(a), the magnetic moments of the free layer and the pinned polarizing layer of an MTJ lie collinear to one another in the plane of the junction. In this configuration (in-plane STT-RAM or IST-RAM), STT is small during the initial stages of the free layer's magnetic moment reversal, resulting in a relatively long nanosecond-scale switching time. Switching can be greatly accelerated in an alternative STT-RAM configuration, in which a second polarizer with magnetic moment perpendicular to the MTJ plane is added to the magnetic multilayer (orthogonal STT-RAM or OST-RAM). The initial STT from the perpendicular polarizer is large and has been predicted to induce ultrafast precessional switching of the free layer's magnetization on a time scale of 100 ps. The differences in the reversal modes expected for the IST-RAM and OST-RAM devices are illustrated in Figs. 1(c) and 1(d), wherein magnetization switching trajectories are shown for the two types of memory.
{"title":"Ultrafast spin torque memory based on magnetic tunnel junctions with combined in-plane and perpendicular polarizers","authors":"I. Krivorotov, G. Rowlands, T. Rahman, J. Katine, J. Langer, A. Lyle, H. Zhao, J. G. Alzate, A. Kovalev, Y. Tserkovnyak, Z. Zeng, H. W. Jiang, K. Galatsis, Y. Huai, P. Amiri, K. Wang, J. Wang","doi":"10.1109/DRC.2012.6256944","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256944","url":null,"abstract":"Since the initial prediction and experimental demonstration of magnetization reversal by spin transfer torque (STT), there has been continuous progress toward the development of nonvolatile magnetic random access memory based on STT switching (STT-RAM) in nanoscale magnetic tunnel junctions (MTJs). In the most common STT-RAM configuration shown in Fig. 1(a), the magnetic moments of the free layer and the pinned polarizing layer of an MTJ lie collinear to one another in the plane of the junction. In this configuration (in-plane STT-RAM or IST-RAM), STT is small during the initial stages of the free layer's magnetic moment reversal, resulting in a relatively long nanosecond-scale switching time. Switching can be greatly accelerated in an alternative STT-RAM configuration, in which a second polarizer with magnetic moment perpendicular to the MTJ plane is added to the magnetic multilayer (orthogonal STT-RAM or OST-RAM). The initial STT from the perpendicular polarizer is large and has been predicted to induce ultrafast precessional switching of the free layer's magnetization on a time scale of 100 ps. The differences in the reversal modes expected for the IST-RAM and OST-RAM devices are illustrated in Figs. 1(c) and 1(d), wherein magnetization switching trajectories are shown for the two types of memory.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"1 1","pages":"211-212"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88924385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256979
P. Bafna, P. Karkare, S. Srinivasan, S. Chopra, S. Lashkare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, U. Ganguly
Resistive RAM is a very promising candidate for high density non-volatile memory. Although bipolar operation has been shown to work at lower current (essential for low power, mobile computing) [1], a suitable selector device that delivers high current density and high on/off current ratio is challenging [2–4]. We demonstrate a 4F2 bipolar selector device based on the punch-through mechanism. An npn vertical junction device fabricated using in-situ doped epitaxial silicon is presented. Superior on-current density (Jon=1MA/cm2) and high on-off current ratio (Ion/Ioff) of 300–5000 is experimentally demonstrated. TCAD simulations based performance, variability and scalability are presented.
{"title":"Epitaxial Si punch-through based selector for bipolar RRAM","authors":"P. Bafna, P. Karkare, S. Srinivasan, S. Chopra, S. Lashkare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, U. Ganguly","doi":"10.1109/DRC.2012.6256979","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256979","url":null,"abstract":"Resistive RAM is a very promising candidate for high density non-volatile memory. Although bipolar operation has been shown to work at lower current (essential for low power, mobile computing) [1], a suitable selector device that delivers high current density and high on/off current ratio is challenging [2–4]. We demonstrate a 4F2 bipolar selector device based on the punch-through mechanism. An npn vertical junction device fabricated using in-situ doped epitaxial silicon is presented. Superior on-current density (Jon=1MA/cm2) and high on-off current ratio (Ion/Ioff) of 300–5000 is experimentally demonstrated. TCAD simulations based performance, variability and scalability are presented.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"4 1","pages":"115-116"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89116208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256982
Xiaopeng Duan, V. Stephanovich, Y. Semenov, H. Fangohr, M. Franchin, K. W. Kim
We proved for the first time the feasibility of the DW motion control by electric field using the exchange interaction between Gr electrons and the FMI layer. A device prototype is designed and modeled. It is shown an effective magnetic field at 10-100 Oe is generated upon the DW, which leads to a velocity around 30 m/s. 0.5-1 GHz operating frequency is expected in this condition as a bi-state memory. No active current is present and the equivalent circuit model is a set of capacitors. Therefore, low energy consumption is achieved, about 10-16 J/switch.
{"title":"Electric field driven domain wall transfer in hybrid structures","authors":"Xiaopeng Duan, V. Stephanovich, Y. Semenov, H. Fangohr, M. Franchin, K. W. Kim","doi":"10.1109/DRC.2012.6256982","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256982","url":null,"abstract":"We proved for the first time the feasibility of the DW motion control by electric field using the exchange interaction between Gr electrons and the FMI layer. A device prototype is designed and modeled. It is shown an effective magnetic field at 10-100 Oe is generated upon the DW, which leads to a velocity around 30 m/s. 0.5-1 GHz operating frequency is expected in this condition as a bi-state memory. No active current is present and the equivalent circuit model is a set of capacitors. Therefore, low energy consumption is achieved, about 10-16 J/switch.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"1 1","pages":"121-122"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75969881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256951
K. Ganapathi, M. Lundstrom, S. Salahuddin
To summarize, we propose that quasi-saturation in short-channel GFET output characteristics can be effectively engineered by doping in the drain-underlap region and show using self-consistent NEGF simulations that a 0.2% p-type doping can enhance output resistance by 13x and intrinsic gain by 4x in 20 nm gate-length GFETs.
{"title":"Can quasi-saturation in the output characteristics of short-channel graphene field-effect transistors be engineered?","authors":"K. Ganapathi, M. Lundstrom, S. Salahuddin","doi":"10.1109/DRC.2012.6256951","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256951","url":null,"abstract":"To summarize, we propose that quasi-saturation in short-channel GFET output characteristics can be effectively engineered by doping in the drain-underlap region and show using self-consistent NEGF simulations that a 0.2% p-type doping can enhance output resistance by 13x and intrinsic gain by 4x in 20 nm gate-length GFETs.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"100 3 1","pages":"85-86"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77098427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256984
Jiwon Chang, L. Register, S. Banerjee
We have begun to explore the possibility of thin film three dimensional (3D) topological insulator (TI) based tunnel FETs (TFETs), specifically Bi2Se3 here, using quantum ballistic transport simulations with a tight-binding Hamiltonian in the atomic orbital basis including spin degrees of freedom. TI-based TFETs would be analogous in some ways to graphene nanoribbon TFETs, but without the sensitivity to ribbon width and edge roughness, and in some ways to narrow gap III-V TFETs but with substantially thinner quantum well widths.
{"title":"Possible applications of topological insulator thin films for tunnel FETs","authors":"Jiwon Chang, L. Register, S. Banerjee","doi":"10.1109/DRC.2012.6256984","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256984","url":null,"abstract":"We have begun to explore the possibility of thin film three dimensional (3D) topological insulator (TI) based tunnel FETs (TFETs), specifically Bi2Se3 here, using quantum ballistic transport simulations with a tight-binding Hamiltonian in the atomic orbital basis including spin degrees of freedom. TI-based TFETs would be analogous in some ways to graphene nanoribbon TFETs, but without the sensitivity to ribbon width and edge roughness, and in some ways to narrow gap III-V TFETs but with substantially thinner quantum well widths.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"74 1","pages":"31-32"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77404666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256968
A. Nidhi, V. Saripalli, V. Narayanan, Y. Kimura, R. Arghavani, S. Datta
We compared the impact of Fin LER and Lg variations in Si and In0.53Ga0.47As FINFETs, for the first time. Better electrostatics in In0.53Ga0.47As than in Si, due to higher effective channel length from lower SD doping in In0.53Ga0.47As, reduces Lg variation impact. Strong quantum confinement effects in In0.53Ga0.47As FINFET make them more sensitive to Fin LER variation than Si. However, the lower sensitivity to LG variation in In0.53Ga0.47As FINFETs compensates for the increased variation from quantum confinement effect. Interestingly, by considering both Fin LER and LG variations, both devices show similar sensitivity to variation. We conclude that tighter control of Fin LER in In0.53Ga0.47As together with improved short channel immunity will make III-VFINFETs a promising device for 0.5V and below logic applications.
{"title":"Will strong quantum confinement effect limit low VCC logic application of III–V FINFETs?","authors":"A. Nidhi, V. Saripalli, V. Narayanan, Y. Kimura, R. Arghavani, S. Datta","doi":"10.1109/DRC.2012.6256968","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256968","url":null,"abstract":"We compared the impact of Fin LER and Lg variations in Si and In0.53Ga0.47As FINFETs, for the first time. Better electrostatics in In0.53Ga0.47As than in Si, due to higher effective channel length from lower SD doping in In0.53Ga0.47As, reduces Lg variation impact. Strong quantum confinement effects in In0.53Ga0.47As FINFET make them more sensitive to Fin LER variation than Si. However, the lower sensitivity to LG variation in In0.53Ga0.47As FINFETs compensates for the increased variation from quantum confinement effect. Interestingly, by considering both Fin LER and LG variations, both devices show similar sensitivity to variation. We conclude that tighter control of Fin LER in In0.53Ga0.47As together with improved short channel immunity will make III-VFINFETs a promising device for 0.5V and below logic applications.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"85 4 1","pages":"231-232"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76195693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6257045
S. Swandono, A. Penumatcha, J. Cooper
Silicon carbide Schottky diodes have been in commercial production since 2002, their use has saved about $2B in energy and prevented about 10M tons of CO2 from being released into the atmosphere worldwide, equivalent to taking 1.7M automobiles off the roads. Recently, SiC power DMOSFETs entered commercial production, ushering in a new era of opportunity for wide bandgap power electronics. Going forward, high-voltage SiC MOSFETs and IGBTs hold the key to more efficient energy utilization and renewable energy production.
{"title":"Electrical evidence of disorder at the SiO2/4H-SiC MOS interface and its effect on electron transport","authors":"S. Swandono, A. Penumatcha, J. Cooper","doi":"10.1109/DRC.2012.6257045","DOIUrl":"https://doi.org/10.1109/DRC.2012.6257045","url":null,"abstract":"Silicon carbide Schottky diodes have been in commercial production since 2002, their use has saved about $2B in energy and prevented about 10M tons of CO2 from being released into the atmosphere worldwide, equivalent to taking 1.7M automobiles off the roads. Recently, SiC power DMOSFETs entered commercial production, ushering in a new era of opportunity for wide bandgap power electronics. Going forward, high-voltage SiC MOSFETs and IGBTs hold the key to more efficient energy utilization and renewable energy production.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"25 1","pages":"167-168"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88950119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256963
H. Movva, M. Ramón, C. Corbet, F. Chowdhury, G. Carpenter, E. Tutuc, S. Banerjee
The exceptional electronic properties of graphene field-effect transistors (GFETs) make them a promlsmg replacement for conventional Si CMOS transistors for high frequency analog applications. Radio frequency GFETs with intrinsic cut-off frequencies as high as 300GHz have been reported, with theoretically predicted THz frequencies only being limited by fabrication challenges. A major factor responsible for degradation of GFET performance is high series resistance of the access regions between the source/drain contacts and the top-gated graphene channel, which reduces maximum possible drive currents. A back-gate bias can be used to modulate this resistance, but this approach does not provide for independent control of mUltiple GFETs on the same substrate and for GFETs on insulating substrates. GFETs with self-aligned gates overcome this problem by reducing the access region resistance, but their fabrication is not straightforward. Here, we propose a simple scheme of improving GFET performance by reducing the source/drain access resistance using self-aligned charge-transfer doping. A novel and controllable way of "spin-on-doping" of the access regions with chemical dopants is demonstrated.
{"title":"Graphene field-effect transistors with self-aligned spin-on-doping of source/drain access regions","authors":"H. Movva, M. Ramón, C. Corbet, F. Chowdhury, G. Carpenter, E. Tutuc, S. Banerjee","doi":"10.1109/DRC.2012.6256963","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256963","url":null,"abstract":"The exceptional electronic properties of graphene field-effect transistors (GFETs) make them a promlsmg replacement for conventional Si CMOS transistors for high frequency analog applications. Radio frequency GFETs with intrinsic cut-off frequencies as high as 300GHz have been reported, with theoretically predicted THz frequencies only being limited by fabrication challenges. A major factor responsible for degradation of GFET performance is high series resistance of the access regions between the source/drain contacts and the top-gated graphene channel, which reduces maximum possible drive currents. A back-gate bias can be used to modulate this resistance, but this approach does not provide for independent control of mUltiple GFETs on the same substrate and for GFETs on insulating substrates. GFETs with self-aligned gates overcome this problem by reducing the access region resistance, but their fabrication is not straightforward. Here, we propose a simple scheme of improving GFET performance by reducing the source/drain access resistance using self-aligned charge-transfer doping. A novel and controllable way of \"spin-on-doping\" of the access regions with chemical dopants is demonstrated.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"14 1","pages":"175-176"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89961236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256997
S. Mittal, S. Gupta, A. Nainani, M. Abraham, K. Schuegraf, S. Lodha, U. Ganguly
Device variability has become a major concern for CMOS technology [1]. Various sources of variability include Random Dopant Fluctuation (RDF), Gate Edge Roughness (GER) and Line Edge Roughness (LER) [2]. The introduction of FinFETs at 22nm node has two issues. Firstly, the effect of RDF is considerably reduced due to undoped fins [3]. But the aggressive fin width (Wfin) requirement (~Lg/3 [4]) to reduce short channel effect aggravates the electrical impact of LER and makes it greatest contributor to patterning induced variability [2]. Moreover, the edge roughness does not scale with technology and remains independent of the type of lithography used [5]. Secondly, multiple threshold voltage (VT) is achieved in planar technology by various patterned implant steps, which is unavailable for FinFET technology as the fin is undoped. Multiple VT transistor technology is essential for power vs. performance optimization by circuit designers [6]. In this work, we propose an alternative to conventional FinFET structure which can (a) reduce overall variability by 4× reduction in sensitivity to LER and (b) enable multiple VT by applying body bias dynamically without any costly patterned implant steps.
{"title":"Epitaxialy defined (ED) FinFET: to reduce VT variability and enable multiple VT","authors":"S. Mittal, S. Gupta, A. Nainani, M. Abraham, K. Schuegraf, S. Lodha, U. Ganguly","doi":"10.1109/DRC.2012.6256997","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256997","url":null,"abstract":"Device variability has become a major concern for CMOS technology [1]. Various sources of variability include Random Dopant Fluctuation (RDF), Gate Edge Roughness (GER) and Line Edge Roughness (LER) [2]. The introduction of FinFETs at 22nm node has two issues. Firstly, the effect of RDF is considerably reduced due to undoped fins [3]. But the aggressive fin width (Wfin) requirement (~Lg/3 [4]) to reduce short channel effect aggravates the electrical impact of LER and makes it greatest contributor to patterning induced variability [2]. Moreover, the edge roughness does not scale with technology and remains independent of the type of lithography used [5]. Secondly, multiple threshold voltage (VT) is achieved in planar technology by various patterned implant steps, which is unavailable for FinFET technology as the fin is undoped. Multiple VT transistor technology is essential for power vs. performance optimization by circuit designers [6]. In this work, we propose an alternative to conventional FinFET structure which can (a) reduce overall variability by 4× reduction in sensitivity to LER and (b) enable multiple VT by applying body bias dynamically without any costly patterned implant steps.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"10 1","pages":"127-128"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90991301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-18DOI: 10.1109/DRC.2012.6256932
D. Reddy, L. Register, S. Banerjee
Electronic devices have been explored in the past based on resonant single-electron CB (conduction band) to CB tunneling between parallel quasi-two dimensional (2D) quantum wells within III-V heterostructures and their accompanying negative differential resistance (NDR) [1]. Such devices are attractive for high speed electronics, and digital logic circuits also have been demonstrated using a combination of conventional and such NDR FETs [2]. For two graphene layers separated by a tunnel barrier, we recently proposed the ultra-low-voltage Bilayer pseudoSpin FET (BiSFET) which would employ enhanced nonresonant VB (valence band) to CB tunneling, with a nevertheless very sharp NDR characteristic based on a predicted room-temperature many-body superfluid state [3]. However, NDR due to resonant single-particle CB-to-CB or VB-to-VB tunneling may also be achievable in such a structure. Furthermore, the atomically near-perfect 2D nature of the component graphene layers and the conduction/valence band symmetry may offer advantages over III-Vs. Here, we model the I-V characteristics due to single-particle tunneling in such a structure, Fig. 1, using a perturbative tunneling Hamiltonian approach [4,5], and deviations from this simple theory using atomistic tight-binding nonequilibrium Green's function (NEGF) simulation.
{"title":"Bilayer graphene vertical tunneling field effect transistor","authors":"D. Reddy, L. Register, S. Banerjee","doi":"10.1109/DRC.2012.6256932","DOIUrl":"https://doi.org/10.1109/DRC.2012.6256932","url":null,"abstract":"Electronic devices have been explored in the past based on resonant single-electron CB (conduction band) to CB tunneling between parallel quasi-two dimensional (2D) quantum wells within III-V heterostructures and their accompanying negative differential resistance (NDR) [1]. Such devices are attractive for high speed electronics, and digital logic circuits also have been demonstrated using a combination of conventional and such NDR FETs [2]. For two graphene layers separated by a tunnel barrier, we recently proposed the ultra-low-voltage Bilayer pseudoSpin FET (BiSFET) which would employ enhanced nonresonant VB (valence band) to CB tunneling, with a nevertheless very sharp NDR characteristic based on a predicted room-temperature many-body superfluid state [3]. However, NDR due to resonant single-particle CB-to-CB or VB-to-VB tunneling may also be achievable in such a structure. Furthermore, the atomically near-perfect 2D nature of the component graphene layers and the conduction/valence band symmetry may offer advantages over III-Vs. Here, we model the I-V characteristics due to single-particle tunneling in such a structure, Fig. 1, using a perturbative tunneling Hamiltonian approach [4,5], and deviations from this simple theory using atomistic tight-binding nonequilibrium Green's function (NEGF) simulation.","PeriodicalId":6808,"journal":{"name":"70th Device Research Conference","volume":"23 1","pages":"73-74"},"PeriodicalIF":0.0,"publicationDate":"2012-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87275691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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