Pub Date : 2021-12-06DOI: 10.1109/SSLChinaIFWS54608.2021.9675188
Hao Lu, Bin Hou, Ling Yang, Teng Huo, Zeyan Si, Meng Zhang, Mei Wu, Xiao-hua Ma, Y. Hao
In this paper, we have proposed a novel ohmic contact on undoped AlGaN/GaN heterostructures using the ternary SixTiyAl alloy pre-deposition ohmic contacts to reduce the contact resistance (RC) and improve the ohmic surface morphology. The use of ternary alloys simultaneously achieves n-type doping of barrier material by thermal annealing of Si and uniform Ti/Al contact with semiconductors. The systematical investigation of the parameters, including the pre-deposition layer and annealing temperature, have been performed. Low contact resistance of 0.34 Ω'mm and a specific resistivity (ρC) of 2.9 × 10−6 Ω.cm2 was achieved for the proposed metal scheme annealed at 900°C, which was superior compared with conventional Ti/Al/Ni/Au ohmic contacts (8.3 × 10−6 Ω.cm2, 0.56 Ω.mm). Atomic force microscope (AFM) compares the surface root mean square (RMS) roughness of the varied samples at the different annealing temperature. Through the results presented here, the ternary alloyed layer has significant advantages over monolayer Si or reference sample. These results are believed to facilitate the process of the GaN HEMT applied for next-generation communication systems.
{"title":"Improved Ohmic Contact Performance on Undoped AlGaN/GaN HEMTs Using by Ternary Alloy Predeposition","authors":"Hao Lu, Bin Hou, Ling Yang, Teng Huo, Zeyan Si, Meng Zhang, Mei Wu, Xiao-hua Ma, Y. Hao","doi":"10.1109/SSLChinaIFWS54608.2021.9675188","DOIUrl":"https://doi.org/10.1109/SSLChinaIFWS54608.2021.9675188","url":null,"abstract":"In this paper, we have proposed a novel ohmic contact on undoped AlGaN/GaN heterostructures using the ternary SixTiyAl alloy pre-deposition ohmic contacts to reduce the contact resistance (RC) and improve the ohmic surface morphology. The use of ternary alloys simultaneously achieves n-type doping of barrier material by thermal annealing of Si and uniform Ti/Al contact with semiconductors. The systematical investigation of the parameters, including the pre-deposition layer and annealing temperature, have been performed. Low contact resistance of 0.34 Ω'mm and a specific resistivity (ρC) of 2.9 × 10−6 Ω.cm2 was achieved for the proposed metal scheme annealed at 900°C, which was superior compared with conventional Ti/Al/Ni/Au ohmic contacts (8.3 × 10−6 Ω.cm2, 0.56 Ω.mm). Atomic force microscope (AFM) compares the surface root mean square (RMS) roughness of the varied samples at the different annealing temperature. Through the results presented here, the ternary alloyed layer has significant advantages over monolayer Si or reference sample. These results are believed to facilitate the process of the GaN HEMT applied for next-generation communication systems.","PeriodicalId":6816,"journal":{"name":"2021 18th China International Forum on Solid State Lighting & 2021 7th International Forum on Wide Bandgap Semiconductors (SSLChina: IFWS)","volume":"45 1","pages":"65-67"},"PeriodicalIF":0.0,"publicationDate":"2021-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73802491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-06DOI: 10.1109/SSLChinaIFWS54608.2021.9675187
Lei Song, M. Cai, Hengjian He, Kailin Zhang
Silicon carbide (SiC) power device has a leap forward improvement in various performance indexes compared with the existing silicon-based power devices, and is suitable for higher frequency working occasions. Its high switching speed makes it more sensitive to stray parameters and easier to cause voltage and current oscillation. Therefore, reducing the inductance of power module has become the key to module design. Usually when designing the layout of the power module, it is necessary to establish the 3d model and then use the Q3d software to extract the internal circuit inductance of the device. The process is complicated and the design cycle is long. To solve this problem, this article focuses on the rapid evaluation method of loop inductance in the process of power module layout design, and proposes a faster, simpler, and relatively accurate calculation model based on the existing theories - Inductance Calculation Model of Arbitrary Shape Open-loop Circuit. Then, the convenience and accuracy of the equivalent closed loop model are verified by calculating three different IGBT layout loop inductances. This method is conducive to the rapid iteration of the power module layout design and shortens the design cycle.
{"title":"A Fast Calculation Model for Parasitic Inductance of SiC Power Devices","authors":"Lei Song, M. Cai, Hengjian He, Kailin Zhang","doi":"10.1109/SSLChinaIFWS54608.2021.9675187","DOIUrl":"https://doi.org/10.1109/SSLChinaIFWS54608.2021.9675187","url":null,"abstract":"Silicon carbide (SiC) power device has a leap forward improvement in various performance indexes compared with the existing silicon-based power devices, and is suitable for higher frequency working occasions. Its high switching speed makes it more sensitive to stray parameters and easier to cause voltage and current oscillation. Therefore, reducing the inductance of power module has become the key to module design. Usually when designing the layout of the power module, it is necessary to establish the 3d model and then use the Q3d software to extract the internal circuit inductance of the device. The process is complicated and the design cycle is long. To solve this problem, this article focuses on the rapid evaluation method of loop inductance in the process of power module layout design, and proposes a faster, simpler, and relatively accurate calculation model based on the existing theories - Inductance Calculation Model of Arbitrary Shape Open-loop Circuit. Then, the convenience and accuracy of the equivalent closed loop model are verified by calculating three different IGBT layout loop inductances. This method is conducive to the rapid iteration of the power module layout design and shortens the design cycle.","PeriodicalId":6816,"journal":{"name":"2021 18th China International Forum on Solid State Lighting & 2021 7th International Forum on Wide Bandgap Semiconductors (SSLChina: IFWS)","volume":"102 1","pages":"29-32"},"PeriodicalIF":0.0,"publicationDate":"2021-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80515275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-06DOI: 10.1109/SSLChinaIFWS54608.2021.9675238
Xiaoxiao Ji, Fei Wang, Luqiao Yin, Jianhua Zhang
With the advent of the Micro-light-emitting diodes, it has become the focus of display and visible light communication research. However, as the LED chip size shrinks, the difficulty of integration increase gradually. Nowadays, the integration of Micro- LEDs in display is still a challenge for commercialization. In this work, we conducted a comparative study by finite element method simulation to reveal the influencing factors of bonding yield. The results show that stress concentrates at the junction of the bumps and electrodes of Micro-LED chips, and the stress concentration at the corner of Micro-LED array is more seriously. By altering the parameters of bumps, such as shapes and materials to reduce the stress and stress concentration. Numerical simulate results provide theoretical basis for reducing stress and stress concentration and optimizing the bump shape.
{"title":"Simulation study on thermal mechanical properties of 4×4 Micro-LED array in flip-chip bonding process","authors":"Xiaoxiao Ji, Fei Wang, Luqiao Yin, Jianhua Zhang","doi":"10.1109/SSLChinaIFWS54608.2021.9675238","DOIUrl":"https://doi.org/10.1109/SSLChinaIFWS54608.2021.9675238","url":null,"abstract":"With the advent of the Micro-light-emitting diodes, it has become the focus of display and visible light communication research. However, as the LED chip size shrinks, the difficulty of integration increase gradually. Nowadays, the integration of Micro- LEDs in display is still a challenge for commercialization. In this work, we conducted a comparative study by finite element method simulation to reveal the influencing factors of bonding yield. The results show that stress concentrates at the junction of the bumps and electrodes of Micro-LED chips, and the stress concentration at the corner of Micro-LED array is more seriously. By altering the parameters of bumps, such as shapes and materials to reduce the stress and stress concentration. Numerical simulate results provide theoretical basis for reducing stress and stress concentration and optimizing the bump shape.","PeriodicalId":6816,"journal":{"name":"2021 18th China International Forum on Solid State Lighting & 2021 7th International Forum on Wide Bandgap Semiconductors (SSLChina: IFWS)","volume":"17 1","pages":"135-138"},"PeriodicalIF":0.0,"publicationDate":"2021-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76635925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, 1.2kV SiC MOSFET integrated Junction-Barrier-Schottky diode (JMOS) is fabricated. The Schottky width is 2μm. The static characteristic of the JMOS is evaluated at room and elevated temperature. The single pulse avalanche robustness under Vgs= −5V is studied. Moreover, excessive gate leakage current is observed during the avalanche. The mechanism of gate leakage current is studied by simulation. The high impact ionization and high temperature in JFET region causes high gate leakage current. The transfer characteristic after each UIS test is monitored to confirm ionized holes inject into gate oxide during the avalanche.
本文制作了1.2kV SiC MOSFET集成结垒肖特基二极管(JMOS)。肖特基宽度为2μm。对JMOS在室温和高温下的静态特性进行了评价。研究了Vgs= - 5V条件下的单脉冲雪崩鲁棒性。此外，在雪崩过程中观察到过大的栅漏电流。通过仿真研究了栅漏电流产生的机理。JFET区域的高冲击电离和高温导致了高栅极漏电流。监测每次UIS测试后的转移特性，以确认雪崩期间注入栅极氧化物的电离孔。
{"title":"Avalanche Robustness of 1.2kV SiC MOSFET with Integrated Junction-Barrier-Schottky Diode and Gate Leakage Current Analysis","authors":"Chongyu Jiang, Hongyi Xu, Zijian Gao, Na Ren, Qing Guo, Kuang Sheng","doi":"10.1109/SSLChinaIFWS54608.2021.9675259","DOIUrl":"https://doi.org/10.1109/SSLChinaIFWS54608.2021.9675259","url":null,"abstract":"In this work, 1.2kV SiC MOSFET integrated Junction-Barrier-Schottky diode (JMOS) is fabricated. The Schottky width is 2μm. The static characteristic of the JMOS is evaluated at room and elevated temperature. The single pulse avalanche robustness under Vgs= −5V is studied. Moreover, excessive gate leakage current is observed during the avalanche. The mechanism of gate leakage current is studied by simulation. The high impact ionization and high temperature in JFET region causes high gate leakage current. The transfer characteristic after each UIS test is monitored to confirm ionized holes inject into gate oxide during the avalanche.","PeriodicalId":6816,"journal":{"name":"2021 18th China International Forum on Solid State Lighting & 2021 7th International Forum on Wide Bandgap Semiconductors (SSLChina: IFWS)","volume":"1989 1","pages":"25-28"},"PeriodicalIF":0.0,"publicationDate":"2021-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82740962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-06DOI: 10.1109/SSLChinaIFWS54608.2021.9675152
Lei Ge, Yan Peng, Xiwei Wang, Dufu Wang, Mingsheng Xu, Xiangang Xu
In this paper, a microwave plasma chemical vapor deposition (MPCVD) method is used to homoepitaxially epitaxial diamond film on a high-pressure high temperature(HPHT) diamond substrate, and a metal-semiconductor field effect transistor (MESFET) solar-blind detector is prepared to measure the photoelectric response performance of the detector. The results show that the detector made of diamond has a good photoelectric response to deep ultraviolet light.
{"title":"Diamond Metal-Semiconductor Field-Effect-Transistor-based Solar Blind Detector","authors":"Lei Ge, Yan Peng, Xiwei Wang, Dufu Wang, Mingsheng Xu, Xiangang Xu","doi":"10.1109/SSLChinaIFWS54608.2021.9675152","DOIUrl":"https://doi.org/10.1109/SSLChinaIFWS54608.2021.9675152","url":null,"abstract":"In this paper, a microwave plasma chemical vapor deposition (MPCVD) method is used to homoepitaxially epitaxial diamond film on a high-pressure high temperature(HPHT) diamond substrate, and a metal-semiconductor field effect transistor (MESFET) solar-blind detector is prepared to measure the photoelectric response performance of the detector. The results show that the detector made of diamond has a good photoelectric response to deep ultraviolet light.","PeriodicalId":6816,"journal":{"name":"2021 18th China International Forum on Solid State Lighting & 2021 7th International Forum on Wide Bandgap Semiconductors (SSLChina: IFWS)","volume":"72 1","pages":"91-92"},"PeriodicalIF":0.0,"publicationDate":"2021-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88476430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-06DOI: 10.1109/SSLChinaIFWS54608.2021.9675262
Zheming Wang, Liguo Zhang, Rongkun Ji, Xuan Zhang, Yong Cai, B. Zhang
Activation annealing of implantation doping of GaN has been restricted by the phenomenon of GaN decomposition at high temperatures. Purpose of high temperature annealing is to recover the lattice damage caused by implantation and to activate the implanted atoms to substitute the lattice atoms. Since elevating the substrate temperature during implantation has been proved to be effective to reduce the lattice damage and help to enhance the activation efficiency in other semiconductor materials, in this work such a method was applied to Si implantation in GaN. The samples were implanted at different temperatures from room temperature to 500°C with a dose of 2×1015cm−2 and subsequently annealed at 1200°C for 5 min. Both structural and electrical characterizations were performed before and after annealing to investigate the effect of implantation temperature on Si implantation in GaN.
{"title":"Si Implantation in GaN at Elevated Temperatures","authors":"Zheming Wang, Liguo Zhang, Rongkun Ji, Xuan Zhang, Yong Cai, B. Zhang","doi":"10.1109/SSLChinaIFWS54608.2021.9675262","DOIUrl":"https://doi.org/10.1109/SSLChinaIFWS54608.2021.9675262","url":null,"abstract":"Activation annealing of implantation doping of GaN has been restricted by the phenomenon of GaN decomposition at high temperatures. Purpose of high temperature annealing is to recover the lattice damage caused by implantation and to activate the implanted atoms to substitute the lattice atoms. Since elevating the substrate temperature during implantation has been proved to be effective to reduce the lattice damage and help to enhance the activation efficiency in other semiconductor materials, in this work such a method was applied to Si implantation in GaN. The samples were implanted at different temperatures from room temperature to 500°C with a dose of 2×1015cm−2 and subsequently annealed at 1200°C for 5 min. Both structural and electrical characterizations were performed before and after annealing to investigate the effect of implantation temperature on Si implantation in GaN.","PeriodicalId":6816,"journal":{"name":"2021 18th China International Forum on Solid State Lighting & 2021 7th International Forum on Wide Bandgap Semiconductors (SSLChina: IFWS)","volume":"17 1","pages":"39-41"},"PeriodicalIF":0.0,"publicationDate":"2021-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73023474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-06DOI: 10.1109/SSLChinaIFWS54608.2021.9675258
Xi Li, Wei Gao, Yanwei Shan, Bo Zhang
A novel power semiconductor device, GaN HEMT, has the advantages of high power density and high operating frequency. Thermal problems are caused by high power operation of the device, however, there is no specific test standard for GaN HEMT thermal resistance at present. For GaN HEMT devices with high gate impedance, the method of using gate source diode to extract junction temperature is not suitable. Therefore, in this paper, we used the on-resistance of the device as the thermal parameter of this type of device, but it is found in the test that the on-resistance of the device is unstable due to the threshold voltage drift, which leads to poor repeatability of the thermal resistance test results of the same device. The addition of high temperature baking in the post test restores the threshold voltage of the device to the initial state, so as to achieve the purpose of stable and repeatable thermal resistance test results of GaN HEMT devices. In addition, this paper does an in-depth analysis of the mechanism of poor thermal resistance test repeatability for this type of device.
GaN HEMT是一种新型的功率半导体器件，具有高功率密度和高工作频率的优点。器件的高功率运行会引起热问题，但目前对于GaN HEMT热阻尚无具体的测试标准。对于具有高栅阻抗的GaN HEMT器件，采用栅极源二极管提取结温的方法是不合适的。因此，在本文中，我们使用器件的导通电阻作为这类器件的热参数，但在测试中发现，由于阈值电压漂移，器件的导通电阻不稳定，导致同一器件的热阻测试结果重复性差。后测中加入高温烘烤，使器件的阈值电压恢复到初始状态，从而达到GaN HEMT器件热阻测试结果稳定、可重复的目的。此外，本文还对该类器件热阻测试重复性差的机理进行了深入分析。
{"title":"Study on Thermal Transient Measurement Method and Mechanism of GaN HEMT Power Devices","authors":"Xi Li, Wei Gao, Yanwei Shan, Bo Zhang","doi":"10.1109/SSLChinaIFWS54608.2021.9675258","DOIUrl":"https://doi.org/10.1109/SSLChinaIFWS54608.2021.9675258","url":null,"abstract":"A novel power semiconductor device, GaN HEMT, has the advantages of high power density and high operating frequency. Thermal problems are caused by high power operation of the device, however, there is no specific test standard for GaN HEMT thermal resistance at present. For GaN HEMT devices with high gate impedance, the method of using gate source diode to extract junction temperature is not suitable. Therefore, in this paper, we used the on-resistance of the device as the thermal parameter of this type of device, but it is found in the test that the on-resistance of the device is unstable due to the threshold voltage drift, which leads to poor repeatability of the thermal resistance test results of the same device. The addition of high temperature baking in the post test restores the threshold voltage of the device to the initial state, so as to achieve the purpose of stable and repeatable thermal resistance test results of GaN HEMT devices. In addition, this paper does an in-depth analysis of the mechanism of poor thermal resistance test repeatability for this type of device.","PeriodicalId":6816,"journal":{"name":"2021 18th China International Forum on Solid State Lighting & 2021 7th International Forum on Wide Bandgap Semiconductors (SSLChina: IFWS)","volume":"31 1","pages":"231-234"},"PeriodicalIF":0.0,"publicationDate":"2021-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74435220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-06DOI: 10.1109/SSLChinaIFWS54608.2021.9675175
Ge Wenjing, Jiang Minyu, Cao Jing, Yang Xiu
This paper presented the process and results of the questionnaire survey and brightness measurement toward the lobby and corridor space of Costa Venezia Cruise. The questionnaire content includes Visual Perception and Lighting Evaluation. The brightness measurement contents include average brightness, maximum brightness, glare index. The conclusion reached are as follows: 1)subjects are highly satisfied with the lighting environment of the lobby, 41%(13 subjects) of the subjects rated uncomfortable / comfortable as 6, uneven / uniform and cold / warm as 5; 2) 14% (4 subjects) and 7% (2 subjects) of the subjects rated dazzling / non-dazzling at the corridor as −2, −1 respectively; 3)If the 0–3 evaluation is defined as satisfactory, the average satisfaction degree of the Visual Perception and Lighting Evaluation of the lobby and corridor will reach more than 90%; 4)The difference toward the average brightness between the lobby and the corridor is not large, and the ratio is 1: 1.5; the difference toward the maximum brightness is large, the ratio is 1: 60; 5)Within a certain range of the brightness value changes, Visual Perception evaluation satisfaction and the indoor brightness show a significant negative correlation.
{"title":"Research on Evaluation of Lighting Design for Cruise Interior Public Space: a Case study of Costa Venezia Cruise","authors":"Ge Wenjing, Jiang Minyu, Cao Jing, Yang Xiu","doi":"10.1109/SSLChinaIFWS54608.2021.9675175","DOIUrl":"https://doi.org/10.1109/SSLChinaIFWS54608.2021.9675175","url":null,"abstract":"This paper presented the process and results of the questionnaire survey and brightness measurement toward the lobby and corridor space of Costa Venezia Cruise. The questionnaire content includes Visual Perception and Lighting Evaluation. The brightness measurement contents include average brightness, maximum brightness, glare index. The conclusion reached are as follows: 1)subjects are highly satisfied with the lighting environment of the lobby, 41%(13 subjects) of the subjects rated uncomfortable / comfortable as 6, uneven / uniform and cold / warm as 5; 2) 14% (4 subjects) and 7% (2 subjects) of the subjects rated dazzling / non-dazzling at the corridor as −2, −1 respectively; 3)If the 0–3 evaluation is defined as satisfactory, the average satisfaction degree of the Visual Perception and Lighting Evaluation of the lobby and corridor will reach more than 90%; 4)The difference toward the average brightness between the lobby and the corridor is not large, and the ratio is 1: 1.5; the difference toward the maximum brightness is large, the ratio is 1: 60; 5)Within a certain range of the brightness value changes, Visual Perception evaluation satisfaction and the indoor brightness show a significant negative correlation.","PeriodicalId":6816,"journal":{"name":"2021 18th China International Forum on Solid State Lighting & 2021 7th International Forum on Wide Bandgap Semiconductors (SSLChina: IFWS)","volume":"1 1","pages":"165-168"},"PeriodicalIF":0.0,"publicationDate":"2021-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81947169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
It is well known that despite the superior performance of SiC MOSFETs, reliability issues persist and limit their development. In this work, short-circuit (SC) stresses have been applied to commercial SiC trench MOSFETs to verify their reliability under extreme conditions. First, a single-pulse SC stress was applied to the device. Two different short-circuit failure mechanisms were identified. One type of failure was thermal runaway and the other was gate failure. Subsequently, multiple non-destructive short-circuit pulses have been applied to the device. After the stress, the shift in the device static characteristics has been measured and recorded to determine the effects of the stress on the degradation of the device's electrical parameters. Finally, TCAD device simulations have been used to help understand the intrinsic degradation mechanism.
{"title":"Degradation of 4H-SiC Trench MOSFET under single and repetitive short-circuit stress","authors":"Yuan Zou, Jue Wang, Li Liu, Hongyi Xu, Hengyu Wang, Kuang Sheng","doi":"10.1109/SSLChinaIFWS54608.2021.9675237","DOIUrl":"https://doi.org/10.1109/SSLChinaIFWS54608.2021.9675237","url":null,"abstract":"It is well known that despite the superior performance of SiC MOSFETs, reliability issues persist and limit their development. In this work, short-circuit (SC) stresses have been applied to commercial SiC trench MOSFETs to verify their reliability under extreme conditions. First, a single-pulse SC stress was applied to the device. Two different short-circuit failure mechanisms were identified. One type of failure was thermal runaway and the other was gate failure. Subsequently, multiple non-destructive short-circuit pulses have been applied to the device. After the stress, the shift in the device static characteristics has been measured and recorded to determine the effects of the stress on the degradation of the device's electrical parameters. Finally, TCAD device simulations have been used to help understand the intrinsic degradation mechanism.","PeriodicalId":6816,"journal":{"name":"2021 18th China International Forum on Solid State Lighting & 2021 7th International Forum on Wide Bandgap Semiconductors (SSLChina: IFWS)","volume":"80 3 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2021-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89429496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-06DOI: 10.1109/SSLChinaIFWS54608.2021.9675184
Bing Zhang, Pengjie Cui, Haitian Zhao
The intensity of glare in Low Mounting Height Luminaires(LMHL) is positively correlated with the light output efficiency of the lamps. The light interceptor that eliminates glare will cause the light output efficiency of the lamps to be extremely low. This paper analyzes the light output of the street lamps based on the driver's visual needs, and puts forward the concept of effective luminous flux for road lighting. The street lamp light is divided into three parts: effective luminous flux, invalid luminous flux and harmful luminous flux; according to the concept of effective luminous flux, a multi-channel luminaire structure is designed to convert invalid luminous flux into effective luminous flux and eliminate harmful luminous flux. The software simulation experiment verifies the relationship between the luminous efficiency of the lamp and the number of channels, and the final sample is made to prove the feasibility of the structure. The experimental results show that the luminous efficiency of the luminaire has a linear relationship with the number of channels. It is 67%; the light output efficiency of the dual-channel sample is increased by 34% compared with the single-channel sample; the light output efficiency of the four-channel sample is increased by 92% compared to the single-channel sample. Therefore, the multi-channel luminaire structure can simultaneously solve the problems of intense glare and high energy consumption in LMHL.
{"title":"Research on Glare-free Lamps Based on the Concept of Effective Luminous Flux","authors":"Bing Zhang, Pengjie Cui, Haitian Zhao","doi":"10.1109/SSLChinaIFWS54608.2021.9675184","DOIUrl":"https://doi.org/10.1109/SSLChinaIFWS54608.2021.9675184","url":null,"abstract":"The intensity of glare in Low Mounting Height Luminaires(LMHL) is positively correlated with the light output efficiency of the lamps. The light interceptor that eliminates glare will cause the light output efficiency of the lamps to be extremely low. This paper analyzes the light output of the street lamps based on the driver's visual needs, and puts forward the concept of effective luminous flux for road lighting. The street lamp light is divided into three parts: effective luminous flux, invalid luminous flux and harmful luminous flux; according to the concept of effective luminous flux, a multi-channel luminaire structure is designed to convert invalid luminous flux into effective luminous flux and eliminate harmful luminous flux. The software simulation experiment verifies the relationship between the luminous efficiency of the lamp and the number of channels, and the final sample is made to prove the feasibility of the structure. The experimental results show that the luminous efficiency of the luminaire has a linear relationship with the number of channels. It is 67%; the light output efficiency of the dual-channel sample is increased by 34% compared with the single-channel sample; the light output efficiency of the four-channel sample is increased by 92% compared to the single-channel sample. Therefore, the multi-channel luminaire structure can simultaneously solve the problems of intense glare and high energy consumption in LMHL.","PeriodicalId":6816,"journal":{"name":"2021 18th China International Forum on Solid State Lighting & 2021 7th International Forum on Wide Bandgap Semiconductors (SSLChina: IFWS)","volume":"11 1","pages":"125-130"},"PeriodicalIF":0.0,"publicationDate":"2021-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76439209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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