Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537342
Won Ji Park, Min Guk Kang, J. Oh, Shaofeng Ding, Ji Hyung Kim, Jesse Hwang, Yun Ki Choi, Jung-Ho Park, Won Hyoung Lee, Seung Ki Nam, Seong Wook Moon, J. Youn, Jeonghoon Ahn
Interposer to interconnect between the electronic components has been developed for the last few decades because it can improve the system performance effectively, compared to the system with intra-chip wiring. In this paper, the integrated stack capacitor (ISC) embedded interposer system was demonstrated with the approximately 8 times higher capacitance (Ci) than interposer with MIM (Metal / Insulator / Metal capacitor). The resistance and leakage current were measured and the results indicate that there were no the open fail inside the system. In addition, WLR (Wafer Level Reliability) was proved using TDDB (Time Dependent Dielectric Breakdown), Vramp, HTS (High Temperature Storage), TC (Thermal Cycle) and Pre-con tests and finally, all requirements of WLR are satisfied.
在过去的几十年里，电子元件之间的互连被开发出来，因为与芯片内布线的系统相比，它可以有效地提高系统的性能。本文演示了集成堆叠电容器(ISC)嵌入式中间体系统，其电容(Ci)比MIM(金属/绝缘体/金属电容器)中间体高约8倍。测量了系统的电阻和漏电流，结果表明系统内部不存在开路故障。此外，通过TDDB (Time Dependent Dielectric击穿)、Vramp、HTS (High Temperature Storage)、TC (Thermal Cycle)和Pre-con测试验证了WLR(晶圆级可靠性)，最终满足了WLR的所有要求。
{"title":"Fabrication and Characterization of ISC embedded Interposer for High Performance Interconnection","authors":"Won Ji Park, Min Guk Kang, J. Oh, Shaofeng Ding, Ji Hyung Kim, Jesse Hwang, Yun Ki Choi, Jung-Ho Park, Won Hyoung Lee, Seung Ki Nam, Seong Wook Moon, J. Youn, Jeonghoon Ahn","doi":"10.1109/IITC51362.2021.9537342","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537342","url":null,"abstract":"Interposer to interconnect between the electronic components has been developed for the last few decades because it can improve the system performance effectively, compared to the system with intra-chip wiring. In this paper, the integrated stack capacitor (ISC) embedded interposer system was demonstrated with the approximately 8 times higher capacitance (Ci) than interposer with MIM (Metal / Insulator / Metal capacitor). The resistance and leakage current were measured and the results indicate that there were no the open fail inside the system. In addition, WLR (Wafer Level Reliability) was proved using TDDB (Time Dependent Dielectric Breakdown), Vramp, HTS (High Temperature Storage), TC (Thermal Cycle) and Pre-con tests and finally, all requirements of WLR are satisfied.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"124 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79494791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537535
V. Vega-Gonzalez, D. Montero, J. Versluijs, O. Pedreira, N. Jourdan, H. Puliyalil, B. Chehab, T. Peissker, A. Haider, D. Batuk, G. Martinez, J. Geypen, Q. Le, N. Bazzazian, N. Heylen, M. H. van der Veen, Z. El-Mekki, T. Webers, H. Vats, L. Rynders, M. Cupák, J. Uk-Lee, Y. Drissi, L. Halipré, W. Gillijns, A. Charley, P. Verdonck, T. Witters, S. Gompel, Y. Kimura, I. Ciofi, B. de Wachter, J. Swerts, E. Grieten, M. Ercken, R. Kim, K. Croes, P. Leray, M. Jaysankar, N. Nagesh, L. Ramakers, G. Murdoch, S. Park, Z. Tokei, E. Dentoni-Litta, N. Horiguchi
The integration of high aspect-ratio (AR) vias or supervias (SV) with a min CDbottom = 10.5 nm and a max AR = 5.8 is demonstrated, allowing a comparison between ruthenium (Ru) and cobalt (Co) chemical vapor deposition (CVD) metallizations. Ru gave a resistance ~2x higher than Co when a 1.1 nm titanium nitride (TiN) film, realized by atomic layer deposition (ALD), was used as an adhesion/nucleation layer. The lowest SV resistance of 56 Ω at the median was obtained with 0.3 nm of titanium oxide (TiOx) ALD and Ru CVD. This configuration gave a 3.4x lower resistance than the equivalent scheme with 0.3 nm TiN ALD and 15% lower resistance than the stacked-via configuration (with 0.3 nm TiOx and Ru fill), meaning that an IR-drop penalty is avoided when compared to the stacked-via approach. A congestion reduction can also be expected from the CD reduction of the SVs as the exclusion area in the intermediate layer can be smaller. Thermal shock tests for both Ru and Co SVs produced no failure after 1000 cycles between −50 °C and 125 °C, and 250 hours.
{"title":"Process Integration of High Aspect Ratio Vias with a Comparison between Co and Ru Metallizations","authors":"V. Vega-Gonzalez, D. Montero, J. Versluijs, O. Pedreira, N. Jourdan, H. Puliyalil, B. Chehab, T. Peissker, A. Haider, D. Batuk, G. Martinez, J. Geypen, Q. Le, N. Bazzazian, N. Heylen, M. H. van der Veen, Z. El-Mekki, T. Webers, H. Vats, L. Rynders, M. Cupák, J. Uk-Lee, Y. Drissi, L. Halipré, W. Gillijns, A. Charley, P. Verdonck, T. Witters, S. Gompel, Y. Kimura, I. Ciofi, B. de Wachter, J. Swerts, E. Grieten, M. Ercken, R. Kim, K. Croes, P. Leray, M. Jaysankar, N. Nagesh, L. Ramakers, G. Murdoch, S. Park, Z. Tokei, E. Dentoni-Litta, N. Horiguchi","doi":"10.1109/IITC51362.2021.9537535","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537535","url":null,"abstract":"The integration of high aspect-ratio (AR) vias or supervias (SV) with a min CDbottom = 10.5 nm and a max AR = 5.8 is demonstrated, allowing a comparison between ruthenium (Ru) and cobalt (Co) chemical vapor deposition (CVD) metallizations. Ru gave a resistance ~2x higher than Co when a 1.1 nm titanium nitride (TiN) film, realized by atomic layer deposition (ALD), was used as an adhesion/nucleation layer. The lowest SV resistance of 56 Ω at the median was obtained with 0.3 nm of titanium oxide (TiOx) ALD and Ru CVD. This configuration gave a 3.4x lower resistance than the equivalent scheme with 0.3 nm TiN ALD and 15% lower resistance than the stacked-via configuration (with 0.3 nm TiOx and Ru fill), meaning that an IR-drop penalty is avoided when compared to the stacked-via approach. A congestion reduction can also be expected from the CD reduction of the SVs as the exclusion area in the intermediate layer can be smaller. Thermal shock tests for both Ru and Co SVs produced no failure after 1000 cycles between −50 °C and 125 °C, and 250 hours.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"39 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81399944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537336
H. Kino, T. Fukushima, Tetsu Tanaka
The resistance of the metal wirings in the integrated circuits increases due to the decrease of the mean free path of electrons with the temperature increase. This thermal instability requires redundancy circuits. On the other hand, several materials have the saturation characteristics of the mean free path around room temperature. The anti-perovskite manganese nitride compound material is one of them. The anti-perovskite manganese nitride compounds show a flat resistance-temperature curve around room temperature. However, the flat resistance-temperature curves have been obtained with only the sintered bulk materials. It has not become clear the characteristics of the manganese nitride compounds in the micro/nanoscale. In this study, we proposed manganese nitride wiring for high-thermal-stability systems. Then, we fabricated and evaluated the micro/nanoscale manganese nitride compound wiring with the complementary metal-oxide-semiconductor compatible process.
{"title":"Development of Manganese Nitride Resistor with Near-Zero Temperature-Coefficient of Resistance to Achieve High-Thermal-Stability ICs","authors":"H. Kino, T. Fukushima, Tetsu Tanaka","doi":"10.1109/IITC51362.2021.9537336","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537336","url":null,"abstract":"The resistance of the metal wirings in the integrated circuits increases due to the decrease of the mean free path of electrons with the temperature increase. This thermal instability requires redundancy circuits. On the other hand, several materials have the saturation characteristics of the mean free path around room temperature. The anti-perovskite manganese nitride compound material is one of them. The anti-perovskite manganese nitride compounds show a flat resistance-temperature curve around room temperature. However, the flat resistance-temperature curves have been obtained with only the sintered bulk materials. It has not become clear the characteristics of the manganese nitride compounds in the micro/nanoscale. In this study, we proposed manganese nitride wiring for high-thermal-stability systems. Then, we fabricated and evaluated the micro/nanoscale manganese nitride compound wiring with the complementary metal-oxide-semiconductor compatible process.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"11 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82447280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537312
T. Tabata, P. Raynal, F. Rozé, Sebastien Halty, Louis Thuries, F. Cristiano, E. Scheid, F. Mazzamuto
UV nanosecond pulsed laser annealing (UV NLA) enables both surface-localized heating and short timescale high temperature processing, which can be advantageous to reduce metal line resistance by enlarging metal grains in lines or in thin films, while maintaining the integrity and performance of surrounding structures. In this work UV NLA is applied on a typical Cu thin film, demonstrating a mean grain size of over 1 μm and 400 nm in a melt and sub-melt regime, respectively. Along with such grain enlargement, film resistivity is also reduced.
{"title":"Copper Large-Scale Grain Growth by UV Nanosecond Pulsed Laser Annealing","authors":"T. Tabata, P. Raynal, F. Rozé, Sebastien Halty, Louis Thuries, F. Cristiano, E. Scheid, F. Mazzamuto","doi":"10.1109/IITC51362.2021.9537312","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537312","url":null,"abstract":"UV nanosecond pulsed laser annealing (UV NLA) enables both surface-localized heating and short timescale high temperature processing, which can be advantageous to reduce metal line resistance by enlarging metal grains in lines or in thin films, while maintaining the integrity and performance of surrounding structures. In this work UV NLA is applied on a typical Cu thin film, demonstrating a mean grain size of over 1 μm and 400 nm in a melt and sub-melt regime, respectively. Along with such grain enlargement, film resistivity is also reduced.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"52 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89557173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537545
D. Tierno, M. Hosseini, M. H. van der Veen, A. Dangol, K. Croes, S. Demuynck, Z. Tokei, E. Litta, N. Horiguchi
We evaluate the reliability of barrierless Mo metallization on various dielectrics that are used in both BEOL and MOL integration schemes. In particular, we assess the risk of metal drift-induced failure in SiO2, LK3.0, SiCO and Si3N4 films by performing TDDB measurements on MIM planar capacitors. We show that Mo does not drift in SiO2, LK3.0, and SiCO. Despite a thoroughly failure analysis no definitive conclusion could be reached for the Si3N4 films.
{"title":"Reliability of Barrierless PVD Mo","authors":"D. Tierno, M. Hosseini, M. H. van der Veen, A. Dangol, K. Croes, S. Demuynck, Z. Tokei, E. Litta, N. Horiguchi","doi":"10.1109/IITC51362.2021.9537545","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537545","url":null,"abstract":"We evaluate the reliability of barrierless Mo metallization on various dielectrics that are used in both BEOL and MOL integration schemes. In particular, we assess the risk of metal drift-induced failure in SiO<inf>2</inf>, LK3.0, SiCO and Si<inf>3</inf>N<inf>4</inf> films by performing TDDB measurements on MIM planar capacitors. We show that Mo does not drift in SiO<inf>2</inf>, LK3.0, and SiCO. Despite a thoroughly failure analysis no definitive conclusion could be reached for the Si<inf>3</inf>N<inf>4</inf> films.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"67 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86019136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537515
Aravindh Kumar, A. Tang, H. Wong, K. Saraswat
Two-dimensional (2D) semiconductors are promising candidates for scaled transistors because they are immune to mobility degradation at the monolayer limit. However, sub-10 nm scaling of 2D semiconductors, such as MoS2, is limited by the contact resistance. In this work, we show for the first time a statistical study of Au contacts to chemical vapor deposited monolayer MoS2 using transmission line model (TLM) structures, before and after dielectric encapsulation. We report contact resistance values as low as 330 ohm-um, which is the lowest value reported to date. We further study the effect of Al2O3 encapsulation on variability in contact resistance and other device metrics. Finally, we note some deviations in the TLM model for short-channel devices in the back-gated configuration and discuss possible modifications to improve the model accuracy.
{"title":"Improved Contacts to Synthetic Monolayer MoS2 – A Statistical Study","authors":"Aravindh Kumar, A. Tang, H. Wong, K. Saraswat","doi":"10.1109/IITC51362.2021.9537515","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537515","url":null,"abstract":"Two-dimensional (2D) semiconductors are promising candidates for scaled transistors because they are immune to mobility degradation at the monolayer limit. However, sub-10 nm scaling of 2D semiconductors, such as MoS2, is limited by the contact resistance. In this work, we show for the first time a statistical study of Au contacts to chemical vapor deposited monolayer MoS2 using transmission line model (TLM) structures, before and after dielectric encapsulation. We report contact resistance values as low as 330 ohm-um, which is the lowest value reported to date. We further study the effect of Al2O3 encapsulation on variability in contact resistance and other device metrics. Finally, we note some deviations in the TLM model for short-channel devices in the back-gated configuration and discuss possible modifications to improve the model accuracy.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"os-48 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87244532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537463
Cheng-Hsuan Kuo, V. Wang, Zichen Zhang, J. Spiegelman, D. Alvarez, A. Kummel, SeongUk Yun, H. Simka
A low temperature (300°C–350°C) TiN thermal ALD process using titanium tetrachloride (TiCl4) and anhydrous hydrazine was developed to yield films with resistivities below 200 μohm-cm. Surface treatments such as Ar plasma and atomic hydrogen were applied to further reduce the surface impurities including all halogens. These experiments indicate that minimizing oxygen concentration using an ultra-clean ALD process with minimum background oxidants and high purity precursors are keys in producing TiN thin films with low resistivity.
{"title":"Low Resistivity Titanium Nitride Thin Film Fabricated by Atomic Layer Deposition on Silicon","authors":"Cheng-Hsuan Kuo, V. Wang, Zichen Zhang, J. Spiegelman, D. Alvarez, A. Kummel, SeongUk Yun, H. Simka","doi":"10.1109/IITC51362.2021.9537463","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537463","url":null,"abstract":"A low temperature (300°C–350°C) TiN thermal ALD process using titanium tetrachloride (TiCl4) and anhydrous hydrazine was developed to yield films with resistivities below 200 μohm-cm. Surface treatments such as Ar plasma and atomic hydrogen were applied to further reduce the surface impurities including all halogens. These experiments indicate that minimizing oxygen concentration using an ultra-clean ALD process with minimum background oxidants and high purity precursors are keys in producing TiN thin films with low resistivity.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"42 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88402380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537517
Sang-heon Lee, Seunggi Seo, Wontae Noh, I. Oh, Hyungjun Kim
We develop the atomic layer deposition (ALD) process of titanium silicate with halide-free precursor and evaluate film properties as a spacer for self-aligned double/quadruple patterning (SADP/SAQP). Growth characteristics are investigated depending on substrate temperature. Growth per cycle (GPC) at 100 °C is largely observed than the estimated value, while that as 200 °C shows an opposite trend. There have been reports on ALD ternary oxides, but different growth characteristics observed in this work have not been fully understood. In this work, the growth behavior of ALD titanium silicate are studied by correlating different characterization results, including infrared spectra, chemical compositions, and X-ray reflection spectra. Correlative results suggest that the surface density of hydroxyl group would be a key role for different growth characteristics of titanium silicates. Also, the feasibility of ALD titanium silicate as a spacer is evaluated, such as etch rates and deposited titanium silicates shows better quality than a conventional SiO2 spacer. This study on ALD titanium silicate should significantly expand multi-patterning applications, especially in a semiconductor field.
{"title":"Atomic Layer Deposition of Titanium Silicate for Multi-Patterning Process","authors":"Sang-heon Lee, Seunggi Seo, Wontae Noh, I. Oh, Hyungjun Kim","doi":"10.1109/IITC51362.2021.9537517","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537517","url":null,"abstract":"We develop the atomic layer deposition (ALD) process of titanium silicate with halide-free precursor and evaluate film properties as a spacer for self-aligned double/quadruple patterning (SADP/SAQP). Growth characteristics are investigated depending on substrate temperature. Growth per cycle (GPC) at 100 °C is largely observed than the estimated value, while that as 200 °C shows an opposite trend. There have been reports on ALD ternary oxides, but different growth characteristics observed in this work have not been fully understood. In this work, the growth behavior of ALD titanium silicate are studied by correlating different characterization results, including infrared spectra, chemical compositions, and X-ray reflection spectra. Correlative results suggest that the surface density of hydroxyl group would be a key role for different growth characteristics of titanium silicates. Also, the feasibility of ALD titanium silicate as a spacer is evaluated, such as etch rates and deposited titanium silicates shows better quality than a conventional SiO2 spacer. This study on ALD titanium silicate should significantly expand multi-patterning applications, especially in a semiconductor field.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"118 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84933805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537483
M. Kobrinsky
Rapidly evolving requirements for on-die interconnects resulting from scaling and performance needs of current and future products is bringing about an exciting acceleration of the rate of innovations. In this paper, we will link evolutionary technology node needs and disruptive trends to interconnect requirements and to the key technologies needed to address future challenges, which include the introduction of new materials, as well as new geometries and structures.
{"title":"On-die Interconnect Innovations for Future Technology Nodes","authors":"M. Kobrinsky","doi":"10.1109/IITC51362.2021.9537483","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537483","url":null,"abstract":"Rapidly evolving requirements for on-die interconnects resulting from scaling and performance needs of current and future products is bringing about an exciting acceleration of the rate of innovations. In this paper, we will link evolutionary technology node needs and disruptive trends to interconnect requirements and to the key technologies needed to address future challenges, which include the introduction of new materials, as well as new geometries and structures.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"138 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74101811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537337
V. Mootheri, A. Minj, G. Arutchelvan, A. Leonhardt, I. Asselberghs, M. Heyns, I. Radu, D. Lin
Graphene based 2D electrical contacts have been proposed to mitigate the contact resistance bottleneck in 2D material based transistors. In this work, we present a detailed analysis of Ru-graphene and Ni-graphene contacts to 2.1nm thick CVD MoS2, which show a contact resistance of 9.34 kΩ – μm and 17.1 kΩ – μm, respectively. We report a novel physical characterization strategy to characterize the MoS2-contact interface by inverting the MoS2 devices, exposing the contact interface. Using Raman spectroscopy and X-ray photoelectron spectroscopy, we characterize the contact interface to correlate the observed electrical trend with physical characterization of the contact interface.
{"title":"Contact Interface Characterization of Graphene contacted MoS2 FETs","authors":"V. Mootheri, A. Minj, G. Arutchelvan, A. Leonhardt, I. Asselberghs, M. Heyns, I. Radu, D. Lin","doi":"10.1109/IITC51362.2021.9537337","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537337","url":null,"abstract":"Graphene based 2D electrical contacts have been proposed to mitigate the contact resistance bottleneck in 2D material based transistors. In this work, we present a detailed analysis of Ru-graphene and Ni-graphene contacts to 2.1nm thick CVD MoS2, which show a contact resistance of 9.34 kΩ – μm and 17.1 kΩ – μm, respectively. We report a novel physical characterization strategy to characterize the MoS2-contact interface by inverting the MoS2 devices, exposing the contact interface. Using Raman spectroscopy and X-ray photoelectron spectroscopy, we characterize the contact interface to correlate the observed electrical trend with physical characterization of the contact interface.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"7 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72736105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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