Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537371
Jungil Park, Jeonghoon Ahn, Y. Yoon, Yunki Choi, Junki Jang, Miji Lee
This paper describes an advanced 5nm node back-end-of-line (BEOL) process integration based on an extreme ultraviolet (EUV) lithography process, atomic layer deposition (ALD) barrier metal (BM) and Cu reflow process. The ALD BM technology was integrated into Low-k in the damascene metallization. This advanced BEOL integration showed a good RC (resistance-capacitance) performance within +3% and an excellent 46% reduction in the via resistance compared to the physical vapor deposition (PVD) BM, and satisfied the reliability requirement for the time-dependent dielectric breakdown (TDDB) and the electro-migration (EM). Finally, ALD BM and Cu reflow process were developed for the advanced 5nm node BEOL integration, and the new process is implemented in order to achieve low via resistance and better device performance.
{"title":"Advanced 5nm BEOL integration development for manufacuring","authors":"Jungil Park, Jeonghoon Ahn, Y. Yoon, Yunki Choi, Junki Jang, Miji Lee","doi":"10.1109/IITC51362.2021.9537371","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537371","url":null,"abstract":"This paper describes an advanced 5nm node back-end-of-line (BEOL) process integration based on an extreme ultraviolet (EUV) lithography process, atomic layer deposition (ALD) barrier metal (BM) and Cu reflow process. The ALD BM technology was integrated into Low-k in the damascene metallization. This advanced BEOL integration showed a good RC (resistance-capacitance) performance within +3% and an excellent 46% reduction in the via resistance compared to the physical vapor deposition (PVD) BM, and satisfied the reliability requirement for the time-dependent dielectric breakdown (TDDB) and the electro-migration (EM). Finally, ALD BM and Cu reflow process were developed for the advanced 5nm node BEOL integration, and the new process is implemented in order to achieve low via resistance and better device performance.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"8 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74628503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537484
B. Peethala, D. Sil, B. Briggs, D. Rath, N. Lanzillo, K. Matam, H. Shobha, K. Choi, T. Spooner, D. Canaperi, B. Haran, M. Packiam, D. Janes, J. Casey, L. Chang, K. Ryan
The Fully aligned via scheme (FAV) is known to mitigate the via misalignment issues that drive a lower Vmax and limits the contact area between the via and the underlying line. Even though the overall benefits of FAV are well known, the key detractors and their contributions are not well understood. One of the key challenges in FAV integration is the need to create of topography which can be either achieved by recessing the metal lines or by selective insulator deposition. Wet recess process has been promising for enabling downstream integration learning of conformal cap deposition, ultra low-k gap-fill, and via landing on recessed area. In this paper wet recess challenges for topography creation and key process improvements that improve the resistance distribution are discussed.
{"title":"Metal Wet Recess Challenges and Solutions for beyond 7nm Fully Aligned Via Integration","authors":"B. Peethala, D. Sil, B. Briggs, D. Rath, N. Lanzillo, K. Matam, H. Shobha, K. Choi, T. Spooner, D. Canaperi, B. Haran, M. Packiam, D. Janes, J. Casey, L. Chang, K. Ryan","doi":"10.1109/IITC51362.2021.9537484","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537484","url":null,"abstract":"The Fully aligned via scheme (FAV) is known to mitigate the via misalignment issues that drive a lower Vmax and limits the contact area between the via and the underlying line. Even though the overall benefits of FAV are well known, the key detractors and their contributions are not well understood. One of the key challenges in FAV integration is the need to create of topography which can be either achieved by recessing the metal lines or by selective insulator deposition. Wet recess process has been promising for enabling downstream integration learning of conformal cap deposition, ultra low-k gap-fill, and via landing on recessed area. In this paper wet recess challenges for topography creation and key process improvements that improve the resistance distribution are discussed.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"110 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76303033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537558
M. Lofrano, O. Pedreira, I. Ciofi, H. Oprins, Seongho Park, Z. Tokei
In this paper, we present a modeling study to investigate the self-heating effect on advanced metallization schemes with airgaps using an experimentally calibrated finite element model. We compared N3 technology node with N2 integrated with airgaps. Despite the higher metal density of the fully dense Ru lines (50%) at the lower metal levels in the N2 structure with airgaps, the N2 stack is more susceptible to self-heating than the N3 structure with 25% line density, showing that the IMD has an important impact on the interconnect self-heating. We quantified the effect of the line density and IMD on the interconnect temperature increase. We found that decreasing the line density from 50% to 15% increases the temperature with 40% in the interconnect structure. A reduction of the low-k thermal conductivity values below 1 W/m-K shows to accelerate the temperature increase in the BEOL.
{"title":"Joule heating investigation for advanced interconnect schemes with airgaps","authors":"M. Lofrano, O. Pedreira, I. Ciofi, H. Oprins, Seongho Park, Z. Tokei","doi":"10.1109/IITC51362.2021.9537558","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537558","url":null,"abstract":"In this paper, we present a modeling study to investigate the self-heating effect on advanced metallization schemes with airgaps using an experimentally calibrated finite element model. We compared N3 technology node with N2 integrated with airgaps. Despite the higher metal density of the fully dense Ru lines (50%) at the lower metal levels in the N2 structure with airgaps, the N2 stack is more susceptible to self-heating than the N3 structure with 25% line density, showing that the IMD has an important impact on the interconnect self-heating. We quantified the effect of the line density and IMD on the interconnect temperature increase. We found that decreasing the line density from 50% to 15% increases the temperature with 40% in the interconnect structure. A reduction of the low-k thermal conductivity values below 1 W/m-K shows to accelerate the temperature increase in the BEOL.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"4 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76990345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537363
Tomohiro Shimizu, S. Shingubara, K. Matsui, Y. Torinari, Shigeru Watariguchi, H. Watanabe, M. Motoyoshi
We developed TSV fabrication process using the anisotropic wet etching of Si assisted by noble metal catalyst and electroless plating of CoWB barrier and Cu seed layers. These methods are essentially low cost as compared to conventional dry etching and CVD methods which use high vacuum chamber systems. Controllability of anisotropic Si etching is improved with the use of catalytic Au disk with nanopores and adequate choice of a mixing ratio of HF and H2O2 in etching solutions. Conformal deposition of CoWB barrier film is possible even for a high aspect ratio TSV with choice of adequate temperature. We have developed equipment of 8 inch processes for both Si etching and electroless plating.
{"title":"Low cost TSV fabrication technologies using anisotropic Si wet etching and conformal electroless plating of barrier and seed metals","authors":"Tomohiro Shimizu, S. Shingubara, K. Matsui, Y. Torinari, Shigeru Watariguchi, H. Watanabe, M. Motoyoshi","doi":"10.1109/IITC51362.2021.9537363","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537363","url":null,"abstract":"We developed TSV fabrication process using the anisotropic wet etching of Si assisted by noble metal catalyst and electroless plating of CoWB barrier and Cu seed layers. These methods are essentially low cost as compared to conventional dry etching and CVD methods which use high vacuum chamber systems. Controllability of anisotropic Si etching is improved with the use of catalytic Au disk with nanopores and adequate choice of a mixing ratio of HF and H2O2 in etching solutions. Conformal deposition of CoWB barrier film is possible even for a high aspect ratio TSV with choice of adequate temperature. We have developed equipment of 8 inch processes for both Si etching and electroless plating.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90947265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537346
D. Lehninger, M. Lederer, T. Ali, T. Kämpfe, K. Mertens, K. Seidel
Advanced non-volatile memory concepts such as the 1T1C ferroelectric (FE) random-access memory (FeRAM) and the 1T1C FE field-effect transistor (FeFET) can be realized by connecting a metal-ferroelectric-metal (MFM) capacitor placed in the back end of line (BEoL) of a microchip to the drain and gate contacts of a standard logic device, respectively. With the vertical distributed select devices in the front-end of line (FEoL) and the storage elements in the BEoL, both concepts increase the effective memory density of a microchip without introducing major changes in the FEoL fabrication technology. However, for advanced neuromorphic computing architectures, the 1T1C FeFET is the device of choice, since it provides non-destructive readout. The most promising material for the integration of FE non-volatile memory functionalities into the BEoL is Zr doped HfO2 (HZO). It crystallizes at low temperatures in the orthorhombic phase (the one with FE properties) and with a polycrystalline structure. The latter is important to enable analogue like switching in synaptic devices. Herein, the above-mentioned memory concepts are introduced and key steps to optimize the HZO films for the BEoL integration and for the neuromorphic computing use case are described.
{"title":"Enabling Ferroelectric Memories in BEoL - towards advanced neuromorphic computing architectures","authors":"D. Lehninger, M. Lederer, T. Ali, T. Kämpfe, K. Mertens, K. Seidel","doi":"10.1109/IITC51362.2021.9537346","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537346","url":null,"abstract":"Advanced non-volatile memory concepts such as the 1T1C ferroelectric (FE) random-access memory (FeRAM) and the 1T1C FE field-effect transistor (FeFET) can be realized by connecting a metal-ferroelectric-metal (MFM) capacitor placed in the back end of line (BEoL) of a microchip to the drain and gate contacts of a standard logic device, respectively. With the vertical distributed select devices in the front-end of line (FEoL) and the storage elements in the BEoL, both concepts increase the effective memory density of a microchip without introducing major changes in the FEoL fabrication technology. However, for advanced neuromorphic computing architectures, the 1T1C FeFET is the device of choice, since it provides non-destructive readout. The most promising material for the integration of FE non-volatile memory functionalities into the BEoL is Zr doped HfO2 (HZO). It crystallizes at low temperatures in the orthorhombic phase (the one with FE properties) and with a polycrystalline structure. The latter is important to enable analogue like switching in synaptic devices. Herein, the above-mentioned memory concepts are introduced and key steps to optimize the HZO films for the BEoL integration and for the neuromorphic computing use case are described.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"70 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77894295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537421
Min-Hsuan Hsu, Chih-Chen Lin, Hsiang-Meng Yu, Kuang-Wei Chen, T. Luoh, Ling-Wu Yang, Tahone Yang, K. Chen
Chemical-mechanical polishing closed loop control optimized process with machine learning assisted wafer image analysis algorithm implemented on the inter layer dielectric of 3D NAND ON stacking with poly-silicon stop layer is studied. The grayscale wafer image can be responded for film residue, stop layer damage, wafer edge damage, and thickness variation. Polishing five zones control model is trainned with wafer grayscale value by Python NN model with two hidden layers. The best condition of closed loop feedback control is deduced by machine learning assisted wafer image analysis algorithm.
{"title":"Advanced CMP Process Control by Using Machine Learning Image Analysis","authors":"Min-Hsuan Hsu, Chih-Chen Lin, Hsiang-Meng Yu, Kuang-Wei Chen, T. Luoh, Ling-Wu Yang, Tahone Yang, K. Chen","doi":"10.1109/IITC51362.2021.9537421","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537421","url":null,"abstract":"Chemical-mechanical polishing closed loop control optimized process with machine learning assisted wafer image analysis algorithm implemented on the inter layer dielectric of 3D NAND ON stacking with poly-silicon stop layer is studied. The grayscale wafer image can be responded for film residue, stop layer damage, wafer edge damage, and thickness variation. Polishing five zones control model is trainned with wafer grayscale value by Python NN model with two hidden layers. The best condition of closed loop feedback control is deduced by machine learning assisted wafer image analysis algorithm.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"22 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74128155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537349
E. Ketsombun, T. Akimoto, K. Ueno
Doped MLG is expected as an inductor material with high inductance density due to its high kinetic inductance. A practical fabrication process for doped MLG patterns is developed using a selective CVD on Ni catalyst patterns and stable MoCl5 intercalation. The highly doped MLG patterns of stage-2 were realized by CVD-MLG with a G/D ratio of 20 or more, and the sheet-resistance could be reduced.
{"title":"Fabrication of Highly Doped MLG Patterns Using Selective CVD and MoCl5 Intercalation","authors":"E. Ketsombun, T. Akimoto, K. Ueno","doi":"10.1109/IITC51362.2021.9537349","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537349","url":null,"abstract":"Doped MLG is expected as an inductor material with high inductance density due to its high kinetic inductance. A practical fabrication process for doped MLG patterns is developed using a selective CVD on Ni catalyst patterns and stable MoCl5 intercalation. The highly doped MLG patterns of stage-2 were realized by CVD-MLG with a G/D ratio of 20 or more, and the sheet-resistance could be reduced.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"86 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81028434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537552
K. Park, H. Simka
As the on-chip interconnect scales down to below 30nm pitch, it faces challenges in all aspects of performance, yield, and cost. Performance degradation caused by electron scattering in narrow Cu damascene lines, combined with slow barrier/liner scaling is a big concern. In order to reduce the resistivity of damascene Cu lines, grain size and interface engineering are being investigated, as well as a new liner that can enable more aggressive thickness scaling. To improve capacitance, k-value reduction of dielectric films by damage recovery during process integration is being studied. Yield loss is mainly attributed to micro bridge, also known as stochastic printing failures of EUV lithography, or scaling induced Cu void or bridge defects. New photoresists or etch process recipes are being explored in order to address the micro bridge. Cu-fill friendly damascene profile is being introduced to suppress Cu void defects. Since rising BEOL cost is a critical challenge, single EUV patterning to replace double patterning is being actively investigated. In parallel to the conventional scaling, disruptive interconnect architectural changes such as backside power distribution network, and innovative materials such as alternative conductors, and 2D barriers / liners need to be considered.
{"title":"Advanced interconnect challenges beyond 5nm and possible solutions","authors":"K. Park, H. Simka","doi":"10.1109/IITC51362.2021.9537552","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537552","url":null,"abstract":"As the on-chip interconnect scales down to below 30nm pitch, it faces challenges in all aspects of performance, yield, and cost. Performance degradation caused by electron scattering in narrow Cu damascene lines, combined with slow barrier/liner scaling is a big concern. In order to reduce the resistivity of damascene Cu lines, grain size and interface engineering are being investigated, as well as a new liner that can enable more aggressive thickness scaling. To improve capacitance, k-value reduction of dielectric films by damage recovery during process integration is being studied. Yield loss is mainly attributed to micro bridge, also known as stochastic printing failures of EUV lithography, or scaling induced Cu void or bridge defects. New photoresists or etch process recipes are being explored in order to address the micro bridge. Cu-fill friendly damascene profile is being introduced to suppress Cu void defects. Since rising BEOL cost is a critical challenge, single EUV patterning to replace double patterning is being actively investigated. In parallel to the conventional scaling, disruptive interconnect architectural changes such as backside power distribution network, and innovative materials such as alternative conductors, and 2D barriers / liners need to be considered.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"23 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88186920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537549
H. Warashina, H. Kawasaki, H. Nagai, T. Yamaguchi, N. Sato, Y. Kikuchi, X. Sun
As a solution for RC delay of BEOL interconnect, we developed a novel air gap formation scheme. This scheme uses a volatile material (VM) and allows us to omit one lithography step, which was required for conventional air gap formation. It is possible to apply this scheme to subtractive interconnect scheme too. In this study, we will introduce the basic characteristics of VM and demonstrate the novel air gap integration through e-tests.
{"title":"Advanced Air Gap Formation Scheme Using Volatile Material","authors":"H. Warashina, H. Kawasaki, H. Nagai, T. Yamaguchi, N. Sato, Y. Kikuchi, X. Sun","doi":"10.1109/IITC51362.2021.9537549","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537549","url":null,"abstract":"As a solution for RC delay of BEOL interconnect, we developed a novel air gap formation scheme. This scheme uses a volatile material (VM) and allows us to omit one lithography step, which was required for conventional air gap formation. It is possible to apply this scheme to subtractive interconnect scheme too. In this study, we will introduce the basic characteristics of VM and demonstrate the novel air gap integration through e-tests.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90915578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-07-06DOI: 10.1109/IITC51362.2021.9537528
T. Kuge, M. Yahagi, J. Koike
In this paper, we report the property and reliability of CuAl2 and its effects of compositional shift within ±5%. Resistivity was found to be 7–8 μΩ· cm after annealing at 400 °C, even with compositional shift. Capacitance–Voltage (C–V) after Bias Thermal Stress (BTS) test showed no shift of flat–band voltage under the condition of 3.0 MV/cm × 30 min at 250 °C. Time–Dependent–Dielectric–Breakdown (TDDB) evaluation showed that the reliability is better than that of conventional Cu/TaN interconnects.
{"title":"Effects of composition deviation of CuAl2 on BTS and TDDB reliability","authors":"T. Kuge, M. Yahagi, J. Koike","doi":"10.1109/IITC51362.2021.9537528","DOIUrl":"https://doi.org/10.1109/IITC51362.2021.9537528","url":null,"abstract":"In this paper, we report the property and reliability of CuAl2 and its effects of compositional shift within ±5%. Resistivity was found to be 7–8 μΩ· cm after annealing at 400 °C, even with compositional shift. Capacitance–Voltage (C–V) after Bias Thermal Stress (BTS) test showed no shift of flat–band voltage under the condition of 3.0 MV/cm × 30 min at 250 °C. Time–Dependent–Dielectric–Breakdown (TDDB) evaluation showed that the reliability is better than that of conventional Cu/TaN interconnects.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"24 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82689750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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