Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919757
Li Li, Xuan Liu, Shyam Pal
The rapid development in dense integrated circuits requires significant advancement in small scaling patterning technology. EUV technology is considered as a powerful solution for the sub-7 nm node pattering and beyond. The high performance resist development is required for the practical applications of the EUV patterning for high volume manufacturing. In the current work, the requirements for the development of next generation resist materials is reviewed and summarized to propose the design criterion for high performance photoresist materials.
{"title":"Advancement in resist materials for sub-7 nm patterning and beyond","authors":"Li Li, Xuan Liu, Shyam Pal","doi":"10.1109/CSTIC.2017.7919757","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919757","url":null,"abstract":"The rapid development in dense integrated circuits requires significant advancement in small scaling patterning technology. EUV technology is considered as a powerful solution for the sub-7 nm node pattering and beyond. The high performance resist development is required for the practical applications of the EUV patterning for high volume manufacturing. In the current work, the requirements for the development of next generation resist materials is reviewed and summarized to propose the design criterion for high performance photoresist materials.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"46 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81267261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919881
T. Chiang, K. Littau, Stephen L Weeks, A. Pal, V. Narasimhan, G. Nowling, M. Bowes, S. Barabash, D. Pramanik
Materials are playing an increasingly important role to enable novel device applications beyond dimensional scaling. We describe areas of ferroelectric materials, high Eg dielectrics, chalcogenides, and oxide semiconductors. These materials find potential use in advanced memory, select element and transistor applications. In each area, a material screening workflow methodology is used to garner physical as well as electrical properties. DFT modeling of basic materials properties is used to complement experimental results.
{"title":"Materials screening workflow methodologies for metal oxides and chalcogenides for use in novel devices","authors":"T. Chiang, K. Littau, Stephen L Weeks, A. Pal, V. Narasimhan, G. Nowling, M. Bowes, S. Barabash, D. Pramanik","doi":"10.1109/CSTIC.2017.7919881","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919881","url":null,"abstract":"Materials are playing an increasingly important role to enable novel device applications beyond dimensional scaling. We describe areas of ferroelectric materials, high Eg dielectrics, chalcogenides, and oxide semiconductors. These materials find potential use in advanced memory, select element and transistor applications. In each area, a material screening workflow methodology is used to garner physical as well as electrical properties. DFT modeling of basic materials properties is used to complement experimental results.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"11 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87211838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919852
G. Niu, W. Chien, Jack Chen, Dennis Zhang, Susie Yu, Daniel Zhao, Silvia Duan, Ming Li, Alicia Ding
Package Level Threshold Voltage Stability (VTS) evaluation on PMOS has emerged as one of the critical reliability concerns in deep sub-micron devices. In this paper, we present a novel method to fast measure VTS at wafer level. Our result shows that changing the Source/Drain IMP species can improve the VTS of a 0.13um Flash.
{"title":"Practical wafer Level Threshold Voltage Stability measurement methodology for the fast evaluation of Flash technology","authors":"G. Niu, W. Chien, Jack Chen, Dennis Zhang, Susie Yu, Daniel Zhao, Silvia Duan, Ming Li, Alicia Ding","doi":"10.1109/CSTIC.2017.7919852","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919852","url":null,"abstract":"Package Level Threshold Voltage Stability (VTS) evaluation on PMOS has emerged as one of the critical reliability concerns in deep sub-micron devices. In this paper, we present a novel method to fast measure VTS at wafer level. Our result shows that changing the Source/Drain IMP species can improve the VTS of a 0.13um Flash.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"42 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91363324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919865
M. Yao, Daquan Yu, N. Zhao, Jun Fan, Zhiyi Xiao, Haitao Ma
Development of low temperature wafer level hybrid bonding process using Cu/SnAg bump and photosensitive adhesive was reported. Two kinds of photosensitive adhesives, i.e., polyimide and dry film, were selected for adhesive bonding. The proposed hybrid bonding method has been successfully applied to 8 inch wafer to wafer bonding. Hybrid bonding using both polyimide and dry film achieved seam-free bonding interface. However, the wafer bonding quality using polyimide is poor and dies were separated during dicing process. As comparison, dry film is more suitable to integrate with Cu/SnAg bump for hybrid bonding and the bonded chip has robust bonding strength.
{"title":"Development of wafer level hybrid bonding process using photosensitive adhesive and Cu pillar bump","authors":"M. Yao, Daquan Yu, N. Zhao, Jun Fan, Zhiyi Xiao, Haitao Ma","doi":"10.1109/CSTIC.2017.7919865","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919865","url":null,"abstract":"Development of low temperature wafer level hybrid bonding process using Cu/SnAg bump and photosensitive adhesive was reported. Two kinds of photosensitive adhesives, i.e., polyimide and dry film, were selected for adhesive bonding. The proposed hybrid bonding method has been successfully applied to 8 inch wafer to wafer bonding. Hybrid bonding using both polyimide and dry film achieved seam-free bonding interface. However, the wafer bonding quality using polyimide is poor and dies were separated during dicing process. As comparison, dry film is more suitable to integrate with Cu/SnAg bump for hybrid bonding and the bonded chip has robust bonding strength.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"71 ","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91465333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919803
W. Lau
In this paper, the Smoluchoski effect will be explained and is further used to understand the physics of the current-voltage (I–V) characteristics of high-k MIM capacitors in mixed-signal CMOS technology application.
{"title":"The application of the Smoluchowski effect to explain the current-voltage characteristics of high-k MIM capacitors","authors":"W. Lau","doi":"10.1109/CSTIC.2017.7919803","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919803","url":null,"abstract":"In this paper, the Smoluchoski effect will be explained and is further used to understand the physics of the current-voltage (I–V) characteristics of high-k MIM capacitors in mixed-signal CMOS technology application.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"32 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88487429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919735
Lu Sun
The concentrated sulfuric acid is a necessary chemical for IC-Industry, especially in the wet process. The electronic grade concentrated sulfuric acid offered by major suppliers satisfies the requirements of the new technologies in metal ion impurities and insoluble particulate matters, but during the use of that offered by a core supplier in wet process, a new kind of particle contamination appeared. In this paper, the particulate pollution matter has been confirmed as carbide formed from Siloxane, which was produced at high temperature and strong acidic conditions. In order to control the generation of this new particulate pollutant, TOC (Total Organic Carbon) and Silicon content (Sc) were measured in electronic grade concentrated sulfuric acid, and used to establish the relevant mathematical model for calculating the Sr (Siloxane Relative Value) in electronic grade concentrated sulfuric acid, which was first proposed as a new quality demand for the concentrated sulfuric acid.
{"title":"Identification and solutions for a novel particulate pollution matter in wafer surface caused by concentrated sulfuric acid","authors":"Lu Sun","doi":"10.1109/CSTIC.2017.7919735","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919735","url":null,"abstract":"The concentrated sulfuric acid is a necessary chemical for IC-Industry, especially in the wet process. The electronic grade concentrated sulfuric acid offered by major suppliers satisfies the requirements of the new technologies in metal ion impurities and insoluble particulate matters, but during the use of that offered by a core supplier in wet process, a new kind of particle contamination appeared. In this paper, the particulate pollution matter has been confirmed as carbide formed from Siloxane, which was produced at high temperature and strong acidic conditions. In order to control the generation of this new particulate pollutant, TOC (Total Organic Carbon) and Silicon content (Sc) were measured in electronic grade concentrated sulfuric acid, and used to establish the relevant mathematical model for calculating the Sr (Siloxane Relative Value) in electronic grade concentrated sulfuric acid, which was first proposed as a new quality demand for the concentrated sulfuric acid.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"38 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90805299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919903
Chun-Chen Liu, Yilei Li, Yuan Du, L. Du, Tianchen Wang
In this paper we propose an innovative 3D IC architecture that combines reconfigurable 2D structure with monolithic 3D. This new architecture not only resolves Power Distributive Network (PDN) design and thermal management issues of traditional 3D-IC, but also provides additional power control and programmable routing capability. It provides a cost effective way to integrate different modules together using stacked interposer structure. With power rails and signal paths that can be routed dynamically using reconfigurable peripheral switches, the new system is adjustable. Moreover, area saving is achieved by using monolithic 3D to realize the modules. With the corresponding new thermal aware hierarchical simulated annealing floorplan algorithm designed for our hybrid reconfigurable architecture, the thermal problem can be further alleviated. Our testing results on 15 benchmarks show that we obtain an average 1.69× lower temperature and average 2.82× smaller power compared with traditional 2D SoC structure, 1.3× lower temperature compared to traditional 3D structure.
{"title":"Hybrid thermal aware reconfigurable 3D IC with dynamic power gating architecture","authors":"Chun-Chen Liu, Yilei Li, Yuan Du, L. Du, Tianchen Wang","doi":"10.1109/CSTIC.2017.7919903","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919903","url":null,"abstract":"In this paper we propose an innovative 3D IC architecture that combines reconfigurable 2D structure with monolithic 3D. This new architecture not only resolves Power Distributive Network (PDN) design and thermal management issues of traditional 3D-IC, but also provides additional power control and programmable routing capability. It provides a cost effective way to integrate different modules together using stacked interposer structure. With power rails and signal paths that can be routed dynamically using reconfigurable peripheral switches, the new system is adjustable. Moreover, area saving is achieved by using monolithic 3D to realize the modules. With the corresponding new thermal aware hierarchical simulated annealing floorplan algorithm designed for our hybrid reconfigurable architecture, the thermal problem can be further alleviated. Our testing results on 15 benchmarks show that we obtain an average 1.69× lower temperature and average 2.82× smaller power compared with traditional 2D SoC structure, 1.3× lower temperature compared to traditional 3D structure.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"63 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81320146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919835
Chunmei Zou, Y. Zhao, W. Chien, Junyao Tang
Program disturbance is a major intrinsic reliability concern on NAND flash. In this paper, we present that NAND flash E/W (Erase/Write) cycle failures induced by program disturbance for erase cells VT (Threshold Voltage) positive shift. The root cause of program disturbance is the old process of gate re-oxidation issue, which results in ILD (Intra-Layer Dielectric) voids, then Ni fills in the ILD voids and induces the lateral E-field increase between WL's. Interface traps and electrons generated by GIDL (Gate Induce Drain Leakage) are accelerated by the lateral E-field and subsequently injected into the erase cell transistors by HCI effect, therefore erase cells VT positive shift, and program disturbance occurs. The disturbance will get worse than fresh sample as interface traps and couple voltage of WLs increasing after E/W cycles. A new process of gate re-oxidation to depress the program disturbance and enhance NAND Flash E/W cycles performance is provided.
{"title":"Fail mechanism of program disturbance for erase cells VT positive shift in NAND flash technology","authors":"Chunmei Zou, Y. Zhao, W. Chien, Junyao Tang","doi":"10.1109/CSTIC.2017.7919835","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919835","url":null,"abstract":"Program disturbance is a major intrinsic reliability concern on NAND flash. In this paper, we present that NAND flash E/W (Erase/Write) cycle failures induced by program disturbance for erase cells VT (Threshold Voltage) positive shift. The root cause of program disturbance is the old process of gate re-oxidation issue, which results in ILD (Intra-Layer Dielectric) voids, then Ni fills in the ILD voids and induces the lateral E-field increase between WL's. Interface traps and electrons generated by GIDL (Gate Induce Drain Leakage) are accelerated by the lateral E-field and subsequently injected into the erase cell transistors by HCI effect, therefore erase cells VT positive shift, and program disturbance occurs. The disturbance will get worse than fresh sample as interface traps and couple voltage of WLs increasing after E/W cycles. A new process of gate re-oxidation to depress the program disturbance and enhance NAND Flash E/W cycles performance is provided.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"216 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79631806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919850
Hongpeng Han
Programmable Logic Cell (PLC) timing test is one of the most critical items for post-silicon validation of a new Field Programmable Gate Array (FPGA) product because it determines the fundamental performance of the FPGA chip. However, it has been very difficult to accurately measure all aspects of PLC segment timing for several practical reasons. First, some segments exhibit merely 100ps delay which places severe requirements on the resolution of the measurement system. Second, some segments are intrinsic elements in a FPGA and cannot be accessed directly from an external measurement port.
{"title":"Two indirect methodologies for testing FPGA intrinsic Programmable Logic Cell timing performance","authors":"Hongpeng Han","doi":"10.1109/CSTIC.2017.7919850","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919850","url":null,"abstract":"Programmable Logic Cell (PLC) timing test is one of the most critical items for post-silicon validation of a new Field Programmable Gate Array (FPGA) product because it determines the fundamental performance of the FPGA chip. However, it has been very difficult to accurately measure all aspects of PLC segment timing for several practical reasons. First, some segments exhibit merely 100ps delay which places severe requirements on the resolution of the measurement system. Second, some segments are intrinsic elements in a FPGA and cannot be accessed directly from an external measurement port.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"19 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89368827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919785
Erhu Zheng, H. Zhang, Yi-ying Zhang
Incorporation of self-aligned multiple patterning (SaMP) techniques have had limited uses in the industry due to a number of issues including: pitching walking, initial line width roughness (LWR) of photoresist, line edge roughness (LER) degradation of subsequent layer patterning. Utilizing plasma coating for PR hardening is attractive for 193nm lithography application. This paper presents the design of experiments (DOE) to optimize the parameters of pressure, RF power and chemistry ratio to achieve the optimal condition on the LER improvement. As a result, the LER of 1st layer is improved 32% at dense pattern region comparing to initial condition.
{"title":"The line edge roughness improvement with plasma coating for 193nm lithography","authors":"Erhu Zheng, H. Zhang, Yi-ying Zhang","doi":"10.1109/CSTIC.2017.7919785","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919785","url":null,"abstract":"Incorporation of self-aligned multiple patterning (SaMP) techniques have had limited uses in the industry due to a number of issues including: pitching walking, initial line width roughness (LWR) of photoresist, line edge roughness (LER) degradation of subsequent layer patterning. Utilizing plasma coating for PR hardening is attractive for 193nm lithography application. This paper presents the design of experiments (DOE) to optimize the parameters of pressure, RF power and chemistry ratio to achieve the optimal condition on the LER improvement. As a result, the LER of 1st layer is improved 32% at dense pattern region comparing to initial condition.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"11 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72706914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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