Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919872
F. Balon, P. Carazzetti, J. Weichart, Mohamed Elghazzali, M. Hoffmann
Advanced Packaging relies heavily on the use of organic/polymer films and mold wafers such as Fan-Out Wafer-Level-Packages (FOWLP). Processing of such wafers poses challenges, potentially resulting in a high contact resistance (Rc), yield loss, increased maintenance costs and low tool productivity. In this paper we focus on novel approaches how to overcome these challenges. It is shown that the combination of Atmospheric Batch Degas and Cooler Modules in connection with the latest generation of Arctic ICP Sputter Etch results in a throughput of more than 45wafers/hour, Etch Shields Kit Lifetime exceeding 30'000 wafers, low and stable Rc values in RDL/UBM processing.
{"title":"High productivity PVD solution for an ever-evolving advanced packaging industry","authors":"F. Balon, P. Carazzetti, J. Weichart, Mohamed Elghazzali, M. Hoffmann","doi":"10.1109/CSTIC.2017.7919872","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919872","url":null,"abstract":"Advanced Packaging relies heavily on the use of organic/polymer films and mold wafers such as Fan-Out Wafer-Level-Packages (FOWLP). Processing of such wafers poses challenges, potentially resulting in a high contact resistance (Rc), yield loss, increased maintenance costs and low tool productivity. In this paper we focus on novel approaches how to overcome these challenges. It is shown that the combination of Atmospheric Batch Degas and Cooler Modules in connection with the latest generation of Arctic ICP Sputter Etch results in a throughput of more than 45wafers/hour, Etch Shields Kit Lifetime exceeding 30'000 wafers, low and stable Rc values in RDL/UBM processing.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"23 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88363300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919831
X. Ji, S. Kang
This paper presents an approach to solving the problems though the method of design of experiment (DOE). In generally, all problems in semiconductor industry can be summarized as 3 types, called Type X, A and T. The definition is based on whether it's clear for root cause and improvement action of problems. According to the problem types, different solutions are recommended to different problem types for effectively solving the issues. In this paper, we introduced a problem solving strategy to identify the problem types and provided a reasonable solution plan based on DOE method. And one flow is designed in this paper to instruct the problem identification and solution determination. The screening method and optimal design method of DOE are recommended for its wide applications and rigorous statistical theory. Two examples are described to using the flow of real problems solving. The result shows the flow can clearly identify and settle the issues.
{"title":"A study on problem solving strategy using experiment of design","authors":"X. Ji, S. Kang","doi":"10.1109/CSTIC.2017.7919831","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919831","url":null,"abstract":"This paper presents an approach to solving the problems though the method of design of experiment (DOE). In generally, all problems in semiconductor industry can be summarized as 3 types, called Type X, A and T. The definition is based on whether it's clear for root cause and improvement action of problems. According to the problem types, different solutions are recommended to different problem types for effectively solving the issues. In this paper, we introduced a problem solving strategy to identify the problem types and provided a reasonable solution plan based on DOE method. And one flow is designed in this paper to instruct the problem identification and solution determination. The screening method and optimal design method of DOE are recommended for its wide applications and rigorous statistical theory. Two examples are described to using the flow of real problems solving. The result shows the flow can clearly identify and settle the issues.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"23 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73378694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919802
Guiying Ma, Tzuchiang Yu
The use of strained SiGe is essential to improve PFET MOS device performance. However, the structure is susceptible to strain relaxation and wafer deformation during thermal annealing. The accumulation of stress in the wafer needs to be controlled to minimize contact misalignment overlay issue. This paper analyzes laser spike annealing impact and SiGe dummy pattern layout impact on contact overlay by experiments on 28n m technology, design guide lines on shape of dummy SiGe patterns for slip free condition have been investigated and clarified. With optimized dummy SiGe patterns and laser spike annealing, random component of contact misalignment has been successfully reduced to normal level.
{"title":"Laser spike annealing and SiGe dummy pattern layout study to improve contact misalignment overlay issue","authors":"Guiying Ma, Tzuchiang Yu","doi":"10.1109/CSTIC.2017.7919802","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919802","url":null,"abstract":"The use of strained SiGe is essential to improve PFET MOS device performance. However, the structure is susceptible to strain relaxation and wafer deformation during thermal annealing. The accumulation of stress in the wafer needs to be controlled to minimize contact misalignment overlay issue. This paper analyzes laser spike annealing impact and SiGe dummy pattern layout impact on contact overlay by experiments on 28n m technology, design guide lines on shape of dummy SiGe patterns for slip free condition have been investigated and clarified. With optimized dummy SiGe patterns and laser spike annealing, random component of contact misalignment has been successfully reduced to normal level.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"102 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79462973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919740
Hai Liu, River He, Byunghak Lee
As the MOSFET scales down, with keeping increasing of speed (ft), minimum noise figure (NF) is difficult to scale down where increasing gate resistance (Rg) is one of crucial impact factors. In this paper, we present a novel approach to boost MOSFET RF performance by spacer profile optimization. It can help reduce Rg about 12% and increase Fmax about 7% for critical size device (L=27nm) without degrading device DC performance on 28nm Poly/SiON technology platform. This approach does NOT introduce any extra steps into process flow and can be easily combined with those traditional Rg reduction methods.
{"title":"MOSFET RF performance improvement through spacer profile optimization for 28nm Poly/SiON SoC technology","authors":"Hai Liu, River He, Byunghak Lee","doi":"10.1109/CSTIC.2017.7919740","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919740","url":null,"abstract":"As the MOSFET scales down, with keeping increasing of speed (ft), minimum noise figure (NF) is difficult to scale down where increasing gate resistance (Rg) is one of crucial impact factors. In this paper, we present a novel approach to boost MOSFET RF performance by spacer profile optimization. It can help reduce Rg about 12% and increase Fmax about 7% for critical size device (L=27nm) without degrading device DC performance on 28nm Poly/SiON technology platform. This approach does NOT introduce any extra steps into process flow and can be easily combined with those traditional Rg reduction methods.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"9 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79077541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919823
Jin Kang, Hanming Wu, Xing Zhang, Qiang Li, J. Ge, Tong Feng, Ziqing Yin, Yu-ling Liu
This study reports a weakly alkaline slurry (WAS) for copper barrier chemical mechanical planarization (CMP) process in standard 12-inch CMOS manufacture. We do copper barrier CMP process result comparison between current maintream production used slurry (BL) and WAS slurry adopts a unique alkaline macromolecular organic chelating agent with the high activation energy (named FA/O). Based on the same CMP process recipe, WAS shows the better erosion (more than 60% improvement) and dishing (more than 45% improvement) performance than BL. At the same time, WAS keeps the same level performance as BL by inline monitor pad thickness, Rs, and inline defect. All the results show that the WAS has advanced properties and it has potential application for future production line.
{"title":"Study of weakly alkaline slurry for copper barrier CMP on manufacture platform","authors":"Jin Kang, Hanming Wu, Xing Zhang, Qiang Li, J. Ge, Tong Feng, Ziqing Yin, Yu-ling Liu","doi":"10.1109/CSTIC.2017.7919823","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919823","url":null,"abstract":"This study reports a weakly alkaline slurry (WAS) for copper barrier chemical mechanical planarization (CMP) process in standard 12-inch CMOS manufacture. We do copper barrier CMP process result comparison between current maintream production used slurry (BL) and WAS slurry adopts a unique alkaline macromolecular organic chelating agent with the high activation energy (named FA/O). Based on the same CMP process recipe, WAS shows the better erosion (more than 60% improvement) and dishing (more than 45% improvement) performance than BL. At the same time, WAS keeps the same level performance as BL by inline monitor pad thickness, Rs, and inline defect. All the results show that the WAS has advanced properties and it has potential application for future production line.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"191 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75685254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919808
Yu Bao, Gang Shi, Lin Gao, Yanyan Zhang, Yingming Liu, P. Tian, Fuchun Xi, Wei Hu, Ying Gao, Zhenhua Cai, Baojun Zhao, Zhigang Yang, J. Leng, Haifeng Zhou, J. Fang
In this paper, the influence of Copper (Cu) barrier and seed process tuning on step coverage was analyzed. TEM images show relatively thinner barrier can improve the opening CD of a metal line structure hence improve the sidewall coverage of Cu seed. Cu Seed adopts the deposition/re-sputter method to improve the step coverage, and a higher ratio of re-sputter/deposition can increase the thickness of Cu seed on the sidewall. According to the post CMP surface defects scan results, the optimization of barrier Cu seed thickness can significantly reduce the copper void defects density.
{"title":"The study of 28nm BEOL Cu gap-fill process","authors":"Yu Bao, Gang Shi, Lin Gao, Yanyan Zhang, Yingming Liu, P. Tian, Fuchun Xi, Wei Hu, Ying Gao, Zhenhua Cai, Baojun Zhao, Zhigang Yang, J. Leng, Haifeng Zhou, J. Fang","doi":"10.1109/CSTIC.2017.7919808","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919808","url":null,"abstract":"In this paper, the influence of Copper (Cu) barrier and seed process tuning on step coverage was analyzed. TEM images show relatively thinner barrier can improve the opening CD of a metal line structure hence improve the sidewall coverage of Cu seed. Cu Seed adopts the deposition/re-sputter method to improve the step coverage, and a higher ratio of re-sputter/deposition can increase the thickness of Cu seed on the sidewall. According to the post CMP surface defects scan results, the optimization of barrier Cu seed thickness can significantly reduce the copper void defects density.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"2 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78929246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919830
Jia Liu, Yusen Qin, T. Li, Yuxin Wang, Weidong Yang, Jun Liu, Ruzhang Li
In the sub-100nm bulk CMOS process technologies, the Single Event Effect (SEE) becomes one of the most critical reliability issues in the semiconductor devices and ICs that are used for the space applications. The modeling of Single Event (SE) current pulse is very important and challenging. In this paper we give the 3D TCAD simulation results of the SE current pulse (SECP) in the devices, and develop a compact model using VerilogA (VA) behavioral language. This model could be used for the validation of the Radiation-Hardened (RH) approaches in the circuit-level simulations.
{"title":"Using VerilogA for modeling of Single Event current pulse: Implementation and application","authors":"Jia Liu, Yusen Qin, T. Li, Yuxin Wang, Weidong Yang, Jun Liu, Ruzhang Li","doi":"10.1109/CSTIC.2017.7919830","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919830","url":null,"abstract":"In the sub-100nm bulk CMOS process technologies, the Single Event Effect (SEE) becomes one of the most critical reliability issues in the semiconductor devices and ICs that are used for the space applications. The modeling of Single Event (SE) current pulse is very important and challenging. In this paper we give the 3D TCAD simulation results of the SE current pulse (SECP) in the devices, and develop a compact model using VerilogA (VA) behavioral language. This model could be used for the validation of the Radiation-Hardened (RH) approaches in the circuit-level simulations.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"115 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79023602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919822
Yanghua He, Michael Lube, J. Leighton
This paper describes the improvement obtained when using an Applied Materials Mirra CMP system equipped with 150mm Titan Profiler or 200mm Titan Contour wafer-carrier heads, versus a polisher with a basic carrier. The wafer-edge profiles and polish-rate stability were compared between the polishers using different wafer-carrier heads. The polisher usage/capacity and CMP cycle time in production were also compared. Results show that the process stability with 150mm Profiler and 200mm Contour wafer-carrier heads makes daily process qualification unnecessary, and enables the elimination of the time-consuming look-ahead (L/A) step for each product lot. As a result, the polisher usage and CMP capacity was greatly improved to meet the requirement of high volume Bulk Acoustic Wave (BAW) production.
{"title":"Process stability and tool capacity improvement with 150mm Profiler and 200mm contour heads","authors":"Yanghua He, Michael Lube, J. Leighton","doi":"10.1109/CSTIC.2017.7919822","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919822","url":null,"abstract":"This paper describes the improvement obtained when using an Applied Materials Mirra CMP system equipped with 150mm Titan Profiler or 200mm Titan Contour wafer-carrier heads, versus a polisher with a basic carrier. The wafer-edge profiles and polish-rate stability were compared between the polishers using different wafer-carrier heads. The polisher usage/capacity and CMP cycle time in production were also compared. Results show that the process stability with 150mm Profiler and 200mm Contour wafer-carrier heads makes daily process qualification unnecessary, and enables the elimination of the time-consuming look-ahead (L/A) step for each product lot. As a result, the polisher usage and CMP capacity was greatly improved to meet the requirement of high volume Bulk Acoustic Wave (BAW) production.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"14 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75400338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919826
Haigou Huang, T. Chao, Ja-Hyung Han, D. Koli, Q. Fang
In this study, new SiOC Chemical Mechanical Planarization (CMP) process is fully developed with the characterization of the blanket wafer selectivity, SiN loss on pattern wafer, within chip SiN uniformity, and topography of CMP house and device areas using Atomic-force microscopy (AFM), Transmission electron microscopy (TEM), high resolution profiler (HRP) and KLA-Aleris. Those results of SiN within-chip uniformity show one step process (only slurry A_bulk + SiN stop) with poor process window, which cannot meet 7nm MOL integration process requirement. And two steps process (Slurry A_bulk + Slurry B_SiN stop) with promising results, good SiN within-chip uniformity (< 2nm) and wide process overpolish margin.
{"title":"SiOC CMP developed and implemented in 7nm and beyond","authors":"Haigou Huang, T. Chao, Ja-Hyung Han, D. Koli, Q. Fang","doi":"10.1109/CSTIC.2017.7919826","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919826","url":null,"abstract":"In this study, new SiOC Chemical Mechanical Planarization (CMP) process is fully developed with the characterization of the blanket wafer selectivity, SiN loss on pattern wafer, within chip SiN uniformity, and topography of CMP house and device areas using Atomic-force microscopy (AFM), Transmission electron microscopy (TEM), high resolution profiler (HRP) and KLA-Aleris. Those results of SiN within-chip uniformity show one step process (only slurry A_bulk + SiN stop) with poor process window, which cannot meet 7nm MOL integration process requirement. And two steps process (Slurry A_bulk + Slurry B_SiN stop) with promising results, good SiN within-chip uniformity (< 2nm) and wide process overpolish margin.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"7 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77013647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919834
Juan Wen, W. Chien, Guan Zhang, Yanhui Sun
In this paper, we develop a new via structure (FTV1), to study the reliability performance of SM (Stress Migration). FTV1 structure is different from the conventional Al-based interconnect technology. Here, the metal beneath the tungsten via is Cu (the conventional is Al), while the upper metal above the via is Al. The complex process of the FTV1(single via) combined with the interaction of the metal layer stresses results in that the SM resistance shift after 168hr baking has bi-modal issue. A new failure mechanism in W-plug via was reported in this paper. By changing the anneal step from before FTV1 photo to after passivation etch, the resistance shift becomes smaller than 2% versus the original 8%, which can meet industry specification.
{"title":"Improvement on the stress migration in tungsten-plug via","authors":"Juan Wen, W. Chien, Guan Zhang, Yanhui Sun","doi":"10.1109/CSTIC.2017.7919834","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919834","url":null,"abstract":"In this paper, we develop a new via structure (FTV1), to study the reliability performance of SM (Stress Migration). FTV1 structure is different from the conventional Al-based interconnect technology. Here, the metal beneath the tungsten via is Cu (the conventional is Al), while the upper metal above the via is Al. The complex process of the FTV1(single via) combined with the interaction of the metal layer stresses results in that the SM resistance shift after 168hr baking has bi-modal issue. A new failure mechanism in W-plug via was reported in this paper. By changing the anneal step from before FTV1 photo to after passivation etch, the resistance shift becomes smaller than 2% versus the original 8%, which can meet industry specification.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"210 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76111849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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